CN100505098C - Non-volatile semiconductor storage device - Google Patents
Non-volatile semiconductor storage device Download PDFInfo
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- CN100505098C CN100505098C CNB200410080720XA CN200410080720A CN100505098C CN 100505098 C CN100505098 C CN 100505098C CN B200410080720X A CNB200410080720X A CN B200410080720XA CN 200410080720 A CN200410080720 A CN 200410080720A CN 100505098 C CN100505098 C CN 100505098C
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Abstract
This invention relates to a nonvolatile semiconductor storage device, which can apply a first supply voltage VCC and a second supply VPP higher than the first in operation based on the application of one control grating in each storage unit transistor in the invented device. A second NMOS transistor is set between the first NMOS driving the control grating WL to the VCC and a control signal (/ER) connected to the grating of the VCC, the /ER is input into the source of the second NMOS and the drain of which is connected with the grating of the first NMOS parallel to a PMOS to form a transmission grating to drive said WL.
Description
Technical field
The present invention relates to a kind of Nonvolatile semiconductor memory devices, particularly relate to a kind of decoding circuit, be applicable to electric data Reprogrammable flash memory (reprogramable flash memory).
Background technology
Known that electric EEPROM is called as EEPROM (electrically erasableprogrammable semiconductor nonvolatile memory).A general EEPROM adopts stack architecture, and memory cell transistor wherein is to have a floating grid and a control grid.When erasing data, with one be higher than be used for general circuit power level (VCC) boost or the supercharging level (VPP: about 12V) be added in control grid (WL), electric charge pulled out or extracted out from the grid that flows, thereby at the floating gate inner control quantity of electric charge.That is, the quantity of electric charge in the floating gate reduces, when making power level (VCC) be added in control corresponding grid (WL), and the memory cell transistor conducting.
During reading of data, control grid (WL) is set as power level (VCC), and is for 1 or is 0 according to the conducting and the nonconducting state determination data of memory cell transistor.Two kinds of situations so just appear, wherein according to an operator scheme power level (VCC) be added in control grid (WL) and according to an operator scheme supercharging level (VPP) be added in be added in control grid (WL).
Fig. 1 is the block scheme of the control gate polar form decoding circuit of crowd erasable programmable EEPROM (batch erasable programmableEEPROM) or the sudden strain of a muscle EEPROM (flash EEPROM) that expresses one's gratification.Fig. 2～Fig. 5 is respectively the structured flowchart of interlock circuit in this decoding circuit.
Every demoder (XDEC and RXDEC) comprising: a logic gate (NA), and it is with each address decoder; An inverter (INV), the output of its input logic grid (NA); A transmission grid (CM00), its source electrode is connected with the output of inverter (INV), and its drain electrode is connected with its corresponding control grid (WL); One level shifter (LS0), the output of the output of its input logic grid (NA) and inverter (INV); And one the transmission grid (CM01), its source electrode is connected with the output of level shifter (LS0), and its drain electrode is connected with its corresponding control grid (WL).
Transmission grid (CM00) comprising: a PMOS transistor, its grid are set to the output (ER) of level shifter LS1; And a nmos pass transistor, its grid is set to the output (ER) of level shifter LS1.
Transmission grid (CM01) comprising: a PMOS transistor, its grid are set to the output (ER) of level shifter LS1; And a nmos pass transistor, its grid is set to the output (ER) of level shifter LS1.
Below be that following several sections describes to the division of operations of existing decoding circuit 1: read operation (a), erase operation for use (b), batch erase operation for use (c).
(a) read operation
When data by EEPROM (quickflashing EEPROM) when reading, control signal/CHIP is set to power level (VCC) and control signal ERASE is maintained at ground level (VSS).In the case, address signal A＜1:0〉be transfused to.Because this moment, control signal/CHIP was set at power level (VCC), supercharging power lead (VEP) adopts power level (VCC) and control signal ERASE to be set as ground level (VSS).Like this, the output ER of level shifter LS1 generation ground level (VSS) and its output/ER adopt power level (VCC).
The output of redundant element 10 (RDDEN, RA＜1:0〉and/RA＜1:0 〉) remain on a predetermined logic level respectively.That is, when not requiring redundancy replacement, RDDEN remains on ground level (VSS), and when requiring redundancy replacement, RDDEN remain on power level (VCC) and redundant discharge address date keep one with the control grid WL＜m that needs replacement (wherein m=0,1,2 and 3) corresponding current potential.
As Input Address signal A＜1:0〉time, predecode circuit 18 is with address signal A＜n〉(wherein n=0 and 1) be converted to complement address signal XA＜n (wherein n=0 and 1) and/XA＜n (wherein n=0 and 1) and with they output.
If the output RA＜n of redundant element 10〉value of (wherein n=0 and 1) is power level (VCC), so redundant definite circuit 12 is to corresponding redundant address RXA＜n〉(wherein n=0 and 1) OPADD signal XA＜n〉(wherein n=0 and 1), if and output RA＜n〉value of (wherein n=0 and 1) is ground level (VSS), so redundantly determines that circuit 12 is to corresponding redundant address RXA＜n〉(wherein n=0 and 1) OPADD signal/XA＜n〉(wherein n=0 and 1).
Promptly, when redundancy is determined the output RXA＜n of circuit 12〉when the value of (wherein n=0 and 1) is power level (VCC), RA＜n〉value of (wherein n=0 and 1) adopts power level (VCC) and address signal XA＜n〉(wherein n=0 and 1) brought to power level (VCC).The another kind of selection is/RA＜n〉value of (wherein n=0 and 1) adopts power level (VCC) and address signal/XA＜n〉(wherein n=0 and 1) adopt power level (VCC).Like this, Input Address A＜n〉(wherein n=0 and 1) and the redundant address RA＜n that discharges〉(wherein n=0 and 1) brought to consistent.
When about Input Address A＜1:0〉with the redundant address RA＜1:0 of release consistent information (according to XA＜1:0 to pre decoder 18 outputs〉and/XA＜1:0 and RXA＜1:0 of exporting of the definite circuit 12 of redundancy) when being sent to redundancy selector 14, redundancy selector is to all redundant address RXA＜1:0〉and redundancy replacement sign RDDEN carry out logical multiply operation, thereby whether decision requires redundancy replacement.When requiring redundancy replacement, this redundancy selector is respectively to RXEN and XEN out-put supply level (VCC) and ground level (VSS).When not requiring redundancy replacement, redundancy selector is respectively to RXEN and XEN output ground level (VSS) and power level (VCC).
Each demoder that constitutes decoder arrangements 50～58 all with address signal (XA＜0〉and/XA＜0) one of, one of address signal (XA＜1〉and/XA＜1 〉), and the output XEN of redundancy selector carries out the logical multiply operation, thereby selected control corresponding grid WL＜m〉(m=0 wherein, 1,2 and 3).Further, according to the selected corresponding Redundant Control grid of the output RXEN of redundancy selector.
For example, when not requiring redundancy replacement, be that XEN is that power level (VCC) and RXEN are when being ground level (VSS), with Input Address A＜1:0〉be sent to demoder by pre decoder 18, and will about whether requiring the determination result of redundancy replacement to be sent to each corresponding demoder by pre decoder 18 and redundant definite circuit 12, thereby select corresponding Input Address A＜1:0〉control grid WL＜m (wherein m=0,1,2 and 3).
When requiring redundancy replacement, be that XEN is that ground level (VSS) and RXEN are when being power level (VCC), will about the determination result that whether requires redundancy replacement by pre decoder 18, redundantly determine that circuit 12 and redundancy selector 14 are sent to each corresponding demoder, thereby select corresponding redundant control grid RWL.
Because so control grid WL＜3:0 about whether requiring the determination result of redundancy replacement to be sent to each corresponding demoder by pre decoder 18, redundant definite circuit 12 and redundancy selector 14 this moment〉be brought into and do not select.
In the demoder that drives selected control grid, the output of logic gate NA becomes ground level (VSS) by power level (VCC), and the output of inverter INV becomes power level (VCC) from ground level (VSS).Be respectively ground level (VSS) and power level (VCC) owing to constitute the transistorized signal ER of PMOS of transmission grid (CM00) and the signal/ER of the nmos pass transistor that constitutes transmission grid (CM00) this moment, selected control grid WL is configured the transistor driving of transmission grid (CM00) to power level (VCC).
In the aforesaid operations process, control signal ERASE keeps ground level (VSS), and the charge pump circuit 20 of having imported control signal ERASE provides power level (VCC) to supercharging power lead (VEP).
(b) erase operation for use
When the data in being stored in EEPROM (quickflashing EEPROM) were erased, one control signal/CHIP is set at power level (VCC) and a control signal ERASE is maintained at ground level (VSS).In this case, address signal A＜1:0〉be transfused to.Because control signal/CHIP of this moment is set at power level (VCC), supercharging power lead (VEP) adopts power level (VCC) and control signal ERASE to be set to ground level (VSS).Like this, the output ER of level shifter accepts ground level and its output/ER adopts power level (VCC).The output of redundant element 10 (RDDEN, RA＜1:0〉and/RA＜1:0 〉) remain on a predetermined logic level respectively.
When not requiring redundancy replacement, RDDEN remains on ground level (VSS).And when requiring redundancy replacement, RDDEN remains on power level (VCC), and the redundant address date that discharges remains on a control grid WL＜m corresponding to the replacement of needs〉voltage of (wherein m=0,1,2 and 3).
As Input Address signal A＜1:0〉time, predecode circuit 18 is with address signal A＜n〉(wherein n=0 and 1) be converted to complement address signal XA＜n (wherein n=0 and 1) and/XA＜n (wherein n=0 and 1) and with they output.
If the output RA＜n of redundant element 10〉value of (wherein n=0 and 1) is power level (VCC), so redundant definite circuit 12 is to corresponding redundant address RXA＜n〉(wherein n=0 and 1) OPADD signal/XA＜n〉(wherein n=0 and 1), if and output RA＜n〉value of (wherein n=0 and 1) is ground level (VSS), so redundantly determines that circuit 12 is to corresponding redundant address RXA＜n〉(wherein n=0 and 1) OPADD signal/XA＜n〉(wherein n=0 and 1).
When redundancy is determined the output RXA＜n of circuit 12〉when the value of (wherein n=0 and 1) is power level (VCC), RA＜n〉value of (wherein n=0 and 1) adopts power level (VCC) and address signal XA＜n〉(wherein n=0 and 1) brought to power level (VCC).The another kind of selection is/RA＜n〉value of (wherein n=0 and 1) adopts power level (VCC) and address signal/XA＜n〉(wherein n=0 and 1) adopt power level (VCC).Like this, Input Address A＜n〉(wherein n=0 and 1) and the redundant address RA＜n that discharges〉(wherein n=0 and 1) brought to consistent.
When about Input Address A＜1:0〉with the redundant address RA＜1:0 that discharges when consistent information is sent to redundancy selector 14 by pre decoder 18 and redundant definite circuit 12, redundancy selector is to all redundant address RXA＜1:0〉and redundancy replacement sign RDDEN carry out logical multiply operation, thereby whether decision requires redundancy replacement.When requiring redundancy replacement, this redundancy selector is respectively to RXEN and XEN out-put supply level (VCC) and ground level (VSS).When not requiring redundancy replacement, redundancy selector is respectively to RXEN and XEN output ground level (VSS) and power level (VCC).
Each demoder that constitutes decoder arrangements 16 all with address signal XA＜0 and/XA＜0 one of, one of address signal XA＜1〉and/XA＜1 〉, and the output XEN of redundancy selector 14 carries out the logical multiply operation, thereby select control corresponding grid WL＜m〉(m=0 wherein, 1,2 and 3).Further, according to the selected corresponding Redundant Control grid of the output RXEN of redundancy selector 14.
For example, when not requiring redundancy replacement, be that XEN is that power level (VCC) and RXEN are when being ground level (VSS), with Input Address A＜1:0〉be sent to demoder by pre decoder 18, and will about whether requiring the determination result of redundancy replacement to determine that by pre decoder 18 and redundancy circuit 12 and redundancy selector 14 are sent to each corresponding demoder, thereby select corresponding Input Address A＜1:0〉control grid WL＜m (wherein m=0,1,2 and 3).
When requiring redundancy replacement, be that XEN is that ground level (VSS) and RXEN are when being power level (VCC), will about the determination result that whether requires redundancy replacement by pre decoder 18, redundantly determine that circuit 12 and redundancy selector 14 are sent to each corresponding demoder, thereby select corresponding redundant control grid RWL.
Because so control grid WL＜3:0 about whether requiring the determination result of redundancy replacement to be sent to each corresponding demoder by pre decoder 18, redundant definite circuit 12 and redundancy selector 14 this moment〉be brought into and do not select.
When control signal ERASE then rises to power level (VCC) by ground level (VSS), the charge pump circuit 20 that has been transfused to control signal ERASE provides a built-up voltage (VPP) to its corresponding supercharging power lead (VEP), and the output/ER of level shifter (LS1) becomes ground level (VSS) and its output ER is switched to supercharging level (VPP).
Owing to provide supercharging level (VPP) to supercharging power lead (VEP), the output that drives the level shifter (LS1) of selected control grid in the demoder becomes supercharging level (VPP) and its output/EP is brought to ground level (VSS), thereby selected control grid is by corresponding level shifter (LS1) with transmit grid (CM01) and be driven to supercharging level (VPP).
(C) criticize erase operation for use
When the data of EEPROM (quickflashing EEPROM) are all erased, at first one control signal/CHIP is set at power level (VCC) and a control signal ERASE is remained on ground level (VSS).Because this control signal/CHIP this moment is set at power level (VCC) and this control signal ERASE remains on ground level (VSS), a built-up voltage line (VEP) adopts power level (VCC) and control signal ERASE to be set to ground level (VSS).Like this, the output ER of level shifter LS1 accepts ground level (VSS) and its output/ER adopts power level (VCC).The output of redundant element (RDDEN, RA＜1:0〉and/RA＜1:0 〉) keep a predetermined logic level respectively.
When not requiring redundancy replacement, RDDEN remains on ground level (VSS), and when requiring redundancy replacement, RDDEN remain on power level (VCC) and redundant discharge address date keep one with the control grid WL＜m that needs replacement (m=0 wherein, 1,2 and 3) corresponding current potential.
When control signal/CHIP was switched to ground level (VSS) in the case, predecode circuit 18 was to complement address signal XA＜n〉(wherein n=0 and 1) and/XA＜n (wherein n=0 and 1) out-put supply level (VCC).
Because complement address signal XA＜n〉(wherein n=0 and 1) and/XA＜n (wherein n=0 and 1) all be power level (VCC), redundant determine that circuit 12 is to redundant address RXA＜1:0〉out-put supply level (VCC), and do not depend on the output RA＜n of redundant element 10〉(wherein n=0 and 1).Because control signal/CHIP is electric Horizon (VSS), redundancy selector 14 is to XEN and RXEN out-put supply level (VCC).
On the other hand, each demoder that constitutes decoder arrangements 16 all with address signal XA＜0 and/XA＜0 one of, one of address signal XA＜1〉and/XA＜1 〉, and the output XEN of redundancy selector 14 carries out the logical multiply operation, thereby select control corresponding grid WL＜m〉(m=0 wherein, 1,2 and 3).Further, according to the selected corresponding Redundant Control grid RWL of the output RXEN of redundancy selector 14.But, all control grid WL＜3:0〉and Redundant Control grid RWL all chosen, all outputs of demoder and redundant decoder are all brought to power level (VCC).
In the demoder that drives selected control grid, the output of logic gate NA is transformed into ground level (VSS) by power level (VCC), the output of inverter INV is transformed into power level (VCC) by ground level (VSS), and the output of current potential shifter (LS0) is switched to power level (VCC).
When control signal ERASE then rises to power level (VCC) by ground level (VSS), charge pump circuit 20 provides a built-up voltage (VPP) to its corresponding supercharging power lead (VEP), and the output/ER of level shifter (LS1) becomes ground level (VSS) and its output ER is switched to supercharging level (VPP).
Owing to provide supercharging level (VPP) to supercharging power lead (VEP), the output that drives the level shifter (LS0) of selected control grid in the demoder becomes supercharging level (VPP) and its output/EP is brought to ground level (VSS), thereby selected control grid is by corresponding level shifter (LS0) with transmit grid (CM01) and be driven to supercharging level (VPP).
Because the control grid is driven to a supercharging level that is higher than the power level of circuit common (VPP: about 12V), all are connected to MOS transistor and supercharging power leads (VEP) of controlling grid all needs one greater than supercharging level (VPP: withstand voltage about 12V) in the data of EEPROM (quickflashing EEPROM) are erased.
Usually, thus the height endurability of MOS transistor be by thickening grid oxidation film and lengthening grid length discharge the MOS transistor associated terminal electric field realize.But consequent problem is that the driving force of MOS transistor descends.
In existing decoding circuit, current potential shifter (LS0 and LS1) and transmission grid (CM00 and CM01) are made up of height tolerance MOS transistor respectively.But the control grid is driven through transmission grid (CM00) when reading.Like this, the decline of driving force that each MOS transistor of transmission grid (CM00) will take place to constitute causes controlling the delay of grid operation.This postpones when the control grid (WL) that the lower P type MOS transistor of channel mobility drives rises obvious especially.
In the method that suppresses control grid rising delay, method is the width that increases the grid of each the P type MOS transistor that constitutes transmission grid (CM00), thereby guarantees to transmit the driving force of grid (CM00).But because transmission grid (CM00) needs long grid realizing the purposes of its height endurability, and each control grid all needs this transmission grid (CM00), so can't avoid the increase of area occupied.
No matter even be the control grid WL＜m that selectes〉(m=0 wherein, 1,2 and 3) or control grid WL＜m (m=0 wherein, 1,2 and 3) not chosen, whether existing decoding circuit needs to require definite result of redundancy replacement to be sent to corresponding demoder, except by transmission Input Address A＜n〉passage, also to pass through pre decoder, redundant definite circuit and redundancy selector.Therefore when read operation, in passage, can produce and postpone.
In existing decoding circuit, all control grids (WL＜3:0〉and RWL) batch all be driven to supercharging level (VPP) when erasing, and with whether require redundant discharge irrelevant.But, there is a kind of like this possibility: such as, as control grid WL＜m〉(wherein m=0,1,2 and 3) when sewing defective, control grid WL＜m that this kind sewed takes place〉(m=0 wherein, 1,2 and 3) can be driven to a supercharging level (VPP), cause like this because control grid WL＜m (m=0 wherein, 1,2 and 3) the decline of sewing caused supercharging level (VPP).
On the other hand, because defect Control grid WL＜m do not take place〉(m=0 wherein, therefore 1,2 and 3) also be driven to supercharging level (VPP), have supercharging level (VPP) even control grid WL＜i under the situation about descending (i ≠ also can not break down when m) having defective wherein.
Summary of the invention
At the problems referred to above the present invention is proposed.The objective of the invention is to, a kind of Nonvolatile semiconductor memory devices is provided, technical matters to be solved is to make it have faster reading speed and take littler area.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of Nonvolatile semiconductor memory devices that the present invention proposes, it comprises: memory cell transistor, each memory cell transistor all have a floating grid and a control grid (WL); The control grid (WL) of wherein said memory cell transistor according to a mode of operation when it is selected, accept one first level (VCC) and one second level (VPP), this second level (VPP) is higher than described first level, and wherein one first nmos pass transistor be set at second nmos pass transistor and control signal (/ER) between, the source electrode of a described NMOS be connected to described control signal (/ER), described control signal (/ER) be used to control one described control grid (WL) is driven into described second nmos pass transistor of described first level (VCC), the drain electrode of described first nmos pass transistor is connected to the grid of described second nmos pass transistor, and the grid of described first nmos pass transistor is connected to described first level (VCC), described second nmos pass transistor of one PMOS transistor AND gate is arranged in parallel, and described control grid (WL) is comprised described second nmos pass transistor and the transistorized transmission gate driving of described PMOS by one.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, in order to reach aforementioned goal of the invention, major technique of the present invention thes contents are as follows:
According to an aspect of the present invention, to achieve these goals, provide a kind of Nonvolatile semiconductor memory devices that constitutes by half memory cell transistor.Each memory cell transistor has a control grid, can adopt one first level (VCC) and to be higher than second level (VCC) of this first level when operation like this.The grid and of a nmos pass transistor be connected to this grid control signal (/provide one second nmos pass transistor between ER), this second nmos pass transistor should be controlled grid (WL) and drive to this first level (VCC).This control signal (/ER) import the source electrode of this second nmos pass transistor, and its drain electrode is connected to the grid of this first nmos pass transistor.A PMOS transistor in parallel with this first nmos pass transistor is set.One comprises those NMOS and the transistorized transmission gate driving control of PMOS grid (WL).
Via as can be known above-mentioned, the invention relates to a kind of Nonvolatile semiconductor memory devices, a kind of Nonvolatile semiconductor memory devices that can quicken storage speed and reduce area occupied is provided.All be provided with a control grid according to each memory cell transistor that is adopted in the Nonvolatile semiconductor memory devices of the present invention, can take one first level (VCC) and to be higher than second level (VPP) of this first level in operation.One will control the control signal that first nmos pass transistor and that grid (WL) is driven into this first level (VCC) is connected to the grid of this first level (VCC) (/be provided with one second nmos pass transistor between ER).The source electrode of this second nmos pass transistor be transfused to this control signal (/ER) and its drain electrode be connected with the grid of this first nmos pass transistor.This first nmos pass transistor is arranged in parallel a PMOS transistor.One this control grid (WL) of transmission gate driving that constitutes by described NMOS and PMOS transistor.
By technique scheme, Nonvolatile semiconductor memory devices of the present invention has following advantage at least:
As mentioned above, the nmos pass transistor that grid is biased to power level (VCC) be added in the grid of nmos pass transistor and control signal (/ER) between, the transmission grid (CM00) of drive controlling grid (WL) when this nmos pass transistor is formed read operation.Therefore, the voltage of grid that will constitute the nmos pass transistor of transmission grid (CM00) is set at and is greater than or equal to power level (VCC) and the side has high raceway groove percent of pass by comparing with the PMOS transistor nmos pass transistor will be controlled grid (WL) to be urged to power level (VCC) be possible.Like this, with control grid (WL) by the situation of PMOS transistor driving Comparatively speaking, the present invention can realize the acceleration of read operation and save area occupied.
Only import the data (RA that in redundant element, is programmed in advance and keeps, / RA and RDDEN) redundancy selector (RXSEL) carried and provide group relevant demoder (XDEC) respectively, and demoder is started and stops by the output of redundancy selector, thereby control corresponding door grid (WL) can not wait for that the definite result who whether requires redundancy replacement is just chosen.Like this, just may realize the acceleration of read operation and the raising of efficient, and because defective control grid (WL) is not biased to the raising that high voltage is realized reliability.
In sum, the Nonvolatile semiconductor memory devices of special construction of the present invention has reading speed faster, and takies the effect of littler area.It has above-mentioned plurality of advantages and practical value, and in like product, do not see have similar structural design to publish or use and really genus innovation, no matter it structurally or bigger improvement all arranged on the function, have technically than much progress, and produced handy and practical effect, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, disclose above-mentioned and other purposes and novel characteristics of the present invention below in conjunction with accompanying drawing more fully by detailed description to claim.
Description of drawings
Fig. 1 is the block scheme of existing decoding circuit structure.
Fig. 2 is the circuit diagram of existing redundancy selector inner structure.
Fig. 3 is the synoptic diagram that is used to illustrate a redundant element.
Fig. 4 is the circuit diagram that a redundancy is determined circuit inner structure.
Fig. 5 is the block scheme of the structure of existing decoder battle array.
Fig. 6 is the block scheme of the decoding circuit of an example according to the present invention.
Fig. 7 is the block scheme according to redundancy selector battle array structure of the present invention.
Fig. 8 is the block scheme according to demoder selector switch battle array structure of the present invention.
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of Nonvolatile semiconductor memory devices, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Below in conjunction with accompanying drawing most preferred embodiment of the present invention is specifically described.
Fig. 6 is the block scheme that shows control grid of the present invention (WL) type decoding circuit structure.Fig. 7 and Fig. 8 are respectively the related circuit block diagram that adopts in this decoding circuit.Redundant element and redundant definite circuit and prior art are similar.
Decoding circuit 60 of the present invention comprises: a predecode circuit 68, its Input Address signal A＜1:0〉and control signal/CHIP; One redundant element 10, its maintenance is also exported a redundancy replacement sign (RDDEN) and a redundant address (RA) that discharges, and is set to power level (VCC) when requiring redundancy replacement; One redundant determines circuit 12, the output of output of its input redundant element (RA＜1:0〉,/RA＜1:0 〉) and predecode circuit 68 (XA＜1:0〉,/XA＜1:0 〉); One redundancy selector battle array 64, the output of its input redundant element (RDDEN, RA＜1:0〉,/RA＜1:0 〉); One decoder arrangements 66, the output of the output of output (RDDEN), the redundancy selector battle array 64 of its input redundant element 10 (XEN＜3:0 〉), the redundant output of determining circuit 12 (RXA＜1:0 〉), predecode circuit 68 (XA＜1:0 〉, / XA〉1:0 〉), and a control signal ERASE; Also comprise a charge pump circuit 70, the power level (VCC) of its responsive control signal ERASE provides to a supercharging power lead (VEP) and boosts or supercharging level (VPP) and the ground level (VSS) that responds ERASE provide power level (VCC) to the supercharging power lead (VEP) corresponding with it.
The redundant battle array 64 of selecting comprises: most redundancy selectors, each redundancy selector input and output RA＜0〉and RA/＜0 in one, export RA＜0 and RA/＜0 in one, and RDDEN.
Decoder arrangements 66 comprises most demoders (XDEC), output XA＜0 of each demoder (XDEC) input predecode circuit〉and/XA＜0 in one, export XA＜1〉and/XA＜1 in one, and the output XEN＜m of respective redundant selector switch (m=0 wherein, 1,2 and 3); One redundant decoder (RXDEC), the redundant output RXA＜1:0 that determines circuit 12 of its input〉and the output RDDEN of redundant element 10; And a level shifter (LS1), its input control signal (ERASE).
Each demoder (XDEC and RXDEC) comprising: a logic gate (NA), with each address decoder; One inverter (INV), the output of its input logic grid (NA); One transmission grid (CM00), its source electrode are connected with the output of inverter (INV) and drain and be connected with control grid (WL); One level shifter (LS0), the output of the output of its input logic grid (NA) and inverter (INV); Output and drain electrode that one transmission grid (CM01), its source electrode are set to be connected to level shifter (LS0) are set to be connected to control grid (WL); And a nmos pass transistor (NM0), its source electrode be set to level shifter LS1 output (/ER), and its grid is to supply voltage (VCC).
Transmission grid (CM00) comprising: a PMOS transistor, the output (ER) of its grid and level shifter LS1; One nmos pass transistor, its grid is connected with the drain electrode of nmos pass transistor (NMO).
Transmission grid (CM01) comprising: a PMOS transistor, the output of its grid and level shifter LS1 (/ER) be connected; One nmos pass transistor, its grid is connected with the output (ER) of level shifter LS1.
Followingly according to an example operation of this decoding circuit is divided into following a few part and describes: read operation (a), erase operation for use (b) and batch erase operation for use (c).
(a) read operation
When data by EEPROM (quickflashing EEPROM) when reading, control signal/CHIP is set to power level (VCC) and control signal ERASE is maintained at ground level (VSS).In the case, address signal A＜1:0〉be transfused to.Because this moment, control signal/CHIP was set at power level (VCC), supercharging power lead (VEP) adopts power level (VCC) and control signal ERASE to be set as ground level (VSS).Like this, the output ER of level shifter LS1 accepts ground level (VSS) and its output/ER adopts power level (VCC), and the grid that constitutes the nmos pass transistor of transmission grid (CM00) is brought to a voltage (VCC-Vt) that is lower than power level (VCC) by a threshold voltage.
The output of redundant element 10 (RDDEN, RA＜1:0〉and/RA＜1:0 〉) and definite logic level XEN＜3:0, remain on a predetermined logic level respectively based on the output of redundant element.
When not requiring redundancy replacement (RDDEN remains on ground level (VSS)), all output XEN＜3:0〉all kept power level (VCC) respectively.And when requiring redundancy replacement (RDDEN remains on power level (VCC)), one control grid WL＜m corresponding to the unit that requires to replace〉(m=0 wherein, 1,2 and 3) m=0 of corresponding output XEN＜wherein, 1,2 and 3〉remain on ground level (VSS), and other output (is that XEN (i) (wherein i ≠ m)) keeps power level (VCC).
In this case, as Input Address signal A＜1:0〉time, predecode circuit 68 is with address signal A＜n〉(wherein n=0 and 1) be converted to complement address signal XA＜n (wherein n=0 and 1) and/XA＜n (wherein n=0 and 1) and with they output.If the output RA＜n of redundant element 10〉value of (wherein n=0 and 1) is power level (VCC), so redundant definite circuit 12 OPADD signal/XA＜n〉(wherein n=0 and 1), if and output RA＜n〉(wherein n=0 and 1) when being ground level (VSS), so redundant definite circuit 12 is to corresponding redundant address RXA＜n〉(wherein n=0 and 1) OPADD signal/XA＜n〉(wherein n=0 and 1).
As redundant address RXA＜n〉when the value of (wherein n=0 and 1) is power level (VCC), RA＜n〉value of (wherein n=0 and 1) adopts power level (VCC) and address signal XA＜n〉(wherein n=0 and 1) be set to power level (VCC).The another kind of selection is/RA＜n〉value of (wherein n=0 and 1) adopts power level (VCC) and address signal/XA＜n〉(wherein n=0 and 1) adopt power level (VCC).Like this, Input Address A＜n〉(wherein n=0 and 1) and the redundant address RA＜n that discharges〉(wherein n=0 and 1) brought to consistent.
On the other hand, each demoder (XDEC＜0:3 〉) that constitutes decoder arrangements 66 all with address signal XA＜0 and/XA＜0 one of, one of address signal XA＜1〉and/XA＜1 〉, and the output XEN＜m of redundancy selector battle array〉m=0 wherein, 1,2 and 3) carry out logical multiply operation, thereby select control corresponding grid WL＜m (m=0 wherein, 1,2 and 3).Demoder RXDEC determines the output RXA＜1:0 of circuit 12 to redundancy〉and the output RDDEN of redundant element 10 carry out the logical multiply operation, thereby selected corresponding Redundant Control grid RWL.
When not requiring redundancy replacement, be that RDDEN is ground level (VSS) or Input Address A＜1:0〉discharge address RA＜1:0 with the redundancy that remains in the redundant element〉when inconsistent, with Input Address A＜1:0〉be sent to demoder by pre decoder 68, thereby selected corresponding Input Address A＜1:0〉control grid WL＜m (m=0 wherein, 1,2 and 3).
When requiring redundancy replacement, be that RXEN is power level (VCC) and Input Address A＜1:0〉be retained in redundant element 10 in the redundant address RA＜1:0 of release consistent, about Input Address A＜1:0〉with the redundant address RA＜1:0 that discharges corresponding to information is sent to corresponding redundant decoder, corresponding like this Redundant Control grid RWL is chosen.Owing to remain in the redundant element 10 the redundant address RA＜1:0 of release this moment〉already by redundancy selector RXSEL＜m〉(m=0 wherein, 1,2 and 3) be sent to demoder XDEC＜m〉(m=0 wherein, 1,2 and 3), corresponding to Input Address A＜1:0〉control grid WL＜m (wherein m=0,1,2 and 3) not chosen.
In the demoder that drives selected control grid, the output of logic gate NA becomes ground level (VSS) by power level (VCC).Like this, the output of inverter INV becomes power level (VCC) from ground level (VSS).Separated from/ER by a nmos pass transistor NM0 owing to constitute the grid of the nmos pass transistor of transmission grid (CM00) this moment, its grid is boosted to the voltage that is approximately 2*VCC-Vt certainly.
Nmos pass transistor and PMOS transistor driving that the control grid of selected unit is configured transmission grid (CM00) arrive power level (VCC).
Can also remove the PMOS transistor that constitutes transmission grid (CM00).But grid voltage from the nmos pass transistor that boosts is considered to descend in time owing to having carried out, and preferably this point can be used in combination, and will control grid and remain on power level (VCC).
During aforesaid operations, control signal ERASE remains on ground level (VSS), and the charge pump circuit of having imported control signal ERASE provides power level (VCC) to supercharging power lead (VEP).
(b) erase operation for use
When the data in being stored in EEPROM (quickflashing EEPROM) were erased, one control signal/CHIP is set at power level (VCC) and a control signal ERASE is maintained at ground level (VSS).In this case, address signal A＜1:0〉be transfused to.Because control signal/CHIP of this moment is set at power level (VCC), supercharging power lead (VEP) adopts power level (VCC) and control signal ERASE to be set to ground level (VSS).Like this, the output ER of level shifter LS1 accepts ground level and its output/ER adopts power level (VCC), and the grid that constitutes the nmos pass transistor of transmission grid (CM00) is brought to a voltage (VCC-Vt) that is lower than power level (VCC) by a threshold voltage.
The output of redundant element 10 (RDDEN, RA＜1:0〉and/RA＜1:0 〉) and based on the XEN＜3:0 of definite logic level of redundant element output remain on a predetermined logic level respectively.
When not requiring redundancy replacement (RDDEN remains on ground level (VSS)), all output XEN＜3:0〉all kept power level (VCC) respectively.And when more asking superfluous She to replace (RDDEN is power level (VCC)), the one control grid WL＜m that replaces corresponding to needs〉(m=0 wherein, 1,2 and 3) m=0 of corresponding output XEN＜wherein, 1,2 and 3〉remain on ground level (VSS), and other output (is that XEN (i) (wherein i ≠ m)) keeps power level (VCC).
In this case, as Input Address signal A＜1:0〉time, predecode circuit 68 is with address signal A＜n〉(wherein n=0 and 1) be converted to complement address signal XA＜n (wherein n=0 and 1) and/XA＜n (wherein n=0 and 1) and thus with they output.
If the output RA＜n of redundant element 10〉value of (wherein n=0 and 1) is power level (VCC), so redundant definite circuit 12 is to corresponding redundant address RXA＜n〉(wherein n=0 and 1) OPADD signal/XA＜n〉(wherein n=0 and 1), if and output RA＜n〉when the value of (wherein n=0 and 1) is ground level (VSS), so redundantly determine that circuit 12 is to corresponding redundant address RXA＜n〉(wherein n=0 and 1) OPADD signal/XA＜n〉(wherein n=0 and 1).
That is, as redundant address RXA＜n〉in n=0 and 1) value when being power level (VCC), RA＜n〉value of (wherein n=0 and 1) adopts power level (VCC) and address signal XA＜n (wherein n=0 and 1) brought to power level (VCC).The another kind of selection is/RA＜n〉n=0 and 1 wherein) value adopt power level (VCC) and address signal/XA＜n (wherein n=0 and 1) adopt power level (VCC).Like this, Input Address A＜n〉in n=0 and 1) and the redundant address RA＜n that discharges (wherein n=0 and 1) quilt brought to consistent.
On the other hand, each demoder (XDEC＜0:3 〉) that constitutes decoder arrangements 66 all with address signal XA＜0 and/XA＜0 one of, one of address signal XA＜1〉and/MA＜1 〉, and the output KEN＜m of redundancy selector battle array 64〉(m=0 wherein, 1,2 and 3) carry out logical multiply operation, thereby select control corresponding grid WL＜m (m=0 wherein, 1,2 and 3).Demoder RXDEC determines the output RXA＜1:0 of circuit 12 to redundancy〉and the output RDDEN of redundant element 10 carry out the logical multiply operation, thereby selected corresponding Redundant Control grid RWL.
When not requiring that superfluous She replaces, be that RDDEN is ground level (VSS) or Input Address A＜1:0〉discharge address RA＜1:0 with the redundancy that remains on redundant element〉when inconsistent, with Input Address A＜1:0〉be sent to corresponding demoder, thereby selected corresponding Input Address A＜1:0〉control grid WL＜m (m=0 wherein, 1,2 and 3).When requiring redundancy replacement, be that RDDEN is power level (VCC) and Input Address A＜1:0〉be retained in the redundant address RA＜1:0 of release in the redundant element consistent, about Input Address A＜1:0〉with the redundant address RA＜1:0 of release corresponding to information is by pre decoder 68 and redundantly determine that circuit 12 is sent to corresponding redundant decoder, corresponding like this Redundant Control grid RWL is chosen.
Owing to remain in the redundant element 10 the redundant address RA＜1:0 of release this moment〉early be sent to demoder XDEC＜m (wherein m=0,1,2 and 3), corresponding to Input Address A＜1:0〉control grid WL＜m (wherein m=0,1,2 and 3) not chosen.
In the demoder that drives selected control grid, the output of logic gate NA becomes ground level (VSS) by power level (VCC).The output of inverter INV is converted to power level (VCC) from ground level (VSS), and the output of level shifter (LS0) becomes power level (VCC).
When control signal ERASE then rises to power level (VCC) by ground level (VSS), the charge pump circuit that has been transfused to control signal ERASE provides a built-up voltage (VPP) to its corresponding supercharging power lead (VEP), and the output/ER of level shifter (LS1) becomes ground level (VSS) and its output ER is switched to supercharging level (VPP).
Owing to provide supercharging level (VPP) to supercharging power lead (VEP), the output that drives the level shifter (LS0) of selected control grid in the demoder becomes supercharging level (VPP) and its output/EP is brought to ground level (VSS), thereby selected control grid is by corresponding level shifter (LS0) with transmit grid (CM01) and be driven to supercharging level (VPP).
(C) criticize erase operation for use
When the data of EEPROM (quickflashing EEPROM) are all erased, at first one control signal/CHIP is set at power level (VCC) and a control signal ERASE is remained on ground level (VSS).Because this moment, this control signal/CHIP was set at power level (VCC), a built-up voltage line (VEP) adopts power level (VCC) and control signal ERASE to be set to ground level (VSS).Like this, the output ER of level shifter LS1 accepts ground level (VSS) and its output/ER adopts power level (VCC).
The output of redundant element 10 (RDDEN, RA＜1:0〉and/RA＜1:0 〉) and the output XEN＜3:0 of definite logic level keep a predetermined logic level respectively based on the output of redundant element.
When not requiring redundancy replacement (RDDEN remains on ground level (VSS)), all output XEN＜3:0〉maintained power level (VCC) respectively.And when requiring redundancy replacement (RDDEN remains on power level (VCC)), one need to replace corresponding to a control grid WL＜m (m=0 wherein, 1,2 and 3) output XEN＜m〉(m=0 wherein, 1,2 and 3) remain on ground level (VSS), and other outputs, i.e. XEN＜i〉(wherein i ≠ m) keeps power level (VCC).
When control signal/CHIP was switched to ground level (VSS) in the case, predecode circuit 68 was to complement address signal XA＜n〉(wherein n=0 and 1) and/XA＜n (wherein n=0 and 1) out-put supply level (VCC).
Because complement address signal XA＜n〉(wherein n=0 and 1) and/XA＜n (wherein n=0 and 1) all be power level (VCC), redundant determine that circuit 12 is to redundant address RXA＜1:0〉out-put supply level (VCC), and do not depend on the output RA＜n of redundant element〉(wherein n=0 and 1).
Each demoder (XDEC＜0:3 〉) is all to address signal XA＜0〉(/XA＜0 〉) and XA＜1〉the output XEN＜m of (/XA＜1 〉) and redundancy selector 64〉(m=0 wherein, 1,2 and 3) carry out the logical multiply operation, thereby drive control corresponding grid WL＜m〉(m=0 wherein, 1,2 and 3).
Redundant decoder (RXDEC) is determined the output RXA＜1:0 of circuit 12 to redundancy〉and the output RDDEN of redundant element 10 carry out the logical multiply operation, thereby drive corresponding Redundant Control grid RWL.
Because in this case, address signal XA＜1:0〉and/XA＜1:0〉all be power level (VCC) and redundant address RXA＜1:0 power level also be in, all control grid WL＜3:0〉all do not require under the situation of redundancy replacement chosen, promptly, RDDEN is ground level (VSS), and all XEN＜3:0〉all be power level (VCC).When requiring redundancy replacement, be that RDDEN is when being power level (VCC), the one control grid WL＜m that replaces corresponding to needs〉(m=0 wherein, 1,2 and 3) output XEN＜m〉(wherein m=0,1,2 and 3) be ground level (VSS), and other export XEN＜i〉(wherein i ≠ m) is a power level, corresponding control grid WL＜i〉(wherein i ≠ m) and Redundant Control grid are chosen.
In the demoder that drives selected control grid, the output of logic gate NA is transformed into ground level (VSS) by power level (VCC), the output of inverter INV is transformed into power level (VCC) by ground level (VSS), and the output of current potential shifter (LS0) is become power level (VCC).
When control signal ERASE then rises to power level (VCC) by ground level (VSS), the charge pump circuit 70 of input control signal ERASE provides a built-up voltage (VPP) to its corresponding supercharging power lead (VEP), and the output/ER of level shifter (LS1) is become ground level (VSS) and its output ER is switched to supercharging level (VPP).
Owing to provide supercharging level (VPP) to supercharging power lead (VEP), the output that drives the level shifter (LS0) of selected control grid in the demoder is converted into supercharging level (VPP) and its output/EP is brought to ground level (VSS), thereby selected control grid is by corresponding level shifter (LS0) with transmit grid (CM01) and be driven to supercharging level (VPP).
As mentioned above, the nmos pass transistor that grid is biased to power level (VCC) be added in the grid of nmos pass transistor and control signal (/ER) between, the transmission grid (CM00) of drive controlling grid (WL) when this nmos pass transistor is formed read operation.Therefore, the voltage of grid that will constitute the nmos pass transistor of transmission grid (CM00) is set at and is greater than or equal to power level (VCC) and the side has high raceway groove percent of pass by comparing with the PMOS transistor nmos pass transistor will be controlled grid (WL) to be urged to power level (VCC) be possible.Like this, with control grid (WL) by the situation of PMOS transistor driving Comparatively speaking, the present invention can realize the acceleration of read operation and save area occupied.
Only import the data (RA that in redundant element, is programmed in advance and keeps, / RA and RDDEN) redundancy selector (RXSEL) carried and provide group relevant demoder (XDEC) respectively, and demoder is started and stops by the output of redundancy selector, thereby control corresponding door grid (WL) can not wait for that the definite result who whether requires redundancy replacement is just chosen.Like this, just may realize the acceleration of read operation and the raising of efficient, and because defective control grid (WL) is not biased to the raising that high voltage is realized reliability.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (1)
1, a kind of Nonvolatile semiconductor memory devices is characterized in that it comprises:
Memory cell transistor, each memory cell transistor all have a floating grid and a control grid (WL);
The control grid (WL) of wherein said memory cell transistor when it is selected, is accepted one first level (VCC) and one second level (VPP) according to a mode of operation, and this second level (VPP) is higher than described first level, and
Wherein one first nmos pass transistor be set at second nmos pass transistor and control signal (/ER) between, the source electrode of a described NMOS be connected to described control signal (/ER), described control signal (/ER) be used to control one described control grid (WL) is driven into described second nmos pass transistor of described first level (VCC), the drain electrode of described first nmos pass transistor is connected to the grid of described second nmos pass transistor, and the grid of described first nmos pass transistor is connected to described first level (VCC), described second nmos pass transistor of one PMOS transistor AND gate is arranged in parallel, and described control grid (WL) is comprised described second nmos pass transistor and the transistorized transmission gate driving of described PMOS by one.
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