CN100502003C - Semiconductor device structure - Google Patents
Semiconductor device structure Download PDFInfo
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- CN100502003C CN100502003C CNB2006101606512A CN200610160651A CN100502003C CN 100502003 C CN100502003 C CN 100502003C CN B2006101606512 A CNB2006101606512 A CN B2006101606512A CN 200610160651 A CN200610160651 A CN 200610160651A CN 100502003 C CN100502003 C CN 100502003C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims description 41
- 239000012212 insulator Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 3
- 210000000003 hoof Anatomy 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 description 15
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 108010004350 tyrosine-rich amelogenin polypeptide Proteins 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a structure of high-voltage semiconductor device, which comprises a drain structure which is provided with two open-mouth structures that are insulatively close to each other and cross embedded, a source electrode structure, a drain extending structure and a grid electrode structure that are formed between the embedded places. The generation of electrode terminals with small radius of curvature is avoided through the cross-embedded opend-mouth structures, and the local electric field accumulating effect is eliminated to improve the breakdown voltage. Meanwhile, not only the breakover resistance is reduced through a configuration of the cross-embedded structures, but also the space is effectively utilized, and thus the accumulating degree of the semiconductor device on the chip is improved to meet the needs of the miniaturized electronic device.
Description
Technical field
The present invention relates to a kind of semiconductor device structure, the device architecture of particularly a kind of Laterally Diffused Metal Oxide Semiconductor (LDMOS).
Background technology
Laterally Diffused Metal Oxide Semiconductor (LDMOS) device often is applied under the high voltage operation environment, for example power amplifier of high power and high band, or the high-power component of base station.The feature of LDMOS is to have high-tension resistance characteristics, but resistance to compression is tens of to hundreds of volts, main cause is that LDMOS has low-doped drift extension area in the drain electrode extended structure, can be in order to relaxing the breakdown effects between drain electrode end and the source terminal, thereby make device have higher puncture voltage (breakdown voltage).For making LDMOS obtain higher puncture voltage, therefore must improve at the structure of device.
See also Figure 1A and Figure 1B, be respectively the allocation plan and the profile of prior art Laterally Diffused Metal Oxide Semiconductor (LDMOS) device architecture.Shown in Figure 1A, traditional Laterally Diffused Metal Oxide Semiconductor 10 structures comprise one source pole structure 11, a drain electrode structure 12, a drain electrode extended structure 13 and a grid structure 14.
Shown in Figure 1B, be the profile of Figure 1A along the I-I line.Source configuration 11 comprises and is formed at substrate such as P type substrate 15 lip-deep source electrodes 16; Be formed in the P type substrate 15 and be positioned at p type trap 17 under the source electrode 16, wherein be doped with the P-type conduction ion; Be formed at the n in the p type trap 17
+Type doped region 18 is for having a zone of high-dopant concentration N type conductive ion; Be formed in the p type trap 17 and and n
+The p+ type doped region 19 that type doped region 18 is adjacent is for having a zone of high-dopant concentration p type conductive ion.Wherein, n+ type doped region 18 all is connected with source electrode 16 with p+ type doped region 19.
Comprise n type drift extension area 23 in the drain electrode extended structure 13, and be formed at the p type doped region 24 in the n type drift extension area 23 with low doping concentration N type conductive ion.Wherein, the n type drift extension area 23 of drain electrode extended structure 13 and the n of source configuration 11
+18 of type doped regions have a predeterminable range, in order to form an effect channel region 27.
In the above-mentioned LDMOS structure, source electrode protuberance 11 ' has the tip 111 of a small curvature radius, the phenomenon that easy generation electric charge gathers makes by the electric field strength at this position comparatively strong, cause Electric Field Distribution inequality between an effect channel region, when operating in condition of high voltage following time, to form breakdown effects because of the effect of electric field local accumulation, reduce the puncture voltage of LDMOS.Do not make this protuberance 11 ' influence its device electric breakdown strength as desiring, this radius of curvature must be become big, yet this measure but makes the integral device area become big, the relative conducting resistance (Rdson) that makes uprises, and reduces the integration of device on the chip.
To sum up, gather, cause electric-field intensity distribution inequality between an effect raceway groove, thereby the situation that causes puncture voltage to reduce produces owing to the electrode terminal that has small curvature radius in the prior art easily forms electric charge.
Summary of the invention
Technical problem to be solved by this invention is, a kind of semiconductor device structure with high-breakdown-voltage is provided, and not only has the integration that low on-resistance also can improve chip semiconductor-on-insulator device simultaneously, to satisfy the requirement of microminiaturized electronic device.
Semiconductor device structure of the present invention comprises a substrate, a drain electrode structure, drain electrode extended structure, one source pole structure and a grid structure.
Drain electrode structure is formed on the substrate and has two opening shape structures of the staggered phase embedding of property insulated from each other ground next-door neighbour, these two opening shape structures define three kinds of different zones between interdigitating section, to set the structure of difference in functionality, it has two first areas, two second areas and one the 3rd zone respectively, wherein the first area is adjacent with opening shape structure, second area then is close to the first area, and the 3rd zone is then between above-mentioned two second areas.In addition, each opening shape structure all comprises one first trap, one first doped region and a drain electrode.Drain electrode is formed on the substrate surface; First doped region then is formed in the substrate of drain electrode below, is a zone that is doped with conductive ion of extending from substrate surface downwards, and is connected with drain electrode; First trap then is formed in the substrate and centers on first doped region, and first trap is formed by the regional of conductive doped ion.
The drain electrode extended structure is formed in the substrate and is positioned at the first area, and it comprises one and has the drift extension area of conductive ion, and the extension area that drifts about is adjacent with first trap.
Source configuration is formed in the substrate and is positioned at the 3rd zone.Source configuration comprises one second trap, at least one second doped region and one source pole electrode.Source electrode is formed on the substrate, and is connected with second doped region in being formed at its lower substrate, and second trap is then around the periphery of second doped region.All be doped with conductive ion in second trap and second doped region.
Grid structure is formed on the substrate and is positioned at second area, and an effect of its below formation channel region, and the transmission grating electrode structure can be imitated the on off state of channel region in order to controlling filed.Grid structure comprises a gate insulator and a gate electrode, and wherein, gate insulator is formed on the substrate surface of imitating the channel region top, and gate electrode then is covered on the gate insulator.
Compared with prior art, by semiconductor device structure of the present invention, can avoid producing between source configuration and drain electrode structure the phenomenon that most advanced and sophisticated electric field gathers, effectively improve the puncture voltage of semiconductor device, and through having the drain electrode structure configuration of phase embedding opening shape structure each other, to reduce conducting resistance, even fully represent space utilization efficient, promote the integration of chip semiconductor-on-insulator device, to meet the requirement of microminiaturized electronic device.
Description of drawings
Figure 1A is the allocation plan of prior art LDMOS device architecture;
Figure 1B is the profile of prior art LDMOS device architecture;
Fig. 2 A is the allocation plan of semiconductor device structure preferred embodiment of the present invention;
Fig. 2 B is the profile of semiconductor device structure preferred embodiment of the present invention;
Fig. 3 is the extended structure schematic diagram of semiconductor device of the present invention; And
Fig. 4 is another extended structure schematic diagram of semiconductor device of the present invention.
Wherein, Reference numeral is:
10 Laterally Diffused Metal Oxide Semiconductor
11,31,51,61 source configuration
11 ' protuberance
12,32,52,62 drain electrode structures
13,33 drain electrode extended structures
14,34 grid structures
15,35 P type substrates
16,42 source electrodes
17,43 p type traps
18,22,37,44 n
+The type doped region
19,45 p
+The type doped region
20,36 drain electrodes
21,38 n type traps
23,39 n types drift extension area
24,40 p type doped regions
25,47 gate insulators
26,46 gate electrodes
30 high-voltage semi-conductors
41, imitate channel region for 27
48 insulating barriers
111 tips
Embodiment
See also Fig. 2 A, be the allocation plan of semiconductor device structure of the present invention.Semiconductor 30 device architectures comprise a drain electrode structure 32, drain electrode extended structure 33, one source pole structure 31 and a grid structure 34.
See also Fig. 2 B, be the profile of Fig. 2 A along the II-II line.Shown in Fig. 2 B, each opening shape structure comprises a drain electrode 36, a n
+A type doped region 37 and a n type trap 38.Drain electrode 36 is formed on the substrate as P type substrate 35; n
+Type doped region 37 extends the formed zone of a predeterminable range downwards by drain electrode 36 and P type substrate 35 contact surfaces, wherein is doped with the N type conductive ion of high concentration; 38 of n type traps are to be formed in the P type substrate 35 and to be centered around n
+The periphery of type doped region 37.In addition, though two opening shape structures are the absolute construction that is separated from each other, 36 of its drain electrodes can weld (wire bonding) by outside lead and are connected with each other.
Drain electrode extended structure 33 is arranged in the first area, and it comprises a n type drift extension area 39 and a p type doped region 40.The zone that n type drift extension area 39 and n type trap 38 are adjacent wherein is doped with the N type conductive ion of low concentration; 40 of p type doped regions are formed in 39 region surrounded of n type drift extension area and a zone of extending from P type substrate 35 surfaces downwards, in addition, are doped with the P-type conduction ion in the p type doped region 40.
In addition, drain electrode structure 32, source configuration 31 are formed with insulating barrier 48 as silicon oxide layer to each other with gate structure 34, in order to guarantee the effect that is electrically insulated, in order to avoid produce short circuit phenomenon between each structure.
As shown in Figure 3, be the extended structure schematic diagram of semiconductor device of the present invention.Drain electrode structure 52 is formed the configuration kenel of phase embedding each other by the opening shape structure of S shape, and still comprise in the drain electrode structure 52 herein and be centered around drain electrode structure 52 drain electrode extended structure on every side, source configuration 51 then is formed between the zone of interdigitating section, also presents S shape configuration kenel.Grid structure (figure do not show) then is disposed at 51 of drain electrode structure 52 and source configuration.
As shown in Figure 4, be another extended structure schematic diagram of semiconductor device of the present invention.Drain electrode structure 62 is by the phase embedding and forming each other of the opening shape structure of two flat pectinations, and drain electrode structure 62 still comprises the drain electrode extended structure that is centered around around the drain electrode structure 62, source configuration 61 then is formed at the interregional of interdigitating section, presents end to end continuous S-shaped configuration kenel.Grid structure (figure do not show) then is disposed at 61 of drain electrode structure 62 and source configuration.
By above-mentioned semiconductor device structure configuration, between drain electrode structure, have source configuration with the embedding of opening shape phase, make source electrode no longer have the edge of small curvature radius, and then get rid of in the generation prior art because the phenomenon of the most advanced and sophisticated electric field local accumulation of source electrode protuberance, therefore, source configuration is imitated channel region with formed of drain electrode extended structure and is had uniform electric field distribution, effectively improves semi-conductive puncture voltage.Simultaneously, see through the special opening shape phase scarf of drain electrode structure and put, device is had than low on-resistance, more can reach the effectively effect of utilization of space, promote the integration of chip semiconductor-on-insulator device, with electronic device manufacturing technology in response to high storage capacity.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (11)
1. a semiconductor device structure is characterized in that, includes:
One substrate;
One drain electrode structure, two opening shape structures by the staggered phase embedding of property insulated from each other ground next-door neighbour are formed on this substrate, and define two first areas between this of interdigitating section two opening shape structures, two second areas and one the 3rd zone, wherein this first area is close to this opening shape structure, this second area is close to this first area, the 3rd zone is between between this two second area, respectively this opening shape structure comprises one first trap, one first doped region and a drain electrode, this drain electrode is formed on this substrate, this first doped region is formed in this substrate of this drain electrode below and with this drain electrode and is connected, and this first trap is formed in this substrate and around this first doped region;
One drain electrode extended structure is formed in this substrate and is positioned at this first area, and this drain electrode extended structure has a drift extension area, and this extension area that drifts about is adjacent with this first trap;
The one source pole structure, be formed in this substrate and be positioned at the 3rd zone, this source configuration comprises one second trap, at least one second doped region and one source pole electrode, wherein this source electrode is formed on this substrate, this at least one second doped region is formed in this substrate of this source electrode below and with this source electrode and is connected, and this second trap is formed in this substrate and around this at least one second doped region; And
One grid structure is formed on this substrate and is positioned at this second area, and it comprises a gate insulator and a gate electrode, and this grid structure below forms one and imitates channel region.
2. semiconductor device structure according to claim 1 is characterized in that, wherein has an insulating barrier between this grid structure and adjacent this drain electrode structure and this source configuration.
3. semiconductor device structure according to claim 1 is characterized in that, wherein is doped with N type conductive ion in this first trap, and is doped with N type conductive ion in this first doped region.
4. semiconductor device structure according to claim 1 is characterized in that, wherein is doped with N type conductive ion in this drift extension area.
5. semiconductor device structure according to claim 1 is characterized in that, wherein this drift extension area also comprises at least one the 3rd doped region, is doped with the P-type conduction ion in this at least one the 3rd doped region.
6. semiconductor device structure according to claim 1 is characterized in that, wherein is doped with the P-type conduction ion in this second trap.
7. semiconductor device structure according to claim 1 is characterized in that, wherein includes several second doped regions, is doped with N type or P-type conduction ion, and this second doped region adjacent one another are different conductive ion kenels of mixing.
8. semiconductor device structure according to claim 1 is characterized in that, wherein this drain electrode of this two openings shape structure can be by the outside lead solder joint.
9. semiconductor device structure according to claim 1 is characterized in that, wherein this opening shape structure is a shape of a hoof or U-shaped structure.
10. semiconductor device structure according to claim 1 is characterized in that, wherein this opening shape structure is a S shape or flat pectinate texture.
11. semiconductor device structure according to claim 10 is characterized in that, wherein this source configuration is a S shape or the S shape structure of joining continuously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101606512A CN100502003C (en) | 2006-11-29 | 2006-11-29 | Semiconductor device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101606512A CN100502003C (en) | 2006-11-29 | 2006-11-29 | Semiconductor device structure |
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| Publication Number | Publication Date |
|---|---|
| CN101192610A CN101192610A (en) | 2008-06-04 |
| CN100502003C true CN100502003C (en) | 2009-06-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006101606512A Expired - Fee Related CN100502003C (en) | 2006-11-29 | 2006-11-29 | Semiconductor device structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5701684B2 (en) * | 2011-05-23 | 2015-04-15 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device |
| TWI467766B (en) * | 2012-08-31 | 2015-01-01 | Nuvoton Technology Corp | Metal oxide semiconductor field transistor and method of fabricating the same |
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- 2006-11-29 CN CNB2006101606512A patent/CN100502003C/en not_active Expired - Fee Related
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