CN100498912C

CN100498912C - Circuit arrangement of LCD gate pole driver

Info

Publication number: CN100498912C
Application number: CNB2005101353891A
Authority: CN
Inventors: 李英信; 邱胜任; 陈建廷
Original assignee: Elan Microelectronics Corp
Current assignee: Elan Microelectronics Corp
Priority date: 2005-12-31
Filing date: 2005-12-31
Publication date: 2009-06-10
Anticipated expiration: 2025-12-31
Also published as: CN1991954A

Abstract

A LCD gate driver circuit device is disclosed, the circuit device includes many gate drivers, and the gate driver includes: a carry circuit which is connected with first and second switch; several temporary-storage circuits connected with the first switch; several buffer circuits connected with the second switch; several buffer circuits output signal to a carry circuit, the carry circuit is as voltage condition, passes the second switch and output to proper buffer circuit to form a gate driver circuit device, the function of decreasing the quantity of carry circuit to reduce the area and maintain original gate circuit can be achieved.

Description

Circuit arrangement of LCD gate pole driver

Technical field:

The present invention relates to a kind of circuit arrangement of LCD gate pole driver, (Level Shifter, quantity LS) reaches dwindles layout area, and can keep the function of gate circuit originally to refer to a kind of minimizing carry circuit especially.

Background technology:

See also shown in Figure 9ly, be the basic circuit synoptic diagram of known LCD.As shown in the figure, integrated circuit (the I ntegratedCircuit of the driving panel of general LCD, IC) assembly, content roughly is divided into gate drive circuit 5 (gate drivercircuit) and source electrode drive circuit 6 (source driver circuit), this gate drive circuit 5 is the gate voltage (gate voltage) in order to the thin film transistor (TFT) (Thin Film Transistor) that produces switch liquid crystal display pixel (pixel), and this source electrode drive circuit 6 is the data voltage (Datavoltage) that produces the pixel color range of LCD; Wherein this gate drive circuit 5 is rearranged by many single gate pole drivers 51 (gate driver), and this single gate pole driver 51 by a buffering circuit 511 (Shift register, SR), voltage carry circuit 512 and a buffer circuit 513 (Buffer) form.

See also shown in Figure 10ly, be the schematic flow sheet of known gate pole driver.As shown in the figure, in the gate drive circuit of the present drive IC of liquid crystal panel, comprise Vcc signal end 71, Vss signal end 72, VGH signal end 73 and VGL signal end 74 at least.In single gate pole driver, signal all is to output to a carry circuit 512 by a buffering circuit 511, outputs to a buffer circuit 5 by a carry circuit 512 again

13; In the gate frequency of LCD, it is noble potential (High opens LCD) that a time point has only the output signal of a gate pole driver, and the output signal of other gate pole driver then is electronegative potential (Low closes LCD).Just in all gate pole drivers, once having only a carry circuit 512 is to do voltage transition action, and other carry circuit 512 then all is to maintain original voltage status.

See also shown in Figure 11ly, be known buffering circuit circuit diagram.As shown in the figure, the buffering circuit 511 of two polyphones, it comprises input end 81 at least, first output terminal 821, second output terminal 822, the first sequential end 831, the second sequential end 832, flip-flop (Flip Flop) (851,852) with sequential signal (Clock) 84, wherein, be to utilize two flip-flops (851, the signal of 852) upper level being come in pins, and reach next stage in proper order, and this flip-flop (851,852) the first sequential end 831 and the signal of the second sequential end 832 are promptly determined the output width of buffering circuit 511 by 84 decisions of sequential signal by the frequency of sequential signal 84; And in Fig. 9, a series of buffering circuit 511 is arranged in the gate pole driver, and high levels signal (high pulse) one-level one-level can be relayed, and each time point has only a high levels signal to occur, therefore, gate can be opened in order.Because the liquid crystal characteristic of LCD, the voltage range of gateway line 52 is about+16v～-16v, the signal voltage scope that buffering circuit 511 is exported is then about 3v～0v, so the output terminal of each group buffering circuit 511 all sees through carry circuit 512 voltage range widened.

See also shown in Figure 12ly, be known carry circuit circuit diagram.As shown in the figure, carry circuit 9 comprises the first transistor 911, transistor seconds 912, the 3rd transistor 913, the 4th transistor 914, the 5th transistor 921, the 6th transistor 922, the 7th transistor 923, the 8th transistor 924, input signal place 9 at least

41, Vss signal end 942, Vci signal end 943, output signal place 944, VGH signal end 945 and VGL signal end 946.(Vci～Vss) forwards high voltage range (VGH～VGL) to this carry circuit 9 of signal mat by low voltage range, the carry circuit 91 of this first order is made up of the first transistor 911, transistor seconds 912, the 3rd transistor 913 and the 4th transistor 914, and its signal reaches Vss signal end 942 by Vci signal end 943 and translates into by VGH signal end 945 and reach Vss signal end 942; Partial carry circuit 92 is to be made up of the 5th transistor 921, the 6th transistor 922, the 7th transistor 923 and the 8th transistor 924, and its signal reaches Vss signal end 942 by VGH signal end 945 and translates into by VGH signal end 945 and reach VGL signal end 946.And for example shown in Figure 10, the buffer circuit 513 of back level receives the signal from voltage carry circuit 512 as the usefulness of impedance matching, and signal is delivered on the gateway line 16.

See also shown in Figure 9, because conventional practice, each group gate pole driver 51 all is furnished with a buffering circuit 511, a voltage carry circuit 512 and a buffer circuit 513, if 220 groups gate pole driver 51 is arranged, just have 511,220 voltage carry circuits 512 of 220 buffering circuits and 220 buffer circuits 513.Please further consult shown in Figure 12, upward the VGH signal can be up to 13v owing to LCD again, and the VGL signal can be up to-13v, and metal-oxide half field effect transistor (the Metal-Oxide Semiconductor of the 3rd transistor 913 to the 8th transistors 924, MOS) assembly all is the assembly of high pressure manufacturing process, needs extra N type buried horizon (NBL) to do the isolation (Well) of assembly.In addition, for the voltage of Vci to Vss being changed smoothly, the MOS width of voltage carry circuit 512 has more than the 100um, causes on the layout, and voltage carry circuit 512 areas are about more than 1/3rd areas of whole gate pole driver 51.So many areas all are used to arrange carry circuit 512 on the gate drive circuit 5, and along with the resolution of LCD is high more, promptly gate quantity is many more, if according to former the design, the layout area of IC will be big more.

Summary of the invention:

Technical matters to be solved by this invention is: at the above-mentioned deficiency of prior art, a kind of circuit arrangement of LCD gate pole driver is provided, can share a carry circuit by at least two gate pole drivers, to reduce the quantity of carry circuit, reach and dwindle layout area, and keep the function of gate circuit originally.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of circuit arrangement of LCD gate pole driver, and this circuit arrangement is made up of most gate pole drivers, and described gate pole driver includes:

One carry circuit, this carry circuit are connected with one first selector switch and one second selector switch respectively; A most buffering circuit, each buffering circuit is connected with above-mentioned first selector switch; And most buffer circuits, each buffer circuit is connected with above-mentioned second selector switch, this majority buffering circuit output signal is to this carry circuit, utilize this carry circuit to do the voltage transition, see through this second selector switch again, output on the buffer circuit suitable in this majority buffer circuit, form a gate pole driver circuit arrangement.

Compared with prior art, advantage of the present invention is: share a carry circuit by at least two buffering circuits, can reduce the quantity of carry circuit, dwindle the layout area of gate pole driver, and can keep the function of gate circuit originally.

Description of drawings:

Fig. 1 is the schematic flow sheet of gate pole driver of the present invention.

Fig. 2 is another embodiment schematic flow sheet of gate pole driver of the present invention.

Fig. 3, Fig. 4 are the circuit diagrams of first and second selector switch of the present invention.

Fig. 5, Fig. 6 are the design diagrams of first and second selector switch of the present invention.

Fig. 7, Fig. 8 are another design diagrams of first and second selector switch of the present invention.

Fig. 9 is the basic circuit synoptic diagram of known LCD.

Figure 10 is the schematic flow sheet of known gate pole driver.

Figure 11 is known buffering circuit circuit diagram.

Figure 12 is known carry circuit circuit diagram.

Label declaration:

Gate pole driver 1 beginning pulse wave 11

Buffering circuit 12

First selector switch 131

Second selector switch 132

Carry circuit 14 buffer circuits 15

Gateway line 16 Vcc signal ends 171

Vss signal end 172 VGH signal ends 173

VGL signal end 174 first selection wires 175

Second selection wire, 176 first beginning pulse waves 21

The second beginning pulse wave, 22 anti-multiplexers 3

Anti-multiplexer input end 31

Anti-multiplexer first output terminal 32

Anti-multiplexer second output terminal 33

Anti-multiplexer selecting side 34 multiplexers 4

Multiplexer first input end 41

Multiplexer second input end 42

Multiplexer output terminal 43

Multiplexer selecting side 44

Gate drive circuit 5 gate pole drivers 51

Buffering circuit 511 carry circuits 512

Buffer circuit 513 gateway lines 52

Source electrode drive circuit 6 Vcc signal ends 71

Vss signal end 72 VGH signal ends 73

VGL signal end 74 input ends 81

First output terminal, 821 second output terminals 822

The first sequential end, 831 second sequential ends 832

Sequential signal 84

Flip-flop 851,852

Carry circuit 9

The carry circuit 91 of the first order

The first transistor 911 transistor secondses 912

The 3rd transistor 913 the 4th transistor 914

The 5th transistor 921

Partial carry circuit 92

The 6th transistor 922 the 7th transistor 923

The 8th transistor 924 buffer circuits 93

Input signal place 941 Vss signal ends 942

Vci signal end 943 output signal places 944

VGH signal end 945 VGL signal ends 946

Embodiment:

See also shown in Figure 1ly, be the schematic flow sheet of gate pole driver of the present invention.As shown in the figure: the flow process of a kind of circuit arrangement of LCD gate pole driver of the present invention, at least comprise beginning pulse wave 11, buffering circuit 12 (Shift Register, SR), Vcc signal end 171, Vss signal end 172, first selector switch 131, carry circuit 14 (Level Shifter, LS), VGH signal end 173, VGL signal end 174, second selector switch 132, buffer circuit 15 (Buffer) and gateway line 16.The present invention is a kind of circuit arrangement of LCD gate pole driver, formed by most gate pole drivers 1, and this gate pole driver 1 is made up of a carry circuit 14, most buffering circuits 12 and most buffer circuits 15, the quantity that can reduce carry circuit 14 reaches dwindles layout (layout) area, and can keep the function of gate circuit originally.

This carry circuit 14 is connected with one first selector switch 131 and one second selector switch 132 respectively; Each buffering circuit 12 is connected with this first selector switch 131; And each buffer circuit 15 is connected with above-mentioned second selector switch 132; By this, can make in most buffering circuit 12 output signals to a carry circuit 14, utilize this carry circuit 14 to do the voltage transition, see through second selector switch 132 again and output on the suitable buffer circuit 15, form a gate pole driver circuit arrangement.

Because this carry circuit 14 is the most space consuming assembly,, must reduce the layout area of gate pole driver 1 if can reduce the quantity of carry circuit 14 in gate pole driver 1.For example: 220 gate pole drivers 1 are set, originally can use 220 carry circuits 14, and the present invention allows the buffering circuit 12 more than 2 share a carry circuit 14, so, the number of this carry circuit 14 will be reduced to 110 groups at least, utilize first and second selection wire (175,176) to go to control first and second selector switch (131,132) again, the script function of gate pole driver 1 can be arranged equally; As for the circuit area that increases first and second selector switch (131,132), approximately have only 1/10th of script carry circuit 14, area is still helpful for reducing.

See also shown in Figure 2ly, be another embodiment schematic flow sheet of gate pole driver of the present invention.As shown in the figure: the another embodiment of the present invention flow process comprises the first beginning pulse wave 21, the second beginning pulse wave 22, buffering circuit 12, Vcc signal end 171, Vss signal end 172, first selector switch 131, first selection wire 175, second selection wire 176, carry circuit 14, second selector switch 132, VGH signal end 173, VGL signal end 174 and buffer circuit 15 at least.Sharing mode about carry circuit 14 of the present invention, not necessarily want two contiguous gate pole drivers 1 to share a carry circuit 14, also can share with gate pole driver 1 far away, there is different carry circuit 14 to share combination, wherein selection signal (S1, the S2 of first selector switch 131 and second selector switch 132 ...) can be different.If the signal of gate is (G1 → G2 → G3 → G4 in proper order ...), select signal tool rule, then share one group of carry circuit 14 with the gate pole driver far away more 1 of being separated by, its switching frequency is low more, and the near more gate pole driver of being separated by is shared carry circuit 14, and selection signal switching frequency then can be high more; If the signal right and wrong of gate in proper order (as G1 → G4 → G7 → G10 ..., G2 → G5 → G8 → G11 ...), then select signal waveform just irregular; In other words, the signal of selection with the assembled arrangement of carry circuit 14 with the difference of gate pole driver 1 load mode and difference.

Please further consult Fig. 3～shown in Figure 8, be respectively the circuit diagram of first and second selector switch of the present invention, the design diagram of first and second selector switch and another design diagram of first and second selector switch.As shown in the figure: first and second selector switch of the present invention comprises anti-multiplexer (De-multiplex at least, DMux) 3, anti-multiplexer input end 31, anti-multiplexer first output terminal 32, anti-multiplexer second output terminal 33, anti-multiplexer selecting side 34, multiplexer 4 (multiplex, Mux), multiplexer first input end 41, multiplexer second input end 42, multiplexer output terminal 4

3 and multiplexer selecting side 44; When carry circuit 14 of the present invention is shared, can use first selector switch 131 (Front switch) and second selector switch 132 (End switch), allow the input of carry circuit 14 and output choose suitable gate pole driver 1; And this first and second selector switch (131,132) can utilize have anti-multiplexer input end 31, the anti-multiplexer 3 of anti-multiplexer first output terminal 32, anti-multiplexer second output terminal 33 and anti-multiplexer selecting side 34, as shown in Figure 3; Or for having multiplexer first input end 41, multiplexer second input end 4

2, the multiplexer 4 of multiplexer output terminal 43 and multiplexer selecting side 44, as shown in Figure 4; And this anti-multiplexer 3 and multiplexer 4 can transmit lock (CMOS (Complementary Metal-Oxide Semiconductor) transmission gate) with the CMOS field-effect transistor, or design with logical circuit (logic gate), reach and use controlling signal just can make signal be sent to different output terminals, as Fig. 5, shown in Figure 7, perhaps select different input signal sources to be sent to output terminal, as Fig. 6, shown in Figure 8.

In sum, circuit arrangement of LCD gate pole driver of the present invention can effectively improve the various shortcoming of prior art, can share a carry circuit by at least two buffering circuits, to reduce the quantity of carry circuit, reach and dwindle layout area, and can keep the function of gate circuit originally, and then the present invention is produced more progressive, more practical, more to meet user's the institute must, really meet the important document of application for a patent for invention, proposed patented claim in accordance with the law.

Only the above only is preferred embodiment of the present invention, when not limiting scope of the invention process with this; So all simple equivalent of being done according to the present patent application claim and description of the invention content change and modify, all should still belong in the scope that patent of the present invention contains.

Claims

1, a kind of circuit arrangement of LCD gate pole driver, this circuit arrangement is made up of most gate pole drivers, and it is characterized in that: described gate pole driver includes:

One carry circuit, this carry circuit are connected with one first selector switch and one second selector switch respectively;

A most buffering circuit, each buffering circuit is connected with above-mentioned first selector switch; And most buffer circuits, each buffer circuit is connected with above-mentioned second selector switch,

This majority buffering circuit output signal utilizes this carry circuit to do the voltage transition to this carry circuit, sees through this second selector switch again, outputs on the buffer circuit suitable in this majority buffer circuit, forms a gate pole driver circuit arrangement.

2, circuit arrangement of LCD gate pole driver according to claim 1 is characterized in that: described second selector switch is anti-multiplexer.

3, circuit arrangement of LCD gate pole driver according to claim 1 is characterized in that: described first selector switch is a multiplexer.

4, circuit arrangement of LCD gate pole driver according to claim 2 is characterized in that: described anti-multiplexer is made of CMOS field-effect transistor transmission lock.

5, circuit arrangement of LCD gate pole driver according to claim 2 is characterized in that: described anti-multiplexer is made of logical circuit.

6, circuit arrangement of LCD gate pole driver according to claim 3 is characterized in that: described multiplexer is made of CMOS field-effect transistor transmission lock.

7, circuit arrangement of LCD gate pole driver according to claim 3 is characterized in that: described multiplexer is made of logical circuit.

8, circuit arrangement of LCD gate pole driver according to claim 1 is characterized in that: described carry circuit connects two these buffering circuits.

9, circuit arrangement of LCD gate pole driver according to claim 1 is characterized in that: described carry circuit connects three these buffering circuits.