CN100498546C - Method for seeking target area for integrated circuit layout design - Google Patents

Abstract

The invention provides a method for finding the target area in the layout design of the integrated circuit, which is mainly used for finding the memory area which is easy to violate the design rules in the layout design of the integrated circuit. This method is designed based on the difference in key dimensions between the memory area and the logic area. Each side of the pattern feature in the layout is enlarged or reduced with a specific selected value, and the memory area and the logic area are distinguished according to the difference before and after the change of the pattern feature. This method is efficient and accurate.

Description

A Method of Finding the Target Region in IC Layout Design

technical field

The invention relates to a photolithography process in the semiconductor manufacturing industry, in particular to a method for finding a target area in an integrated circuit layout design by using a rule-based optical approximation correction tool.

Background technique

Integrated circuit manufacturing processes are divided into logic processes and memory processes, which are essentially different, and even contradictory in some places. This is reflected in some specific aspects, for example, the interconnection requirements of the two are different. The memory regions exhibit a very regular pattern, often appearing in blocks, requiring relatively few interconnects. The logic module area is often scattered in various parts of the chip, which has high requirements for interconnection. Secondly, the level of metal technology of the two is also different. The logic process generally has a circuit structure of 4 to 6 layers, of which there are only 1 to 2 layers of polysilicon, and the rest are metal layers. The memory process often requires the formation of more than 4 layers of polysilicon.

Due to the difference in design and process, the memory area and the logic area are obviously different in the same integrated circuit layout design. The pattern features of the former are compact (small critical size) and arranged in an orderly manner, while the pattern features of the latter are relatively large (key large size) with irregular patterns. With the continuous shrinkage of integrated circuit design rules, the memory area in the current layout design of integrated circuits is prone to violations of the design rules. As mentioned earlier, logic areas do not violate design rules due to the large spacing between pattern features. Only the memory area, for example, a SRAM (Static Random Access Memory) area, is relatively easy to violate the design rules due to its dense pattern features.

In practice, due to cost and turnaround time considerations, people usually only want to perform Optical Proximity Correction (OPC, Optical ProximityCorrection) on memory regions that violate design rules. The method adopted at present is mainly to find out the area that violates the design rule through the Design Rule Check (DRC, Design Rule Check) tool, and then judge whether it is an SRAM cell area. If the judging result is affirmative, draw a layer of color-coded overlay on this area in the layout displayed by the design rule checking tool to mark this area. Subsequent optical approximation corrections will only be performed on the marked areas. The above-mentioned steps of finding and marking the target area take a long time, and it usually takes about 2 days to check a complete IC layout design.

Contents of the invention

Aiming at the problem that it is difficult to find out the memory area in an integrated circuit layout and perform optical approximation correction on it, thus affecting the work efficiency, the present invention is proposed.

The object of the present invention is to provide a method for finding an integrated circuit layout design target area (memory area). This method does not use design rule checking (DRC, Design Rule Check) tools to find memory regions that violate design rules, but uses a rule-based optical approximation correction tool (rule OPC) to find the memory regions. more efficient than current methods.

The method of the present invention is essentially used to distinguish regions of different critical dimensions (CD, Critical Dimension) in the layout design of an integrated circuit, for example, the critical dimension of one region is a, and the critical dimension of another region is b, where a>b. According to the method of the present invention has following operating steps:

1) Expand the pattern features in the layout of the integrated circuit by a distance n on each side, (b/2)<n<(a/2);

2) reducing the distance n inwardly on each side of the pattern feature in the enlarged integrated circuit layout;

3) Exclusive OR (XOR) logic operation is performed on the integrated circuit layout obtained after the above-mentioned steps and the original integrated circuit layout to obtain an integrated circuit layout that only leaves areas with changed pattern features;

4) Mark the area where the pattern features in the integrated circuit layout obtained in the above steps have changed with color, cover the integrated circuit layout on the original layout, and the area covered by the color marking is the original layout target area.

The above-mentioned "exclusive OR" (XOR) logic operation rule is: (A-B)+(B-A), that is, logical NOT operation is performed on two kinds of data respectively, and logical OR operation is performed on the result obtained. For example, in the present invention, A may be layout A before the enlargement and reduction operations, and B may be layout B after the enlargement and reduction operations.

In the present invention, the critical dimension (CD, Critical Dimension) can be understood as the pitch of the pattern features in the layout. As mentioned above, for the logic circuit area, the pattern feature pitch (critical dimension) is relatively large, for example, the critical dimension is 240nm. In contrast, the pattern feature pitch (critical dimension) of the memory region is relatively small, for example, the critical dimension (CD, Critical Dimension) is 230nm.

The method of the present invention is designed based on the difference in critical dimensions of the above two regions.

For the pattern of the logic circuit region whose critical dimension is a=240nm as shown in Figure 1a, if each side of it is expanded outwards by a distance n smaller than (240/2)nm but greater than (230/2)nm, after the expansion The pattern does not overlap with adjacent patterns, and the enlarged pattern features are shown in Figure 1b. Each side of the pattern feature is then shrunk inward by the same distance, that is, the same pattern as before the enlargement and reduction operations is obtained, as shown in FIG. 1c.

For the pattern of the memory region as shown in Figure 2a, its critical dimension is b=230nm, if each side of the pattern feature is expanded by the above-mentioned same distance n, the expanded pattern will overlap with the adjacent pattern, as shown in Fig. As shown in 2b, the overlapped patterns become one pattern. When each side of the pattern is subsequently shrunk inward by the same distance, only the side of the pattern feature that does not overlap with other pattern features shrinks inward, and finally the entire memory area remains unchanged, but the pattern of the memory area becomes a whole block and cannot be separated , as shown in Figure 2c.

The above operations of expanding or reducing the pattern can be completed with the ready-made rule-based optical approximation correction tool (rule OPC), which is usually used to correct the shape of some pattern features according to the rules, for example, when a circuit pattern When there are specified characteristics, rule OPC uses predetermined conditions corresponding to this characteristic to modify the shape of the circuit pattern. In other words, the tool itself has the ability to modify the shape of the pattern entered into it.

It is not difficult to understand that when all the characteristic patterns in an integrated circuit layout design undergo the above-mentioned enlargement and reduction operations in the rule-based optical approximation correction tool, the logic circuit area with a large critical size remains unchanged in shape, and the pattern The change in shape (there is overlap) is the memory region with a smaller critical size, and the two kinds of regions are clearly distinguished.

At this time, the operation function of the optical approximation correction tool can be used to perform "exclusive OR" logic operation on the layout obtained after the enlargement and reduction operations and the original layout, and the result is the memory area with the changed shape of the pattern.

Continue to use the function of the optical approximation correction tool to expand each side of the pattern in the memory area obtained after the "exclusive OR" logical operation without limit in this area, so that the memory area becomes a whole pattern without gaps, each A "block" is an area of memory.

Finally, the obtained layout with only the block memory area left is overlaid on the original layout, and the block memory area is marked with color. After covering the original layout, the target memory area is covered by the color block As indicated, this operation can also be done by the function of the optical approximation correction tool itself. Subsequent optical approximation correction steps can only be performed on the area marked by the color block.

The advantage of the present invention is that all the above-mentioned operations can be completed by the function of the optical approximation correction tool itself, which is very simple and quick. It takes about 2 days to check a complete integrated circuit layout design according to the current method, but according to the method of the present invention, the time can be greatly shortened, and the above work can be completed in about half an hour. In addition, the method of the present invention is designed based on the fact that the key size of the target area is different from other areas, and the accuracy rate is very high during implementation, and a memory area with a smaller key size can be found by repeating at most several times.

In order to understand the purpose, features and advantages of the present invention more easily, the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

Description of drawings

The drawings included in this application are an integral part of the description, and together with the description and the claims, the drawings are used to illustrate the essence of the present invention, so as to better understand the present invention.

Figure 1a is a schematic diagram of the pattern features of the logic circuit region in the layout design of the integrated circuit;

Fig. 1b shows that according to the method of the present invention, each side of the pattern feature shown in Fig. 1a is enlarged outward;

As shown in Figure 1c, according to the method of the present invention, each side of the pattern feature shown in Figure 1b shrinks inwardly;

2a is a schematic diagram of pattern features of memory regions in an integrated circuit layout design;

As shown in Figure 2b, according to the method of the present invention, each side of the pattern feature shown in Figure 2b is enlarged outward;

As shown in Figure 2c, according to the method of the present invention, each side of the pattern feature shown in Figure 2b shrinks inwardly; and

3a to 3f are the integrated circuit layouts displayed in the optical approximation correction tool corresponding to each step when the method of the present invention is applied. The number 1 in the figure indicates the logic circuit area, and the number 2 indicates the memory area.

Detailed ways

In order to better understand the process of the present invention, the following will be further described in conjunction with specific examples of the present invention, but they do not limit the present invention.

Example 1

Finding Memory Regions in IC Layout Designs

The optical approximation correction tool used in this embodiment is the rule generator Rulegen provided by SYNOPSYS and the rule implementation tool Proteus. The former is used to generate rules, which limit the value of the expansion or reduction of the pattern features of the layout. ; The latter is used to implement predetermined rules to expand or reduce the pattern features of the layout.

When it is necessary to perform optical approximation correction on the pattern of an integrated circuit layout design, it is usually only desired to correct the SRAM memory area which is easy to violate the design rules. At this time, the memory area needs to be found in the integrated circuit layout .

In the integrated circuit layout shown in Figure 3a, the critical dimension of the logic circuit area 1 is 240nm, and the critical dimension of the memory area 2 is 230nm. First, this integrated circuit layout is input into rule-based optical approximation in the industry-common gds file format In the correction tool Proteus, and set the pattern expansion and reduction rules between 115nm and 120nm in the rule generator Rulegen, such as 118nm, first expand the above distance outwards on each side of the pattern feature in the integrated circuit layout, and obtain the layout As shown in Figure 3b, each side of the pattern feature in the integrated circuit layout is then shrunk inward at the same distance, since the critical dimension of the memory region is 230nm, when each side of the pattern expands 118nm outward, the pattern of the memory region will Superimposed on each other, the expanded pattern is then shrunk inward by 118nm on each side, and the resulting layout is shown in Figure 3c.

The layout shown in Figure 3c and the original integrated circuit layout (i.e. the integrated circuit layout shown in Figure 1) perform "exclusive OR" logic operations to obtain a layout that only leaves a region 2 with a change in pattern characteristics, such as As shown in Figure 3d (here, the understanding of the layout should be the integrated circuit layout with a complete range, and its area is consistent with the original layout, but after the "exclusive OR" operation, the area where the pattern features do not change in the layout range becomes blank ). The pattern features in the area 2 where the pattern features are changed are enlarged infinitely in this area to make it a whole pattern in this area, and the whole pattern is filled with color, as shown in Figure 3e.

The obtained integrated circuit layout with the entire colored pattern is overlaid on the original layout, and the memory area of the original layout is marked by the covered color blocks, as shown in FIG. 3f.

The above-mentioned process of pattern features being enlarged or reduced is actually equivalent to the operation of optical approximation correction. After the GDS file recording the layout of the integrated circuit is input into the optical approximation correction tool, this operation and subsequent calculations on the layout , coloring, overlay and other steps can be automatically completed in the optical approximation correction tool with its functions, and the time required is very small. Usually, it takes less than half an hour to complete the process of finding and marking the target area for a complete layout.

Claims (2)

1, a kind of method of seeking target area in the IC layout design, described target area has critical size b, the nontarget area has critical size a, a〉b, this method comprises the following steps:

1) the every limit of the pattern characteristics in the integrated circuit Butut is outwards enlarged apart from n, (b/2)＜n＜(a/2);

2) will be through enlarging the inside decreased distance n in the every limit of pattern characteristics in the integrated circuit Butut that obtains;

3) with step 2) the integrated circuit Butut that obtains after handling carries out the XOR computing with original integrated circuit Butut, only stayed the pattern characteristics regional integrated circuit Butut that changes;

4) the vicissitudinous zone of pattern characteristics described in the integrated circuit Butut that obtains with the color mark step 3) covers the integrated circuit Butut behind this mark to original Butut;

Be target area in the original Butut by what described color mark zone covered.

2, the method for claim 1 is characterized in that, step 1)～2) circulation carries out once or once, continues subsequent step again.

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