CN100498546C - Method for seeking target area for integrated circuit layout design - Google Patents
Method for seeking target area for integrated circuit layout design Download PDFInfo
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- CN100498546C CN100498546C CNB2006100264236A CN200610026423A CN100498546C CN 100498546 C CN100498546 C CN 100498546C CN B2006100264236 A CNB2006100264236 A CN B2006100264236A CN 200610026423 A CN200610026423 A CN 200610026423A CN 100498546 C CN100498546 C CN 100498546C
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Abstract
The invention provides a method for searching for target regions in IC layout design, mainly used to search for memory regions easy to violate design rules in IC layout design. And the method is designed, based on different key sizes of memory and logic regions, zooms in and out all sides of pattern property in a layout at specific values, and differentiates the memory regions from the logic regions according to the difference before and after pattern property change. And the method has features of high efficiency and accurate.
Description
Technical field
The present invention relates to the lithographic process in the semi-conductor industry, relate in particular to a kind of method of utilizing rule-based optical approximate truing tool to seek target area in the IC layout design.
Background technology
Integrated circuit fabrication process is divided into logic process and memory process, and they are different in essence, some place or even contradiction.This for example is embodied in some concrete aspects, the interconnection needs difference of the two.The pattern that memory area presents is fairly regular, often becomes piece to occur, and required interconnection is fewer.And the logic module zone usually hash in each place of chip, to the interconnection requirement very high.Secondly, the smithcraft level of the two is also different.Logic process generally has 4～6 layers of circuit structure, wherein has only 1～2 layer of polysilicon, and all the other are metal level.And memory process usually needs to form the polysilicon more than 4 layers.
Because design and technologic difference, memory area is obviously different with logic region in same IC layout design, and the former pattern characteristics is (critical size is little) closely, arranges in order, and the latter's pattern characteristics spacing big (critical size is big), pattern is irregular.Along with the continuous contraction of integrated circuit (IC) design rule, the memory area in the present IC layout design occurs and the contrary situation of design rule easily.As previously mentioned, logic region can't have the situation of violating design rule to occur because big spacing is arranged between pattern characteristics.Have only memory area, for example, because of the pattern characteristics of itself is intensive, disagree with design rule than being easier in a SRAM (static RAM) zone.
In practical operation, for the consideration on cost and turnaround time, people only wish the memory area of violating design rule is carried out optical approximate correction (OPC, Optical ProximityCorrection) usually.The method that adopts mainly is to find out and the contrary zone of design rule by DRC (DRC, Design RuleCheck) instrument at present, judges then whether it is the sram cell zone.If judged result is certainly, then draw the overlayer of one deck color mark on this zone in the domain that the DRC instrument shows, mark this zone.Follow-up optical approximate correction will only be carried out the zone that marks.The step spended time in above-mentioned searching and target-marking zone is very long, checks that usually a complete IC layout design needs about 2 days.
Summary of the invention
At in an integrated circuit Butut, will finding out at present memory area, thereby influence the problem of work efficiency, proposition the present invention to its process of carrying out optical approximate correction difficulty relatively.
The objective of the invention is to, the method for a kind of searching IC layout design target area (memory area) is provided.This method is not used DRC (DRC, Design Rule Check) instrument is sought the memory area of violating design rule, but adopting rule-based optical approximate truing tool (rule OPC) to seek described memory area, the present method of the efficiency ratio of this kind method is higher.
Method of the present invention comes down to be used for distinguishing the zone of IC layout design varying critical dimensions (CD, Critical Dimension), and for example the critical size in a zone is a, and another regional critical size is b, a〉b.Have following operation steps according to method of the present invention:
1) the every limit of the pattern characteristics in the integrated circuit Butut is outwards enlarged apart from n, (b/2)＜n＜(a/2);
2) will be through enlarging the inside decreased distance n in the every limit of pattern characteristics in the integrated circuit Butut that obtains;
3) the integrated circuit Butut that obtains after above-mentioned steps is handled carries out distance (XOR) logical operation with original integrated circuit Butut, is only stayed the pattern characteristics regional integrated circuit Butut that changes;
4) the vicissitudinous zone of pattern characteristics described in the integrated circuit Butut that obtains with the color mark above-mentioned steps covers this integrated circuit Butut to original Butut, is target area in the original Butut by what described color mark zone covered.
Above-mentioned distance (XOR) logical operation rule is: (A-B)+(B-A), promptly two kinds of data are carried out the logic NOT computing respectively, and the result who obtains carries out the logical OR computing again.For example in the present invention, A enlarges and reduction operation Butut A before, and B enlarges and reduction operation Butut B afterwards.
In the present invention, critical size (CD, Critical Dimension) can be interpreted as the spacing of pattern characteristics in the Butut.As previously mentioned, for the logical circuit zone, its pattern characteristics spacing (critical size) is bigger, and for example critical size is 240nm.Relatively, the pattern characteristics spacing (critical size) of memory area is just smaller, and for example critical size (CD, Critical Dimension) is 230nm.
Method of the present invention, the critical size that just is being based on above-mentioned two kinds of zones is different and design.
For as shown in Figure 1a critical size is the pattern in the logical circuit zone of a=240nm, if its every limit is outwards enlarged less than (240/2) nm, but greater than (230/2) nm apart from n, the pattern after the expansion can't with adjacent pattern overlapping, the pattern characteristics after the expansion is shown in Fig. 1 b.Every limit with pattern characteristics inwardly dwindles same distance subsequently, promptly enlarged and reduction operation before identical pattern, shown in Fig. 1 c.
Pattern for the memory area shown in Fig. 2 a, its critical size is b=230nm, if every limit of pattern characteristics is outwards enlarged above-mentioned same apart from n, the pattern after the expansion will with adjacent pattern overlapping, shown in Fig. 2 b, the pattern after overlapping becomes a pattern.Subsequently every limit of pattern is inwardly dwindled same apart from the time, have only the limit of the pattern characteristics that does not overlap inwardly to shrink with other pattern characteristics, last whole memory area scope is constant, but the pattern of memory area becomes monoblock, can not separate, shown in Fig. 2 c.
Above-mentioned pattern is enlarged or the operation dwindled can be finished with ready-made rule-based optical approximate truing tool (rule OPC), this kind instrument conventional application is according to rule the shape of some pattern characteristics to be revised, for example when a circuit pattern had the feature of regulation, rule OPC promptly adopted the predetermined corresponding condition of feature therewith that circuit pattern is carried out Shape Modification.In other words, this instrument itself has the ability of input pattern wherein being carried out Shape Modification.
Be understood that, when all characteristic patterns in the IC layout design all pass through above-mentioned expansion and reduction operation in rule-based optical approximate truing tool after, what shape did not change is the bigger logical circuit zone of critical size, what pattern form changed (overlapping phenomenon is arranged) is the less memory area of critical size, and two kinds of zones are distinguished significantly.
Can utilize the calculation function of optical approximate truing tool this moment, and the Butut that enlarges, obtain after the reduction operation and original Butut are carried out the XOR computing, and the result is the vicissitudinous memory area of described pattern form.
Continue to utilize the function of optical approximate truing tool, every limit of pattern in the memory area that obtains after the XOR computing is unrestrictedly enlarged in the one's respective area, make described memory area become monoblock pattern very close to each other, each " piece " is a memory area.
The Butut that only stays block memory area that will obtain at last covers to original Butut, described block memory area is with color mark, cover to original Butut, the color lump that the target memory zone promptly is capped thereon marks, and this operation can be finished by the function of optical approximate truing tool itself equally.Carry out in the zone that follow-up optical approximate correction step can only indicate at color lump.
The invention has the advantages that above-mentioned all operations all can be finished by the function of optical approximate truing tool itself, and is very simple and efficient.Check that according to present method a complete IC layout design needs about 2 days, and shortened dramatically the time, can finish above-mentioned work about half an hour approximately according to method of the present invention.In addition, it is different with other regional critical sizes and design that method of the present invention is based on the target area, and accuracy rate is very high when carrying out, and repeats can seek out several times the less memory area of critical size at most.
For be more readily understood purpose of the present invention, feature with and advantage, below conjunction with figs. and embodiment are described in detail the present invention.
Description of drawings
The accompanying drawing that comprises among the application is a component part of instructions, and accompanying drawing and instructions and claims one are used from explanation flesh and blood of the present invention, are used for understanding better the present invention.
Fig. 1 a is the pattern characteristics synoptic diagram in logical circuit zone in the IC layout design;
Fig. 1 b is depicted as the synoptic diagram that every limit of pattern characteristics shown in Fig. 1 a is outwards amplified according to the inventive method;
Be depicted as the synoptic diagram that every limit of pattern characteristics shown in Fig. 1 b is inwardly shunk according to the inventive method as Fig. 1 c;
Fig. 2 a is the pattern characteristics synoptic diagram of memory area in the IC layout design;
Be depicted as the synoptic diagram that every limit of pattern characteristics shown in Fig. 2 b is outwards amplified according to the inventive method as Fig. 2 b;
Be depicted as the synoptic diagram that every limit of pattern characteristics shown in Fig. 2 b is inwardly shunk according to the inventive method as Fig. 2 c; With
Fig. 3 a～Fig. 3 f when using method of the present invention, the integrated circuit Butut that in the optical approximate truing tool, shows of corresponding each step, the numeral 1 presentation logic circuit region among the figure, numeral 2 expression memory areas.
Embodiment
In order to understand technology of the present invention better, be described further below in conjunction with specific embodiments of the invention, but it does not limit the present invention.
In IC layout design, seek memory area
The Rule Builder Rulegen and the regular execution instrument Proteus that provide for SYNOPSYS company of the optical approximate truing tool of Cai Yonging in the present embodiment, the former is used for create-rule, and this rule limits expansion that the pattern characteristics to Butut will carry out or the numerical value that dwindles; The latter then is used to implement predetermined rule, the operation that the pattern characteristics of Butut is enlarged or dwindles.
In the time of need carrying out the optical approximate correction to the pattern of an IC layout design, usually only wish for example SRAM memory area of wherein violating design rule is easily revised, need find out described memory area in the integrated circuit Butut this moment.
In the integrated circuit Butut shown in Fig. 3 a, the critical size in logical circuit zone 1 is 240nm, the critical size of memory area 2 is 230nm, at first this integrated circuit Butut is imported in the rule-based optical approximate truing tool Proteus with the general gds file layout of industry, and rule is dwindled in the pattern expansion of setting in Rule Builder Rulegen between 115nm～120nm, 118nm for example, each limit to pattern characteristics in the integrated circuit Butut outwards enlarges above-mentioned distance earlier, the Butut that obtains is shown in Fig. 3 b, with identical distance each limit of pattern characteristics is inwardly shunk then, because the critical size of memory area is 230nm, when every limit of pattern outwards enlarges 118nm, the pattern of memory area will be superimposed mutually, 118nm is inwardly shunk on the every again limit of the pattern that obtains after the expansion, and the Butut that obtains is shown in Fig. 3 c.
Butut shown in Fig. 3 c and original integrated circuit Butut (being integrated circuit Butut shown in Figure 1) carry out the XOR computing, only stayed vicissitudinous regional 2 the Butut of pattern characteristics, (understanding to Butut should be the complete integrated circuit Butut of scope herein shown in Fig. 3 d, its zone is consistent with original Butut, just through nonequivalence operation, the zone that pattern characteristics does not have to change in the Butut scope becomes blank).Pattern characteristics in the pattern characteristics vicissitudinous regional 2 is infinitely amplified in the one's respective area, make it the monoblock pattern in zone for this reason, fill described monoblock pattern with color, shown in Fig. 3 e.
The integrated circuit Butut with the coloured pattern of monoblock that obtains is covered on the original Butut, and the memory area of original Butut is promptly marked by the color lump that is covered, shown in Fig. 3 f.
In fact above-mentioned pattern characteristics process extended or that dwindle is equivalent to the operation of optical approximate correction, after the GDS file of record integrated circuit Butut imported described optical approximate truing tool, this operation and thereafter to the computing of Butut, color in, steps such as covering all can utilize its function to finish automatically in the optical approximate truing tool, required time is few, and a common complete domain only need promptly can be finished the searching labeling process of target area less than the halfhour time.
Claims (2)
1, a kind of method of seeking target area in the IC layout design, described target area has critical size b, the nontarget area has critical size a, a〉b, this method comprises the following steps:
1) the every limit of the pattern characteristics in the integrated circuit Butut is outwards enlarged apart from n, (b/2)＜n＜(a/2);
2) will be through enlarging the inside decreased distance n in the every limit of pattern characteristics in the integrated circuit Butut that obtains;
3) with step 2) the integrated circuit Butut that obtains after handling carries out the XOR computing with original integrated circuit Butut, only stayed the pattern characteristics regional integrated circuit Butut that changes;
4) the vicissitudinous zone of pattern characteristics described in the integrated circuit Butut that obtains with the color mark step 3) covers the integrated circuit Butut behind this mark to original Butut;
Be target area in the original Butut by what described color mark zone covered.
2, the method for claim 1 is characterized in that, step 1)～2) circulation carries out once or once, continues subsequent step again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100264236A CN100498546C (en) | 2006-05-10 | 2006-05-10 | Method for seeking target area for integrated circuit layout design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100264236A CN100498546C (en) | 2006-05-10 | 2006-05-10 | Method for seeking target area for integrated circuit layout design |
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| Publication Number | Publication Date |
|---|---|
| CN101071272A CN101071272A (en) | 2007-11-14 |
| CN100498546C true CN100498546C (en) | 2009-06-10 |
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| CNB2006100264236A Expired - Fee Related CN100498546C (en) | 2006-05-10 | 2006-05-10 | Method for seeking target area for integrated circuit layout design |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9213798B2 (en) * | 2011-05-19 | 2015-12-15 | Sage Design Automation Ltd | Method, system and computer program product of checking an integrated circuit layout for instances of a reference pattern |
| US10685161B2 (en) * | 2018-08-20 | 2020-06-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Region based shrinking methodology for integrated circuit layout migration |
| CN110321640A (en) * | 2019-07-05 | 2019-10-11 | 四川长虹电器股份有限公司 | A kind of domain DRC processing method of integrated circuit conversion process |
| CN111723847A (en) * | 2020-05-21 | 2020-09-29 | 深圳市和美长丰科技有限公司 | Method, system, terminal device and storage medium for calculating similarity between graphs |
| CN116912272B (en) * | 2023-09-14 | 2023-11-21 | 飞腾信息技术有限公司 | Method, device, electronic equipment and storage medium for creating candidate clipping region |
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