CN100493192C - A motion compensation interpolation method for H.264 decoder - Google Patents

A motion compensation interpolation method for H.264 decoder Download PDF

Info

Publication number
CN100493192C
CN100493192C CN 200610144288 CN200610144288A CN100493192C CN 100493192 C CN100493192 C CN 100493192C CN 200610144288 CN200610144288 CN 200610144288 CN 200610144288 A CN200610144288 A CN 200610144288A CN 100493192 C CN100493192 C CN 100493192C
Authority
CN
China
Prior art keywords
pixel
pix
pixels
ask
point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN 200610144288
Other languages
Chinese (zh)
Other versions
CN1964493A (en
Inventor
杨华中
俞尧
罗嵘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BEIJING HUAXIA DENTSU TECHNOLOGY CO LTD
Original Assignee
Tsinghua University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsinghua University filed Critical Tsinghua University
Priority to CN 200610144288 priority Critical patent/CN100493192C/en
Publication of CN1964493A publication Critical patent/CN1964493A/en
Application granted granted Critical
Publication of CN100493192C publication Critical patent/CN100493192C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Image Processing (AREA)
  • Color Television Systems (AREA)

Abstract

The related motion compensation interpolation technology for video decoding circuit comprises: applying semi-pixel interpolation filters of same group to form the values of the complete four pixel points and five semi-pixel points on bright or color part, then, with both 4/9 and 2/4 modules, using the least 2-bit or 3-bit of target pixel point motion vector to decide the pixel point position and find out two nearby points, calculating arithmetic mean value as target value; for color pixel part, feeding back pixel values of first selected four points to the vertical semi-pixel filter to calculate five pixel points in small square to form three-horizontal three-vertical form with four vertexes. This invention can reduce chip area and cost efficiently.

Description

A kind of motion compensation interpolation method of H.264 decoder
Technical field
The ASIC that the present invention relates to the video decode circuit realizes.
Background technology
In H.264 the ASIC of baseline decoder realized, the motion compensated interpolation device was one of key modules.Because H.264 the interpolation formula of standard code luminance pixel point and chroma pixel point is different, common way is that these two parts are separated, and does two interpolation devices and finishes interpolation to brightness and colourity respectively.The design of Shi Xianing often has bigger hardware complexity like this, is difficult to the economize on hardware expense.And, have at least one to be in idle state all the time in two decoders because luminance pixel point and chroma pixel point are serial transmissions.
Summary of the invention
The objective of the invention is to propose a kind of motion compensated interpolation device that adopts the H.264 decoder of the interpolation calculation that same interpolation device removes to realize luminance pixel point and chroma pixel point.
H.264 standard code, movement compensation process need be finished sub-pixel interpolation.For the brightness part, interpolation is accurate to 1/4 pixel.The method of obtaining half-pix point is as described below: utilize institute to ask about half-pix point (or up and down) nearest respectively 3 adjacent whole pixels to make weighted average, weight coefficient is 1 ,-5,20,20 ,-5,1.With Fig. 2 a is example, if current calculative half-pix point is E, the point that is positioned on three whole location of pixels on the left of the E is A1, A0, A; The point that is positioned on three whole location of pixels on E right side is B, B0, B1.Then, the E computing formula is:
E=(the formula (1) of A1-5 * A0+20 * A+20 * B-5 * B0+B1+16)/32
When particular hardware realizes, can adopt following method:
E1=A1-5 * A0+20 * A+20 * B-5 * B0+B1+16, E is obtained by the E1 5bit that moves to right.
The method of wherein utilizing interpolation to obtain 1/4 pixel is to ask arithmetic average to get final product to the most close two the half-pix points (or a whole pixel and a half-pix point) of 1/4 pixel of asking.With accompanying drawing 2a is example, supposes that X is 1/4 pixel to be asked.Then X adopts following formula to obtain:
X=(E+F+1)/2
Formula (2)
Reality can adopt following method when realizing with hardware:
X1=E+F+1, X is obtained by the X1 1bit that moves to right.
For chrominance section, interpolation is accurate to 1/8 pixel.If X ' is for waiting to ask 1/8 pixel, A ', B ', C ', D ' are the adjacent on every side whole pixel of X ', and their position relation is established xFracC and be abscissa poor of X ' and A ' as shown in Figure 3, and yFracC is ordinate poor of X ' and A '.Then the computing formula of X ' is:
X’=((8-xFracC)*(8-yFracC)*A’+xFracC*(8-yFracC)*B’+(8-xFracC)*yFracC*C’+xFracC*yFracC*D’+32)/64
Formula (3)
When particular hardware realizes, can adopt following method:
* yFracC*C '+xFracC*yFracC*D '+32 of * (8-yFracC) * A '+xFracC* (8-yFracC) the * B ' of X1 '=(8-xFracC)+(8-xFracC) can obtain the X ' that asks by X1 ' 6 bits that move to right.
The invention has the advantages that: described method realizes on ASIC, wherein, realizes according to the following steps respectively for the luminance block of 4 x, 4 sizes and the chrominance block of 4 x, 4 sizes:
II. for described luminance block, calculate when waiting to ask current 1/4 pixel X, contain following steps successively:
Step (1.0): initialization, set, whole pixel A, B, C, D is 4 points among 2 of one 2 x in current 4 x, 4 luminance block, and X is in A, B, C, in the square area that D constitutes, A, B, C, D is provided with in the direction of the clock, wherein, A is the top left corner apex in the 2x2 piece, with A is initial point, abscissa is along A=〉setting of B direction, ordinate is along A=〉setting of D direction, A, A0, A1 waits to ask near the upside of the 1/4 pixel X square adjacent whole pixel that makes progress against the current, B, B0, B1 be successively near the X upside downstream square to adjacent whole pixel, D, D0, D1 be successively the X downside against the current square to adjacent whole pixel, C, C0, C1 is the X downside square adjacent whole pixel that makes progress downstream, in like manner, A, J0, J1 and D, L0, L1 is respectively that the left side is contrary near this pixel X, along the adjacent whole pixel of vertical direction, B, K0, K1 and C, M0, M1 is respectively that the right side is contrary near this pixel X, along the adjacent whole pixel on the vertical direction;
E, H, I, F are the mid point of line segment AB, BC, CD, DA successively, all are the half-pix points, and G is the mid point of line segment FH, are the half-pix point, and F1, F0, F and H1, H0, H are respectively the same horizontal left of half-pix point G and right-hand 3 nearest half-pix points;
Step (1.1), deposit the value of whole pixel A1, A0, A, B, B0, B1 at horizontal half-pix interpolation filter 1, deposit the value of half-pix point F1, F0, F, H, H0, H1 at horizontal half-pix interpolation filter 2, deposit the value of putting in order pixel D1, D0, D, C, C0, C1 at horizontal half-pix interpolation filter 3;
Step (1.2), in first clock cycle, carry out following steps:
Vertically the half-pix interpolation filter reads in 6 adjacent whole pixels that whole pixel A, D one are listed as from reference frame, is followed successively by J1, J0, A, D, L0, L1 from top to bottom, and calculates the value of half-pix point F as follows:
F=(J1-5 * J0+20 * A+20 * D-5 * L0+L1+16)/32, this vertical half-pix interpolation filter is sent into shift register group 2 to the value of half-pix point F respectively, whole pixel A is sent into shift register group 1, whole pixel D is sent into shift register group 3;
Step (1.3), carry out following step successively second clock cycle:
This vertical half-pix interpolation filter reference frame reads in 6 adjacent whole pixels of whole pixel B, C place one row, is followed successively by K1, K0, B, C, M0, M1 from top to bottom, and obtains the value of half-pix point H as follows:
(K1-5 * K0+20 * B+20 * D-5 * M0+M1+16)/32, this vertical half-pix interpolation filter is sent into shift register group 2 to half-pix point H respectively to H=, and whole pixel B is sent into shift register group 1, and whole pixel C is sent into shift register group 3;
Step (1.4), shift register group 1 is sent into horizontal half pixel digital difference detector 1 to whole pixel A1, A0, A, B, B0, B1, and this interpolation filter calculates the value of half-pix point E according to following formula:
E=(A1-5×A0+20×A+20×B-5×B0+B1+16)/32;
Shift register group 3 is sent into horizontal half pixel digital difference detector 3 to whole pixel D1, D0, D, C, C0, C1, and this interpolation filter calculates the value of half-pix point I according to following formula:
I=(D1-5×D0+20×D+20×C-5×C0+C1+16)/32;
Shift register group 2 is sent into horizontal half pixel digital difference detector 2 to half-pix point F1, F0, F, H, H0, H1, and this interpolation filter calculates the value of half-pix point G according to following formula:
G=(F1-5×F0+20×F+20×H-5×H0+H1+16)/32;
Step (1.5), shift register group 1 be the value of whole pixel A, B, and shift register group 2 is the value of whole pixel F, H,
Shift register group 3 is the value of whole pixel C, D, laterally half-pix interpolation filter 1 is the value of half-pix point E, laterally half-pix interpolation filter 2 is the value of half-pix point G, and laterally half-pix interpolation filter 3 is the value of half-pix point I, walks abreast to send into 9 and select 4 modules;
Step (1.6), this 9 selects 4 modules to determine the residing position of 1/4 pixel of asking by minimum 2 bits of the motion vector component of the horizontal stroke of 4 of 4 x of input, y direction;
If X direction motion vector mvx, minimum 2 bit mvx[1:0] be 00, then this waits to ask pixel to be positioned at whole location of pixels in X direction; If mvx[1:0] be 01, then this waits to ask pixel to be positioned at whole pixel 1/4 location of pixels to the right in X direction; If mvx[1:0] be 10, then this waits to ask pixel to be positioned at whole pixel 1/2 location of pixels to the right in X direction; If mvx[1:0] be 11, then this waits to ask pixel to be positioned at whole pixel 3/4 location of pixels to the right in X direction;
For the motion vector mvy of y direction, then use " downwards " to replace above-mentioned " to the right " to get final product;
According to the residing position of 1/4 pixel of asking that is obtained by said method, 9 select 4 modules to select to determine little foursquare 4 summit A, E, G, the F at pixel X place;
Step (1.7), this 9 select 4 modules step (1.6) resultant be used for further calculating required send into 4 as little foursquare 4 pixels and select 2 modules;
Differentiate with minimum 2 bits of the described motion vector of step (1.6):
If wait to ask 1/4 pixel to be positioned on this little foursquare limit, these 4 two summits selecting 2 these these limits of little square of output; If wait to ask 1/4 pixel to be positioned at this little square central authorities, this 4 selects cornerwise two summits of 2 these little squares of output, and described these two points are the half-pix point;
Step (1.8), these 42 pixels that select 2 modules that step (1.7) is obtained are input to 2 and ask 1 module; This 2 ask 1 module these two points are asked weighted average and finish the house as, promptly obtain 1/4 pixel to be asked;
II is for described chrominance block, calculates currently when waiting to ask 1/8 pixel X ', contains following steps successively:
Step (2.0), initialization, set, whole pixel A ', B ', C ', D ' are 4 points among 2 of one 2 x in current 4 x, 4 chrominance block, and X ' is in the square area of A ', B ', C ', D ' formation, A ', B ', C ', D ' are provided with in the direction of the clock, wherein, A ' is the top left corner apex among 2 of 2 x, with A ' is initial point, abscissa along A '=setting of B ' direction, ordinate along A '=setting of D ' direction, be without loss of generality, might as well establish X ' and be positioned on the A ' B ' of limit;
Step (2.1), described vertical half-pix interpolation filter reads in A ', B ', 4 whole pixels of C ', D ' from reference frame, obtains all 5 half-pix points in the square A ' B ' C ' D ' scope in the following manner:
Half-pix point for being on the whole pixel link position utilizes two whole pixels on the line end points to ask arithmetic mean, promptly obtains the value of this half-pix point; For the half-pix point that is in square A ' B ' C ' D ' center, utilize A ', B ', 4 points of C ', D ' to ask arithmetic mean, promptly obtain the value of this half-pix point;
Step (2.2), step (2.1) described 4 summit A ', B ', C ', D ' and 5 half-pix points totally 9 points send into 9 and select 4 modules;
This 9 selects the minimum 3 bit mvx[2:0s of 4 modules according to motion vector mvx, the mvy of horizontal stroke, the y direction of waiting to ask 1/8 pixel X '], mvy[2:0], determine to wait to ask the residing position of 1/8 pixel X ' as follows:
If mvx[2:0] be 000, then be in the whole location of pixels of X direction; If mvx[2:0] be 001, then be in 1/8 location of pixels of X direction; If mvx[2:0] be 010, then be in 1/4 location of pixels of X direction; If mvx[2:0] be 011, then be in 3/8 location of pixels of X direction; If mvx[2:0] be 100, then be in 1/2 location of pixels of X direction; If mvx[2:0] be 101, then be in 5/8 location of pixels of X direction; If mvx[2:0] be 110, then be in 3/4 location of pixels of X direction; If mvx[2:0] be 111, then be in 7/8 location of pixels of X direction;
For y direction, described " to the right " made into " downwards " get final product;
Step (2.3), this 9 selects the positional information of 4 modules according to the pixel X ' that asks that obtains in the step (2.2), determine X ' residing little foursquare four summit: A ', E ', F ', G ', and the value of A ', E ', F ', G ' is sent into vertical half-pix interpolation filter by a temporary register group;
Step (2.4), described vertical half-pix interpolation filter is according to 4 pixel A ', E ', F ', the G ' of input, calculate 5 1/4 pixels, A ', the E ' of these 5 1/4 pixels and input, F ', G ' constitute the sphere of movements for the elephants shape array of one 3 x 3; The same step of Calculation Method (2.1); Vertically the half-pix interpolation filter is sent into 9 to these 9 points and is selected 4 modules;
Step (2.5), described 9 select 4 modules to find according to the described method of step (2.2) waits to ask pixel X ' residing little foursquare 4 summit A ', H ', I ', J ', and A ', H ', I ', J ' are sent to 4 select 2 modules;
Step (2.6), described 4 select 2 modules to ask 1 module to export the terminal A on a limit at the X ' place of little square A ', H ', I ', J ' to described 2 ', H ';
Step (2.7), described 2 ask 1 module that pixel A ', the H ' that receives asked arithmetic mean, and finish and round off, the 1/8 pixel X ' that obtains being asked.
The H.264 motion compensated interpolation device that the said method that proposes according to the present invention is realized can be saved hardware resource on conventional motion compensates the basis of interpolation device interpolation device, reduce chip area, thereby reduce cost.
Description of drawings
Fig. 1 is the top level structure schematic diagram of motion compensated interpolation device of the present invention.
Fig. 2 is the interpolation flow process of luminance pixel point.This is actually one and constantly dwindles the hunting zone, and calculates the process of desirable value in current scope.
Fig. 3 is the interpolation flow process of chroma pixel point.This is actually one and constantly dwindles the hunting zone, and calculates the process of desirable value in current scope.
Fig. 4 is the shift register group structural representation.This shift register group can be stored 3 pixels importing before current pixel and the current pixel point.Value in left end first each and every one register is directly outputed to horizontal half-pix interpolation filter.O1, o2 port will be output to 9 and select 4 modules, as 2 in 9 points of candidate.Because the position of brightness and colourity candidate's point is different, need export the value of diverse location at the kind of pixel.If what work as pre-treatment is the brightness part, switch need close to the right; Otherwise switch will close to the left.
Fig. 5 is vertical half-pix interpolation filter structural representation.Among this figure, mark have the module of Sx symbol represent will input data to the x position that moves to left.This structure utilization displacement and addition have substituted the multiplying factor operation, have realized the weighted sum function.When handling luminance pixel point, the downward branch road of all MUX is selected, can be used for realizing the interpolation of 6 taps.When handling chroma pixel point, all MUX branch road up or down all can be selected; If upwards branch road is selected, it can be used for the generation of 5 half-pix points, if branch road is selected downwards, it can be used for the generation of vertical half-pix point.
Fig. 6 is horizontal half-pix interpolation filter structural representation.Among this figure, mark have the module of Sx symbol represent will input data to the x position that moves to left.L is a registers group, can be sent to the back one-level with depositing clock of data delay.This structure utilization displacement and addition have substituted the multiplying factor operation, have realized the weighted sum function.It should be noted that displacement only needs the corresponding position of bus is connected, do not need extra hardware resource.Only adopt an adder just to realize 4 multiplying factors operations (multiply by-5,20,20 ,-5 respectively) in 6 tap filters in this structure.When handling luminance pixel point, the branch road that all MUX make progress is selected, can be used for realizing the interpolation of 6 taps; When handling chroma pixel point, the downward branch road of all MUX is selected, can be used for asking the arithmetic mean of two consecutive points.
Fig. 79 selects 4 modular structure schematic diagrames.This module is responsible for selecting 4 points from the point of 9 formation sphere of movements for the elephants shapes of input, is used for next step operation.This function is finished by 4 groups of MUX.Wherein the sel signal is each bit composition among motion vector mvx and the mvy, and is slightly different according to brightness part or chrominance section.
Fig. 84 selects 2 modular structure schematic diagrames.This module is responsible for selecting 2 points from 4 foursquare points of formation of input, is used for next step operation.This module mainly is made of 2 adders and 6 MUX groups.Some intermediate variables when adder is used to handle chrominance section calculating; The processing of the first row MUX as the brightness part played on a left side, and they are responsible for selecting 2 outputs from 4 luminance pixel points of input; The processing of secondary series MUX as chrominance section played on a left side, and they are responsible for 2 outputs of selection from the intermediate object program that 4 chroma pixel points of input and adder are exported; A left side is played the 3rd row MUX and be responsible for selecting one group of output from the result of brightness and colourity.
Fig. 92 asks 1 modular structure schematic diagram.It is average that it utilizes two points importing to make arithmetic, and finish the operation of rounding off.The output of this module is exactly 1/4 luminance pixel point or 1/8 chroma pixel point finally to be asked.
Embodiment
The present invention will be divided into 4 steps to the flow process that the luminance pixel point carries out interpolation.Fig. 2 a to Fig. 2 d is the schematic diagram of this flow process.Suppose that X is 1/4 pixel current to be asked, A, A0, A1, B, B0, B1, C, C0, C1, D, D0 and D1 are near the pixels the X, and their position relation is shown in Fig. 2 a.Then 4 of this flow process steps are as described below.
1. ask the half-pix point.Utilize 6 tap filters (interpolation formula is described suc as formula (1)) to calculate 5 half-pix points.With Fig. 2 is example, and X is for waiting to ask 1/4 pixel, the summit that A, B, four whole pixels of C, D are X place square area.Like this, 5 half-pix points asking of this step are E, F, G, H and I.Wherein, E utilizes the described method of formula (1) to try to achieve, and is input as A, A0, A1, B, B0 and B1; F utilizes the described method of formula (1) to try to achieve, and it is input as F above and below nearest each 3 whole pixels, i.e. J1, J0, A, D, L0, L1; G utilizes the described method of formula (1) to try to achieve, and it is input as left and right-hand each nearest 3 half-pix point on the same horizontal line of G.The computational methods of E, F, G, H and I H.264 standard have had detailed argumentation, therefore are not repeated.After this step is finished, comprise A, B, four whole pixels of C, D (this is original input) and E, F, G, H, five half-pix points of I, all 4 whole pixels and 5 half-pix points all are known in the square area of X place, and they constitute a sphere of movements for the elephants shape.
2. 9 select 4.For the luminance pixel point, minimum 2 bits of motion vector have characterized residing minute location of pixels of this pixel.For example, if minimum 2 bits of the motion vector (being made as mvx) of X direction (mvx[1:0]) be 00, represent that then this pixel is in whole location of pixels in X direction; If mvx[1:0] be 01, represent that then this pixel is in whole pixel 1/4 location of pixels to the right in X direction; If mvx[1:0] be 10, represent that then this pixel is in whole pixel 1/2 location of pixels to the right in X direction; If mvx[1:0] be 11, represent that then this pixel is in whole picture 3/4 location of pixels to the right in X direction.For y direction, also be similarly, as long as " to the right " changed into " to the bottom right miter angle ".Utilize these information, promptly can from 9 points that step 1 obtains, select step 3 and further calculate 4 required points.With Fig. 2 is example, and the X that the X point is corresponding, minimum 2 bits of motion vector of y direction are respectively: 01,01.Utilize these bits, can further determine square (the be square AEGF) inside of X in the upper left of square ABCD.Therefore can select A, E, G and F is that step 3 is further calculated 4 required points.
3. 4 select 2.Step 2 has determined to wait to ask little foursquare 4 summits at 1/4 pixel place.According to standard code, for obtaining this 1/4 pixel, only need from these 4 points, to select two suitable points, ask arithmetic average to get final product.A little being on the little foursquare limit if wait to ask, then is two end points on this limit.Otherwise, if the point of being asked is positioned at central authorities' (being the center of sphere of movements for the elephants) of 4 points, then be little foursquare one cornerwise two end points (because little square has two diagonal, we only export that cornerwise end points that two end points all are half-pix point).With Fig. 2 is example, if 1/4 pixel to be asked is X, the result of this step output is that E and F (notice that E, F are the half-pix points here so.Why not selecting A, G, is because A is not the half-pix point).
4. 2 ask 1.2 points that step 3 is obtained are asked arithmetic average and are finished and round off, and can obtain 1/4 pixel to be asked.
As mentioned above, ask the interpolation process of brightness part 1/4 pixel to be described as: ask the half-pix point=9 select 4=4 select 2=2 ask 1.If current required what find the solution is not point on 1/4 location of pixels, the whole pixel of input or the result in a certain step in step 1~3 directly can be drawn output as interpolation device.
In order on the basis of brightness interpolator, to finish the interpolation of chroma pixel point simultaneously, need make identical transformation to the interpolation formula of chroma pixel point in the standard H.264.If X ' is for waiting that asking sub-pix point, A ', B ', C ', D ' is the adjacent whole pixel of X ' on every side, wherein A ' is the pixel in the upper left corner; If xFracC is abscissa poor of X ' and A ', yFracC is ordinate poor of X ' and A '.H.264 the interpolation formula of standard code chroma pixel point can be described as: X '=((8-xFracC) * (8-yFracC) * A '+xFracC* (8-yFracC) * B '+(8-xFracC) * yFracC*C '+xFracC*yFracC*D '+32)/64 formulas (3)
When reality realizes with hardware, adopt following method to realize:
* yFracC*C '+xFracC*yFracC*D '+32 of * (8-yFracC) * A '+xFracC* (8-yFracC) the * B ' of X1 '=(8-xFracC)+(8-xFracC) can obtain the X ' that asks by X1 ' 6 bits that move to right.
The present invention will be divided into 6 steps to the flow process that the colourity pixel carries out interpolation.Fig. 3 is the schematic diagram of this flow process.Suppose that X ' is 1/4 pixel current to be asked, A ', B ', four adjacent whole pixels of C ', D ' are summits of X ' place square area, and their position relation as shown in Figure 3.Then 6 of this flow process steps are as described below.
1. ask the half-pix point.The way of the arithmetic mean of input whole pixel A ', B ', C ', D ' is asked in utilization, obtains all the half-pix points in the square A ' B ' C ' D '.Wherein, the half-pix point for being on the whole pixel line utilizes 2 whole pixels on the line end points to ask arithmetic average to get final product, and for the half-pix point that is in square center, then asks the arithmetic mean of A ', B ', C ', D ' four numbers.With Fig. 3 is example, E '=(A '+B ')/2; G '=(A '+C ')/2 and F '=(A '+B '+C '+D ')/4.After this step, be that 9 points that constitute sphere of movements for the elephants shapes of the square interior on summit all become known with A ', B ', C ', D '.
2. 9 select 4.For the chroma pixel point, minimum 3 bits of motion vector have characterized residing minute location of pixels of this pixel.Suppose that motion vector is mvx, mvy, if minimum 3 bits of the motion vector (mvx) of X direction (mvx[2:0]) be 000, represent that then this pixel is in whole location of pixels in X direction; If mvx[2:0] be 001, represent that then this pixel is in whole picture 1/8 location of pixels to the right in X direction ... by that analogy, until mvx[2:0] be 111, represent that then this pixel is in whole picture 7/8 location of pixels to the right in X direction.For the motion vector mvy of y direction, also be similarly, as long as " to the right " changed into " downwards ".In this step, utilize mvx[2:1] and mvy[2:1], promptly can from 9 points that step 1 obtains, select step 3 and further calculate 4 required points.With Fig. 3 is example, and the X that X ' point is corresponding, minimum 3 bits of motion vector of y direction are respectively: 001,000.Utilize wherein high-order dibit, can further determine square (be square A ' E ' F ' the G ') inside of X ' in the upper left of square A ' B ' C ' D '.Therefore can be from be that 9 of square interior on summit constitute the point of sphere of movements for the elephants shapes with A ', B ', C ', D ', select A ', E ', G ' and F ' and be further 4 the required points of calculating of step 3.
3. ask the half-pix point.In fact this step is not the point of really obtaining on the half-pixel position.But on step 2 basis, further calculate the point of little square interior.With Fig. 3 is example, and this step is to be foursquare four summits, repeating step 1 with A ', E ', F ' and G ' point.That is to say, in step 1, utilize A ', E ', G ', F ' to replace A ', B ', C ', D ', is exactly step 3.Because the practical operation and the step 1 of this process are just the same, so same called after " is asked the half-pix point ".After finishing this step, be that 9 points that constitute sphere of movements for the elephants shapes of the square interior on summit all become known with A ', E ', G ', F '.
4. 9 select 4.With A ', E ', G ', F ' be 9 of the square interior points that constitute sphere of movements for the elephants shapes on summit as input, repeating step 2 can obtain 4 points of the required further calculating of step 5.The different of this step and step 2 are that the motion vector that this step is used is mvx[1:0], mvy[1:0], and the motion vector that step 2 is used is mvx[2:1], mvy[2:1].With Fig. 3 is example, can select A ', H ', I ', J ' after this step is finished as further operating 4 required points.
5. 4 select 2.4 points that step 4 obtains constitute a little square, wait to ask pixel inevitable in this little square area.This step is according to the diverse location of waiting to ask a little, for step 6 provides different inputs.A little be on the little foursquare limit if wait to ask, then export two end points on this limit of little square to step 6.Otherwise, if the point of being asked is positioned at central authorities' (being the center of sphere of movements for the elephants) of 4 points, then Shu Chu two point values are (A '+B ') and (C '+D '), because (A '+B ') and (C '+D ') asks addition in 1 module can realize the arithmetic average of A ', B ', C ', 4 points of D ' 2.In Fig. 3, this step is output as A ', H '.
6. 2 ask 1.Result to 5 asks arithmetic average, and finishes and round off, and gets final product to such an extent that band waits to try to achieve the value of 1/8 pixel.
From the above mentioned, ask the process of the interpolation of chrominance section 1/8 pixel to be described as: ask the half-pix point=9 select 4=ask the half-pix point=9 select 4=4 select 2=2 ask 1.If current required what find the solution is not point on 1/8 location of pixels, the result in a certain step in the whole pixel or 1~5 of input directly can be drawn output as interpolation device.Can see that chroma pixel interpolation flow process can obtain by went on foot, insert once more between the 3rd step the 1st, the 2nd step in the 2nd of interpolation of luminance pixels.
The hardware multiplexing structure of chroma interpolation of the present invention and brightness interpolating, feature is as follows:
1. in above-mentioned colourity and brightness interpolating flow process, the step that has identical abbreviation is shared identical hardware resource.For example, the half-pix point of asking in half-pix point and the chroma interpolation of asking in the brightness interpolating is shared same hardware module; In the brightness interpolating 9 select 4 and chroma interpolation in 9 select 4 to share same hardware modules; In the brightness interpolating 4 select 2 and chroma interpolation in 4 select 2 to share same hardware modules or the like.
2. make up the skeleton of interpolation device structure according to luminance pixel point interpolation flow process, rely on this skeleton can finish the luminance pixel point interpolation.
9 of 2 described skeletons select 4 and half-pix dot generation step between add feedback control loop, in order to finish the chroma pixel point interpolation.
4. the chroma pixel point interpolation is divided into two beats and finishes.Input interpolation initial data in first beat is up to finishing the. and inferior 9 select 4.Second beat will 9 select 4 result to feed back to half-pix dot generation unit (vertically half-pix point interpolation filter can serve as half-pix dot generation unit) for the first time, ask end product until finishing.
Fig. 1 is the top level structure figure of the motion compensated interpolation device that designs of the present invention.The operation principle of this structure is described in conjunction with Fig. 1 herein.
To the handling principle of brightness part as described in this section.The data of motion compensated interpolation device are input as the data of reading in from reference frame.Each clock cycle is imported 6 adjacent whole pixels (next clock cycle, 6 adjacent whole pixels of the adjacent row in input right side) of same row.With Fig. 1 is example, and 6 some J1, J0, A, D, L0, L1 of the input of interpolation device input correspond respectively to the same place among Fig. 2.Thus, next clock cycle, interpolation device input just becoming K1, K0, B, C, M0, M1.
Six points supposing the present clock period input are J1, J0, A, D, L0, L1.These six points at first enter vertical half-pix point interpolation filter, and this filter is to some perfect (1) the operation described of these six inputs, and export a half-pix point F.F is positioned at the mid point of A and D line.The F point is output in the shift register group 2 standby.Meanwhile, it is standby that A and D also are imported into shift register group 1 and 3 kind respectively, and other 4 inputs then do not need to be used to again, can abandon.
3 shift register group are exported to other modules to suitable operating point according to the current position a little of asking.On the one hand, shift register group selects 4 modules for its selection the known point input 9 of self storing; On the other hand, it also provides the input data for horizontal half-pix interpolation filter.The output of all horizontal half-pix filters and shift register group is all as 9 inputs of selecting 4 modules.Such output has 9.With the some X in the calculating chart 2 is example: shift register group 1 output A, B, laterally half-pix filter 1 output E; Shift register group 2 output F, H, laterally half-pix filter 2 output G; Shift register group 3 output D, C, laterally half-pix filter 3 output I.
Afterwards, selected 4 modules to select by 9 at these 9 o'clock, finish above said 9 and select 4 steps, obtain 4 points.These 4 points enter 4 and select 2 modules, finish mentioned above 4 and select 2 steps.4 select 2 outputs of 2 modules to enter 2 asks 1 module, and finish 2 and ask 1 step, thus the value of the 1/4 luminance pixel point that obtains being asked.When handling luminance pixel point, the outer switch of the iA of vertical half-pix interpolation filter and iB port can close to any one side among Fig. 1, and it does not exert an influence to result; 9 select the switch of 4 module porch must close downwards, promptly are connected to the output of horizontal half-pix filter and shift register group.
To the operation of chrominance section as described in this section.When chrominance section was operated, the data of motion compensated interpolation device were input as 2 vertical adjacent whole pixels that read in from reference frame.The interpolation process of chrominance section is divided into two beats.In first beat, the outer switch of the iA of vertical half-pix interpolation filter and iB port closes left among Fig. 1, connects A ' and D ' (A ', the D ' of this moment are corresponding to the same place among Fig. 3).2 the vertical adjacent whole pixel A ' and the D ' of this moment input enter vertical half-pix interpolation filter.Vertically the half-pix interpolation filter calculates the half-pix point (G ' among Fig. 3) of these two some line mid points at once.This half-pix point is output in the shift register group 2 standby.Meanwhile, it is standby that A ' and D ' also are imported into shift register group 1 and 3 kind respectively.After this, the work of shift register group and horizontal half-pix interpolation filter is the same with to the luminance pixel point operation time, and the point (4 whole pixels and 5 half-pix points) of exporting 9 sphere of movements for the elephants shapes is united in their cooperations.When first beat, 9 select the switch of 4 module porch must close downwards, promptly are connected to the output of horizontal half-pix filter and shift register group.9 select the output of 4 modules to be deposited in the temporary register heap.The temporary register heap is made up of 4 register files, and each register file is deposited the data of a point.When second beat, the outer switch of the iA of vertical half-pix interpolation filter and iB port closes to the right among Fig. 1, connects the data of temporary register heap.4 outputs of 4 modules are selected in iA~iD input 9,5 points after oa~oe output is calculated.9 points on iA~iD and the oa~oe constitute a sphere of movements for the elephants shape on the position.Vertical half-pix filtering interpolation is at this time finished is step 3 in the chroma operation flow process.In second beat, 9 select the switch of 4 module porch must close upward, and the iA~iD of beat one generation and 9 somes inputs 9 on oa~oe are selected 4 modules, finish above said 9 and select 4 steps, obtain 4 points.These 4 points enter 4 and select 2 modules, finish mentioned above 4 and select 2 steps.4 select 2 outputs of 2 modules to enter 2 asks 1 module, and finish 2 and ask 1 step, thus the value of the 1/8 chroma pixel point that obtains being asked.

Claims (1)

1. the motion compensation interpolation method of decoder H.264 is characterized in that described method realizes on ASIC, wherein, realizes according to the following steps respectively for the luminance block of 4 x, 4 sizes and the chrominance block of 4 x, 4 sizes:
I. for described luminance block, calculate when waiting to ask current 1/4 pixel X, contain following steps successively:
Step (1.0), initialization, set whole pixel A, B, C, D is 4 points among 2 of one 2 x in current 4 x, 4 luminance block, and X is in A, B, C, in the square area that D constitutes, A, B, C, D is provided with in the direction of the clock, wherein, A is the top left corner apex among 2 of 2 x, with A is initial point, abscissa is along A=〉setting of B direction, ordinate is along A=〉setting of D direction, A, A0, A1 waits to ask near the upside of the 1/4 pixel X square adjacent whole pixel that makes progress against the current, B, B0, B1 be successively near the X upside downstream square to adjacent whole pixel, D, D0, D1 be successively the X downside against the current square to adjacent whole pixel, C, C0, C1 is the X downside square adjacent whole pixel that makes progress downstream, in like manner, A, J0, J1 and D, L0, L1 is respectively that the left side is contrary near this pixel X, along the adjacent whole pixel of vertical direction, B, K0, K1 and C, M0, M1 is respectively that the right side is contrary near this pixel X, along the adjacent whole pixel on the vertical direction; E, H, I, F are the mid point of line segment AB, BC, CD, DA successively, all are the half-pix points, and G is the mid point of line segment FH, are the half-pix point, and F1, F0, F and H1, H0, H are respectively the same horizontal left of half-pix point G and right-hand 3 nearest half-pix points;
Step (1.1), deposit the value of whole pixel A1, A0, A, B, B0, B1 at horizontal half-pix interpolation filter 1, deposit the value of half-pix point F1, F0, F, H, H0, H1 at horizontal half-pix interpolation filter 2, deposit the value of putting in order pixel D1, D0, D, C, C0, C1 at horizontal half-pix interpolation filter 3;
Step (1.2), in first clock cycle, carry out following steps:
Vertically the half-pix interpolation filter reads in 6 adjacent whole pixels that whole pixel A, D one are listed as from reference frame, is followed successively by J1, J0, A, D, L0, L1 from top to bottom, and calculates the value of half-pix point F as follows:
F=(J1-5 * J0+20 * A+20 * D-5 * L0+L1+16)/32, this vertical half-pix interpolation filter is sent into shift register group 2 to the value of half-pix point F respectively, whole pixel A is sent into shift register group 1, whole pixel D is sent into shift register group 3;
Step (1.3), carry out following step successively second clock cycle:
This vertical half-pix interpolation filter reference frame reads in 6 adjacent whole pixels of whole pixel B, C place one row, is followed successively by K1, K0, B, C, M0, M1 from top to bottom, and obtains the value of half-pix point H as follows:
(K1-5 * K0+20 * B+20 * D-5 * M0+M1+16)/32, this vertical half-pix interpolation filter is sent into shift register group 2 to half-pix point H respectively to H=, and whole pixel B is sent into shift register group 1, and whole pixel C is sent into shift register group 3;
Step (1.4), shift register group 1 is sent into horizontal half pixel digital difference detector 1 to whole pixel A1, A0, A, B, B0, B1, and this interpolation filter calculates the value of half-pix point E according to following formula:
E=(A1-5×A0+20×A+20×B-5×B0+B1+16)/32;
Shift register group 3 is sent into horizontal half pixel digital difference detector 3 to whole pixel D1, D0, D, C, C0, C1, and this interpolation filter calculates the value of half-pix point I according to following formula:
I=(D1-5×D0+20×D+20×C-5×C0+C1+16)/32;
Shift register group 2 is sent into horizontal half pixel digital difference detector 2 to half-pix point F1, F0, F, H, H0, H1, and this interpolation filter calculates the value of half-pix point G according to following formula:
G=(F1-5×F0+20×F+20×H-5×H0+H1+16)/32;
Step (1.5), shift register group 1 be the value of whole pixel A, B, and shift register group 2 is the value of whole pixel F, H,
Shift register group 3 is the value of whole pixel C, D, laterally half-pix interpolation filter 1 is the value of half-pix point E, laterally half-pix interpolation filter 2 is the value of half-pix point G, and laterally half-pix interpolation filter 3 is the value of half-pix point I, walks abreast to send into 9 and select 4 modules;
Step (1.6), this 9 selects 4 modules to determine the residing position of 1/4 pixel of asking by minimum 2 bits of the motion vector component of the horizontal stroke of 4 of 4 x of input, y direction;
If the minimum 2 bit mvx[1:0 of X direction motion vector mvx] be 00, then this waits to ask pixel to be positioned at whole location of pixels in X direction; If mvx[1:0] be 01, then this waits to ask pixel to be positioned at whole pixel 1/4 location of pixels to the right in X direction; If mvx[1:0] be 10, then this waits to ask pixel to be positioned at whole pixel 1/2 location of pixels to the right in X direction; If mvx[1:0] be 11, then this waits to ask pixel to be positioned at whole pixel 3/4 location of pixels to the right in X direction;
For the motion vector mvy of y direction, then use " downwards " to replace above-mentioned " to the right " to get final product;
According to the residing position of 1/4 pixel of asking that is obtained by said method, 9 select 4 modules to select to determine little foursquare 4 summit A, E, G, the F at pixel X place;
Step (1.7), this 9 select 4 modules step (1.6) resultant be used for further calculating required send into 4 as little foursquare 4 pixels and select 2 modules;
Differentiate with minimum 2 bits of the described motion vector of step (1.6):
If wait to ask 1/4 pixel to be positioned on this little foursquare limit, these 4 two summits selecting 2 these these limits of little square of output; If wait to ask 1/4 pixel to be positioned at this little square central authorities, this 4 selects cornerwise two summits of 2 these little squares of output, and described these two points are the half-pix point;
Step (1.8), these 42 pixels that select 2 modules that step (1.7) is obtained are input to 2 and ask 1 module; This 2 ask 1 module these two points are asked weighted average and finish the house as, promptly obtain 1/4 pixel to be asked;
II is for described chrominance block, calculates currently when waiting to ask 1/8 pixel X ', contains following steps successively:
Step (2.0), initialization, set, whole pixel A ', B ', C ', D ' are 4 points among 2 of one 2 x in current 4 x, 4 chrominance block, and X ' is in the square area of A ', B ', C ', D ' formation, A ', B ', C ', D ' are provided with in the direction of the clock, wherein, A ' is the top left corner apex among 2 of 2 x, with A ' is initial point, abscissa along A '=setting of B ' direction, ordinate along A '=setting of D ' direction, be without loss of generality, might as well establish X ' and be positioned on the A ' B ' of limit;
Step (2.1), described vertical half-pix interpolation filter reads in A ', B ', 4 whole pixels of C ', D ' from reference frame, obtains all 5 half-pix points in the square A ' B ' C ' D ' scope in the following manner:
Half-pix point for being on the whole pixel link position utilizes two whole pixels on the line end points to ask arithmetic mean, promptly obtains the value of this half-pix point; For the half-pix point that is in square A ' B ' C ' D ' center, utilize A ', B ', 4 points of C ', D ' to ask arithmetic mean, promptly obtain the value of this half-pix point;
Step (2.2), step (2.1) described 4 summit A ', B ', C ', D ' and 5 half-pix points totally 9 points send into 9 and select 4 modules;
This 9 selects the minimum 3 bit mvx[2:0s of 4 modules according to motion vector mvx, the mvy of horizontal stroke, the y direction of waiting to ask 1/8 pixel X '], mvy[2:0], determine to wait to ask the residing position of 1/8 pixel X ' as follows:
If mvx[2:0] be 000, then be in the whole location of pixels of X direction; If mvx[2:0] be 001, then be in 1/8 location of pixels of X direction; If mvx[2:0] be 010, then be in 1/4 location of pixels of X direction; If mvx[2:0] be 011, then be in 3/8 location of pixels of X direction; If mvx[2:0] be 100, then be in 1/2 location of pixels of X direction; If mvx[2:0] be 101, then be in 5/8 location of pixels of X direction; If mvx[2:0] be 110, then be in 3/4 location of pixels of X direction; If mvx[2:0] be 111, then be in 7/8 location of pixels of X direction;
For y direction, described " to the right " made into " downwards " get final product;
Step (2.3), this 9 selects the positional information of 4 modules according to the pixel X ' that asks that obtains in the step (2.2), determine X ' residing little foursquare four summit: A ', E ', F ', G ', and the value of A ', E ', F ', G ' is sent into vertical half-pix interpolation filter by a temporary register group;
Step (2.4), described vertical half-pix interpolation filter is according to 4 pixel A ', E ', F ', the G ' of input, calculate 5 1/4 pixels, A ', the E ' of these 5 1/4 pixels and input, F ', G ' constitute the sphere of movements for the elephants shape array of a 3x3; The same step of Calculation Method (2.1); Vertically the half-pix interpolation filter is sent into 9 to these 9 points and is selected 4 modules;
Step (2.5), described 9 select 4 modules to find according to the described method of step (2.2) waits to ask pixel X ' residing little foursquare 4 summit A ', H ', I ', J ', and A ', H ', I ', J ' are sent to 4 select 2 modules;
Step (2.6), described 4 select 2 modules to ask 1 module to export the terminal A on a limit at the X ' place of little square A ', H ', I ', J ' to described 2 ', H ';
Step (2.7), described 2 ask 1 module that pixel A ', the H ' that receives asked arithmetic mean, and finish and round off, the 1/8 pixel X ' that obtains being asked.
CN 200610144288 2006-12-01 2006-12-01 A motion compensation interpolation method for H.264 decoder Active CN100493192C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200610144288 CN100493192C (en) 2006-12-01 2006-12-01 A motion compensation interpolation method for H.264 decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200610144288 CN100493192C (en) 2006-12-01 2006-12-01 A motion compensation interpolation method for H.264 decoder

Publications (2)

Publication Number Publication Date
CN1964493A CN1964493A (en) 2007-05-16
CN100493192C true CN100493192C (en) 2009-05-27

Family

ID=38083332

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200610144288 Active CN100493192C (en) 2006-12-01 2006-12-01 A motion compensation interpolation method for H.264 decoder

Country Status (1)

Country Link
CN (1) CN100493192C (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100576918C (en) * 2007-06-27 2009-12-30 中国科学院微电子研究所 A kind of AVS interframe predicting pixel generating apparatus
US8509567B2 (en) * 2007-07-09 2013-08-13 Analog Devices, Inc. Half pixel interpolator for video motion estimation accelerator
CN101179726B (en) * 2007-12-12 2010-09-29 北京中星微电子有限公司 Motion estimating method and device
CN101527843B (en) * 2008-03-07 2011-01-26 瑞昱半导体股份有限公司 Device for decoding video block in video screen and related method thereof
CN101355704B (en) * 2008-08-15 2011-11-30 北京中星微电子有限公司 Computation method and apparatus for one-third insertion value of chromaticity
CN101527847B (en) * 2009-01-04 2012-01-04 炬力集成电路设计有限公司 Motion compensation interpolation device and method
CN101783947B (en) * 2010-02-05 2011-11-23 合肥工业大学 Luminance interpolating method of H.264 decoder based on symmetry of interpolation algorithm
CN102026005B (en) * 2010-12-23 2012-11-07 芯原微电子(北京)有限公司 Operation method for H.264 chromaticity interpolated calculation
CN102123235B (en) * 2011-03-24 2013-07-17 杭州海康威视数字技术股份有限公司 Method and device for generating video interpolation frame
CN102752585B (en) * 2011-04-18 2015-04-15 联咏科技股份有限公司 Data processing method and digital image processing device
CN103974078B (en) * 2014-03-31 2017-10-31 北京大学深圳研究生院 A kind of interpolation method and wave filter for colourity
CN114365494A (en) * 2019-09-02 2022-04-15 北京字节跳动网络技术有限公司 Improvement of MERGE candidates

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1703094A (en) * 2004-05-28 2005-11-30 三星电子株式会社 Image interpolation apparatus and methods that apply quarter pel interpolation to selected half pel interpolation results
US20050265451A1 (en) * 2004-05-04 2005-12-01 Fang Shi Method and apparatus for motion compensated frame rate up conversion for block-based low bit rate video
CN1756357A (en) * 2004-09-30 2006-04-05 株式会社东芝 Information processing apparatus and program for use in the same
CN1859553A (en) * 2005-05-06 2006-11-08 三星电子株式会社 Image conversion apparatus to perform motion compensation and method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050265451A1 (en) * 2004-05-04 2005-12-01 Fang Shi Method and apparatus for motion compensated frame rate up conversion for block-based low bit rate video
CN1703094A (en) * 2004-05-28 2005-11-30 三星电子株式会社 Image interpolation apparatus and methods that apply quarter pel interpolation to selected half pel interpolation results
CN1756357A (en) * 2004-09-30 2006-04-05 株式会社东芝 Information processing apparatus and program for use in the same
CN1859553A (en) * 2005-05-06 2006-11-08 三星电子株式会社 Image conversion apparatus to perform motion compensation and method thereof

Also Published As

Publication number Publication date
CN1964493A (en) 2007-05-16

Similar Documents

Publication Publication Date Title
CN100493192C (en) A motion compensation interpolation method for H.264 decoder
US5553208A (en) Image synthesizing system having a field buffer unit that stores texture coordinates
CN1922630B (en) Image processing device, image processing system, image processing method, and integrated circuit device
JP2628493B2 (en) Image coding device and image decoding device provided with cosine transform calculation device, calculation device and the like
US4580134A (en) Color video system using data compression and decompression
US20020051496A1 (en) Deblocking filtering apparatus and method
US8509567B2 (en) Half pixel interpolator for video motion estimation accelerator
US5559937A (en) Clipping processing device, three-dimensional simulator device, and clipping processing method
US6366290B1 (en) Dynamically selectable texture filter for a software graphics engine
CN104717485A (en) VGA interface naked-eye 3D display system based on FPGA
JPH04204496A (en) Display control device
JPH0695631A (en) Image processing method and its device
JPH01145778A (en) Image processor having pipeline bus of free flow
CN110246080A (en) Demosaicing methods and its system
CN1179552C (en) Device for converting video format
CN111488963A (en) Neural network computing device and method
CN101888554A (en) VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter
CN107277551B (en) A kind of Approximation Discrete cosine transform method for image procossing
CN100553341C (en) Device for detecting motion vector and motion vector detecting method
JPH11346369A (en) Motion vector detection circuit
CN105578189B (en) Efficient video coding add tree Parallel Implementation method based on asymmetric partition mode
CN101452572B (en) Image rotating VLSI structure based on cubic translation algorithm
JP2914241B2 (en) Image processing device
CN101364401A (en) Color management system and driving method thereof
CN117440168B (en) Hardware architecture for realizing parallel spiral search algorithm

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: BEIJING HUAXIA DIANTONG TECHNOLOGY CO., LTD.

Free format text: FORMER OWNER: TSINGHUA UNIVERSITY

Effective date: 20120823

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 100084 HAIDIAN, BEIJING TO: 100085 HAIDIAN, BEIJING

TR01 Transfer of patent right

Effective date of registration: 20120823

Address after: 100085 A, block 9, 3rd Street, Beijing, Haidian District, A301

Patentee after: Beijing Powercom Technologies Co., Ltd.

Address before: 100084 Beijing 100084-82 mailbox

Patentee before: Tsinghua University

C56 Change in the name or address of the patentee
CP03 Change of name, title or address

Address after: 100094, No. 6, building, No. 3, Feng Xiu Middle Road, Beijing, Haidian District

Patentee after: Beijing Huaxia Diantong Technology Co., Ltd.

Address before: 100085 A, block 9, 3rd Street, Beijing, Haidian District, A301

Patentee before: Beijing Powercom Technologies Co., Ltd.

CP01 Change in the name or title of a patent holder

Address after: 100094, No. 6, building, No. 3, Feng Xiu Middle Road, Beijing, Haidian District

Patentee after: BEIJING HUAXIA DENTSU TECHNOLOGY Co.,Ltd.

Address before: 100094, No. 6, building, No. 3, Feng Xiu Middle Road, Beijing, Haidian District

Patentee before: BEIJING CHINASYS TECHNOLOGIES Co.,Ltd.

CP01 Change in the name or title of a patent holder