CN100492617C - Making method of the pixel structure and pixel structure - Google Patents
Making method of the pixel structure and pixel structure Download PDFInfo
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- CN100492617C CN100492617C CNB2007100974827A CN200710097482A CN100492617C CN 100492617 C CN100492617 C CN 100492617C CN B2007100974827 A CNB2007100974827 A CN B2007100974827A CN 200710097482 A CN200710097482 A CN 200710097482A CN 100492617 C CN100492617 C CN 100492617C
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Abstract
The present invention discloses a production method of the pixel structure, including the following steps: firstly providing one substrate with a pixel area; forming a metal layer, a gate insulation layer, and a semiconductor layer on the substrate, and patterning them by a first partly-adjustable or gray-adjustable light shield, to form a transistor pattern, a lower layer capacitance pattern and a lower layer circuit pattern; then, orderly forming a dielectric layer and one electrode layer to cover the said three patterns, then patterning them to expose some lower layer circuits, lower layer capacitances and onesource/drain area of the transistor pattern, and creating a second metal layer on them; then, patterning the second metal layer and the electrode layer by a second partly-adjustable or gray-adjustable light shield to form a upper layer circuit, a source/drain pattern and a upper layer capacitance, and part of the electrode layer constituting a pixel electrode.
Description
Technical field
The present invention relates to a kind of production method of pixel structure, and particularly relevant for a kind of production method of pixel structure of using less photomask.
Background technology
Along with modern video signal development of technology, various display has been used in mobile phone, mobile computer, digital camera and personal digital assistant in large quantities, and (personal digital assistant PDA) waits on the display screen of consumption electronic products.In these displays, because LCD (liquid crystal display, LCD) and organic electro-luminescent display (organic electroluminescence display, OELD) have in light weight, advantage such as volume is little and power consumption is low, make it become the main flow on the market.No matter be LCD or organic electro-luminescent display, its manufacturing process includes with semiconductor process and form the dot structure that array is arranged on substrate.
Figure 1A～Fig. 1 G illustrates the section flow chart of a kind of one pixel structure process method of prior art.At first, please refer to Figure 1A, at first utilize and on a substrate 10, form a grid (gate) 20.Then, shown in Figure 1B, on substrate 10, form one first dielectric layer 30 with cover gate 20.Then, shown in Fig. 1 C, on first dielectric layer 30, form a channel layer 40.Afterwards, shown in Fig. 1 D, form one source pole (source) 50 and drain electrode (drain) 60 in channel layer (channel) 40 tops.Then, shown in Fig. 1 E, on substrate 10, form one second dielectric layer 70 to cover channel layer 40, source electrode 50 and to drain 60.Then, shown in Fig. 1 F, on second dielectric layer 70, make a contact hole H.Afterwards, shown in Fig. 1 G, form a pixel electrode 80 on second dielectric layer 70, this pixel electrode 80 is that part is inserted among the contact hole H and electrically connected with drain electrode 60.So, the making of dot structure 90 is just roughly finished.
In sum, the making of the dot structure 90 of prior art mainly is to form grid 20 by first photomask, second photomask forms channel layer 40, the 3rd photomask forms source electrode 50 and drains 60, the 4th photomask forms contact hole H, and the 5th photomask forms pixel electrode 80, so the making of dot structure 90 is the operations that adopt five road photomasks, therefore making step is more, and Production Time is longer.When making step was more complicated, the chance of dot structure 90 generation defectives was higher, and the production qualification rate is also lower.In addition, the making of the dot structure 90 of prior art is the Production Time of adopting more making step and cost long, no matter be the board equipment fixed cost of buying more or the material cost of producing on utilizing all can make total production cost uprise.
Summary of the invention
Technical problem to be solved by this invention is, a kind of production method of pixel structure of less photomask operation is provided, and it is suitable for reducing the required number of optical mask of operation, and then reduces cost of manufacture.
For achieving the above object, a kind of production method of pixel structure is proposed at this.At first, provide a substrate with a pixel region.Then, on substrate, form laminated that a first metal layer, a gate insulation layer and semi-conductor layer form in regular turn.Then, formed laminated via one the first half mode (half-tone) or grey mode (gray-tone) photomask patternization by the first metal layer, gate insulation layer and semiconductor layer, in other embodiments, patterning is above-mentioned laminatedly also can finish via two photomask operations of different exposure energies.Hold above-mentionedly, form a transistor pattern, once layer capacitance pattern and layer line road pattern once, wherein the transistor pattern comprises the first metal layer, gate insulation layer and semiconductor layer respectively with following layer capacitance pattern, and lower floor's line pattern comprises the first metal layer.The material of above-mentioned gate insulation layer for example is silica, silicon nitride or organic material, and the material of semiconductor layer for example is amorphous silicon or polysilicon.Afterwards, form a dielectric layer and an electrode layer more in regular turn on substrate, wherein dielectric layer and electrode layer covering transistor pattern, down layer capacitance pattern and lower floor's line pattern, and the material of electrode layer for example is a transparent conductive material.Then, pattern dielectric layer and electrode layer make it form a pattern dielectric layer and patterned electrode layer, to expose the source of part lower floor line pattern, the following layer capacitance pattern of part and transistor pattern.Afterwards, form one second metal level on electrode layer, and make second metal level be electrically connected to the source/drain regions of lower floor's line pattern, following layer capacitance pattern and transistor pattern.At last, via one the second half mode or grey mode photomask patternization second metal level and electrode layer,, can certainly come patterning second metal level by two photomask operations of different exposure energies to form a patterning second metal level.Wherein form layer capacitance pattern on a upper layer circuit pattern, the source pattern and behind patterning second metal level, and the patterned electrode layer that exposes part of second metal level in the pixel region is with as a pixel electrode.In sum, by the dot structure of above-mentioned steps made comprise that the patterning that is disposed on the substrate is laminated, pattern dielectric layer, patterned electrode layer and patterning second metal level.
In one embodiment of this invention, more be included in after pattern dielectric layer and the electrode layer, with the dielectric layer of patterning and electrode layer as mask, the part semiconductor layer of following layer capacitance pattern and the semiconductor layer of source/drain regions are carried out ion doping and form a doping semiconductor layer, and wherein ion doping for example is P type ion doping or N type ion doping.
In one embodiment of this invention, also be included in after pattern dielectric layer and the electrode layer, form a doping semiconductor layer on electrode layer, and make doping semiconductor layer be connected to lower floor's line pattern, the source/drain regions of following layer capacitance pattern and transistor pattern, so that patterning second metal level of follow-up formation contacts with other rete via doping semiconductor layer, in addition, when coming patterning second metal level and electrode layer via the second half modes or grey mode photomask, while patterning doping semiconductor layer is so that doping semiconductor layer has identical pattern with second metal level.In this manufacture method, doping semiconductor layer comprises P type doping semiconductor layer or N type doping semiconductor layer.
In one embodiment of this invention; also be included in and form after second metal level; form a protective layer on second metal level; and when coming patterning second metal level and electrode layer via the second half modes or grey mode photomask; while patterning protective layer; so that protective layer has identical pattern with second metal level, and the material of protective layer for example is silica, silicon nitride or organic material.
In one embodiment of this invention, come the method for patterning the first metal layer, gate insulation layer and semiconductor layer to comprise the following steps: at first, form one first photoresist layer on semiconductor layer via the first half modes or grey mode photomask.Then, via the first half modes or grey mode photomask first photoresist layer is carried out little shadow operation, have a transistor photoresist pattern of first thickness and layer capacitance photoresist pattern once in pixel region, to form, and form the road of the layer line once photoresist pattern with second thickness outside pixel region, wherein first thickness is greater than second thickness.Afterwards, with first photoresist layer is that mask carries out etching to the first metal layer, gate insulation layer and semiconductor layer, forms the lower floor's line pattern, the transistor pattern and following layer capacitance pattern that correspond respectively to lower floor's circuit photoresist pattern, transistor photoresist pattern and following layer capacitance photoresist pattern.Then, remove the segment thickness of transistor photoresist pattern, the following semiconductor layer in segment thickness, lower floor's circuit photoresist pattern and the lower floor's line pattern of layer capacitance photoresist pattern.In other embodiments, removing lower floor's line pattern comprises and removes gate insulation layer.At last, remove remaining first photoresist layer again.
In one embodiment of this invention, comprise the following steps: at first, form one second photoresist layer on second metal level via the method for the second half modes or grey mode photomask patternization second metal level and electrode layer.Then, via the second half modes or grey mode photomask second photoresist layer is carried out little shadow operation, outside pixel region, to form a upper layer circuit photoresist pattern with the 3rd thickness, and a pixel electrode photoresist pattern that forms layer capacitance photoresist pattern on the source photoresist pattern and with the 3rd thickness and have the 4th thickness in pixel region, wherein the 3rd thickness is greater than the 4th thickness.Afterwards, with second photoresist layer is that mask carries out etching to second metal level and electrode layer, and formation corresponds respectively to source/drain photoresist pattern, goes up the source/drain pattern of layer capacitance photoresist pattern and upper layer circuit photoresist pattern, goes up layer capacitance pattern and upper layer circuit pattern.Then, carry out an ashing (ashing) operation, with the segment thickness that removes source/drain photoresist pattern, the segment thickness of going up layer capacitance photoresist pattern and the segment thickness and the pixel electrode photoresist pattern of upper layer circuit photoresist pattern.Then, remove electrode layer that second metal level corresponding to pixel electrode pattern exposes part with as pixel electrode.At last, remove remaining second photoresist layer.
In one embodiment of this invention, also be included in when via the second half modes or grey mode photomask second photoresist layer being carried out little shadow operation, formation has a connection pad photoresist pattern of the 4th thickness pixel region outside simultaneously.Then, carry out an ashing operation, to remove connection pad photoresist pattern, wherein ashing operation for example is an oxygen electricity slurry ashing operation.Then, remove corresponding to second metal level of connection pad photoresist pattern forming a connection pad pattern, and this connection pad pattern connects upper layer circuit pattern.
The present invention proposes another kind of production method of pixel structure, and it omits the making in zones such as above-mentioned lower floor's line pattern and upper layer circuit pattern, and the making flow process is similar to the above.In detail, the dot structure of finishing with this manufacture method made comprise that a substrate, a patterning are laminated, a pattern dielectric layer, a patterned electrode layer and a patterning second metal level.Patterning is laminated to comprise a first metal layer, a gate insulation layer and semi-conductor layer, and forms a transistor pattern and layer capacitance pattern once on substrate.Above-mentioned pattern dielectric layer is disposed on the substrate and covering transistor pattern and following layer capacitance pattern, and pattern dielectric layer exposes partly the source of layer capacitance pattern and transistor pattern down.In addition, patterned electrode layer is disposed on the pattern dielectric layer, and wherein the material of electrode layer for example is a transparent conductive material.In addition, patterning second metal level is disposed on the patterned electrode layer, comprise layer capacitance pattern on source pattern and, wherein source/drain pattern and last layer capacitance pattern are connected to source/drain regions and following layer capacitance pattern respectively, and patterning second metal level exposes the patterned electrode layer of part as a pixel electrode.In other words, this manufacture method only keeps the making of transistor pattern, electric capacity pattern and patterned electrode layer in the pixel region, and gets rid of the making of the outer circuit pattern of pixel region.Configuration, composition and making flow process as for each member of back that completes are all similar with above-mentioned production method of pixel structure, just do not add at this and do not give unnecessary details.
The present invention reintroduces a kind of production method of pixel structure, its make flow process and above-mentioned production method of pixel structure similar, except the making of omitting upper and lower layer line road area of the pattern, also got rid of the making of the electric capacity area of the pattern of upper strata, lower floor.In detail, the dot structure with this manufacture method made comprises a substrate, a transistor pattern, a pattern dielectric layer, a patterned electrode layer and a patterning second metal level.The transistor pattern setting is on substrate, and the transistor pattern comprises a first metal layer, a gate insulation layer and semi-conductor layer.Above-mentioned pattern dielectric layer is disposed on the substrate and the covering transistor pattern, and pattern dielectric layer exposes the source of transistor pattern.In addition, patterned electrode layer is disposed on the pattern dielectric layer, and wherein the material of electrode layer comprises transparent conductive material.In addition, patterning second metal level is disposed on the patterned electrode layer, and patterning second metal level comprises the source pattern, and the source/drain pattern is connected to source/drain regions, and patterning second metal level exposes the patterned electrode layer of part, with as a pixel electrode.In other words, this manufacture method only keeps the making of interior transistor pattern of pixel region and patterned electrode layer, and gets rid of the making of interior electric capacity pattern of pixel region and the outer circuit pattern of pixel region.Configuration, composition and making flow process as for each member of back that completes are all similar with above-mentioned production method of pixel structure, just do not add at this and do not give unnecessary details.
The present invention adopts the operation of less photomask, not only can save the cost of photomask compared to five road photomask operations of prior art, also can lower because of the tediously long defective that causes of operation.In addition, in a dot structure of the present invention, transistor uses the structure of bottom grid, can reduce photoelectric current, keeps performance of transistors.In addition, transistorized structure adopts the design of etch stop layer (Etching Stop Layer), can promote the characteristic of driving component, and improves the production qualification rate.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A～Fig. 1 G is a kind of one pixel structure process method of prior art;
Fig. 2 A～Fig. 2 J is the production method of pixel structure of first embodiment of the invention;
Fig. 3 A～Fig. 3 I is the production method of pixel structure of second embodiment of the invention.
Wherein, Reference numeral is:
10,210: substrate
20: grid
30: the first dielectric layers
40: channel layer
50,250a: source electrode
60,250b: drain electrode
70: the second dielectric layers
80,296: pixel electrode
90,200,300: dot structure
220: the first metal layer
230: gate insulation layer
240: semiconductor layer
240 ': doping semiconductor layer
242: the first photoresist layers
242a: transistor photoresist pattern
242b: following layer capacitance photoresist pattern
242c: lower floor's circuit photoresist pattern
250: the transistor pattern
250a: the source area of transistor pattern
250b: the drain region of transistor pattern
252a: source electrode pattern
252b: drain pattern
256: patterning is laminated
260: following layer capacitance pattern
262: go up the layer capacitance pattern
270: lower floor's line pattern
272: the upper layer circuit pattern
280: dielectric layer
282: the pattern photoresist layer
290: electrode layer
292: the second metal levels
293: protective layer
294: the second photoresist layers
294a: source/drain photoresist pattern
294b: go up layer capacitance photoresist pattern
294c: upper layer circuit photoresist pattern
294d: pixel electrode photoresist pattern
294e: connection pad photoresist pattern
296: pixel electrode
298: the connection pad pattern
D: ion doping
H: opening
H1: first thickness
H2: second thickness
H3: the 3rd thickness
H4: the 4th thickness
M1: the first half mode or grey mode photomasks
M2: the second half mode or grey mode photomasks
P: pixel region
Embodiment
A kind of pixel structure preparation method and dot structure that is suitable for using less photomask operation proposed in the present invention, this production method of pixel structure can be used for making simultaneously driving component, pixel electrode and storage capacitors and the outer outside line of pixel region P in the pixel region P, also can be used for making separately driving component, pixel electrode and storage capacitors in the pixel region P in the dot structure, or only be used for making driving component and pixel electrode in the pixel region P separately.The present invention proposes a kind of dot structure that is suitable for using less photomask operation, but does not limit the formation zone of production method of pixel structure and the zone of finishing of dot structure.In order to be beneficial to explanation, below only explain to make the outer outside line of driving component, pixel electrode and storage capacitors in the pixel region P and pixel region P simultaneously.
[first embodiment]
Fig. 2 A～Fig. 2 I is the production method of pixel structure of first embodiment of the invention.
Please earlier with reference to Fig. 2 A, provide a substrate 210 with a pixel region P earlier.Then, on substrate 210, form the first metal layer 220, gate insulation layer 230 and semiconductor layer 240 in regular turn, wherein the material of semiconductor layer 240 for example is amorphous silicon or polysilicon, and the method for formation the first metal layer 220 for example is sputter (sputtering) or evaporation (evaporation).The material of gate insulation layer 230 for example is that silica or silicon nitride or its are laminated, and the method that forms gate insulation layer 230 for example be chemical vapour deposition technique (chemicalvapor deposition, CVD).Then, shown in Fig. 2 A, via the first half modes or grey mode photomask M1 patterning the first metal layer 220, gate insulation layer 230 and semiconductor layer 240, form first photoresist layer 242 on semiconductor layer 240, wherein first photoresist layer 242 is included in and forms the transistor photoresist pattern 242a and following layer capacitance photoresist pattern 242b with first thickness H1 in the pixel region P, and form the circuit photoresist pattern 242c of lower floor with second thickness H2 outside pixel region P, wherein the first thickness H1 is greater than the second thickness H2.
Afterwards, shown in Fig. 2 B, be that mask carries out etching to the first metal layer 220, gate insulation layer 230 with semiconductor layer 240 with first photoresist layer 242.In the present embodiment, etching work procedure for example is the dry-etching operation, and in other embodiments, etching work procedure also can Wet-type etching.Because the first thickness H1 of transistor photoresist pattern 242a and following layer capacitance photoresist pattern 242b is greater than the second thickness H2 of the circuit photoresist pattern 242c of lower floor, therefore, behind the segment thickness that removes transistor photoresist pattern 242a and following layer capacitance photoresist pattern 242b, the circuit photoresist pattern 242c of lower floor is removed fully.In the present embodiment, the operation that removes photoresist for example is the ashing operation.
Then, shown in Fig. 2 C, proceed an etching work procedure, make that the semiconductor layer 240 in lower floor's line pattern 270 is removed.In other embodiments, remove lower floor's line pattern 270 except removing semiconductor layer 240, still comprise removing gate insulation layer 230, and etching work procedure herein for example is the dry-etching operation.Afterwards, remove remaining first photoresist layer 242a and the 242b again, formation corresponds respectively to lower floor's line pattern 270, the transistor pattern 250 and following layer capacitance pattern 260 of the circuit photoresist pattern 242c of lower floor, transistor photoresist pattern 242a and following layer capacitance photoresist pattern 242b (being illustrated in Fig. 2 B), wherein transistor pattern 250 comprises the first metal layer 220, gate insulation layer 230 and semiconductor layer 240 respectively with following layer capacitance pattern 260, and lower floor's line pattern 270 comprises the first metal layer 220 and gate insulation layer 230 in the present embodiment.
Afterwards, please refer to Fig. 2 D, on substrate 210, form dielectric layer 280 and electrode layer 290 in regular turn, and dielectric layer 280 and electrode layer 290 covering transistor patterns 250, following layer capacitance pattern 260 and lower floor's line pattern 270.The material of above-mentioned dielectric layer 280 for example is that silicon nitride or silica or its are laminated, and the method for its formation for example is physical vaporous deposition or chemical vapour deposition technique.In addition, the method for formation electrode layer 290 for example is to form transparent conductive material layers such as an indium tin oxide layer or an indium-zinc oxide layer by the sputter operation.Continuing it, carry out a little shadow operation, with formation pattern photoresist layer 282, and then carry out an etching work procedure, is mask with pattern photoresist layer 282, etching dielectric layer 280 and electrode layer 290.Shown in Fig. 2 D, behind pattern etched dielectric layer 280 and the electrode layer 290, expose the source electrode 250a/ drain electrode 250b district of part lower floor line pattern 270, the following layer capacitance pattern 260 of part and transistor pattern 250.
Then, shown in Fig. 2 E, after pattern dielectric layer 280 and electrode layer 290, again with pattern photoresist layer 282 as mask, to the part semiconductor floor 240 of layer capacitance pattern 260 and the semiconductor layer 240 in source electrode 250a/ drain electrode 250b district carry out ion doping D down, wherein ion doping D for example is P type ion doping or N type ion doping, and the method for ion doping for example to be ion penetrate clump operation (ionshower) or ion are implanted (ion implantation).Afterwards, again pattern photoresist layer 282 is removed.Afterwards and carry out a high temperature ion activation operation, this step can use boiler tube or the use operation that is rapidly heated to carry out.
Afterwards, shown in Fig. 2 F, after carrying out ion doping D, on electrode layer 290, form second metal level 292, and make second metal level 292 be electrically connected to the source electrode 250a/ drain electrode 250b district of lower floor's line pattern 270, following layer capacitance pattern 260 and transistor pattern 250.Above-mentioned second metal level, 292 materials for example are aluminium (Al), molybdenum (Mo), molybdenum nitride (MoN), titanium (Ti), titanium nitride (TiN), it is laminated, or other electric conducting material, and the method for its formation for example is to utilize proper methods such as sputter or evaporation to deposit.
Then, shown in Fig. 2 G, carry out a little shadow operation via one the second half mode or grey mode photomask M2, on second metal level 292, form second photoresist layer 294, wherein second photoresist layer 294 has the upper layer circuit photoresist pattern 294c of the 3rd thickness H3 outside pixel region P, the source/drain photoresist pattern 294a that has the 3rd thickness H3 in pixel region P and last layer capacitance photoresist pattern 294b and the pixel electrode photoresist pattern 294d with the 4th thickness H4, wherein the 3rd thickness H3 is greater than the 4th thickness H4.In the present embodiment, when second photoresist layer 294 being carried out little shadow operation, comprise more that simultaneously pixel region P outside formation has the connection pad photoresist pattern 294e of the 4th thickness H4 via the second half modes or grey mode photomask M2.
Afterwards, shown in Fig. 2 H, with second photoresist layer 294 is that mask carries out etching to second metal level 292 with electrode layer 290, with outside pixel region P, form a pair of should be in the upper layer circuit pattern 272 of upper layer circuit photoresist pattern 294c, in pixel region P, form corresponding to the source electrode 252a/ drain electrode 252b pattern of source/drain photoresist pattern 294a and corresponding on layer capacitance photoresist pattern 294b on layer capacitance pattern 262.
Then, carry out an ashing operation, because the 3rd thickness H3 of upper layer circuit photoresist pattern 294c, source/drain photoresist pattern 294a and last layer capacitance photoresist pattern 294b is greater than the 4th thickness H4 of pixel electrode photoresist pattern 294d, therefore, when pixel electrode photoresist pattern 294d was removed fully, source electrode 252a/ drain electrode 252b photoresist pattern 294a, last layer capacitance photoresist pattern 294b and upper layer circuit photoresist pattern 294c only were removed the thickness of part.In the present embodiment, ashing operation for example is an oxygen electricity slurry ashing operation.Then, second metal level 292 that is originally covered by pixel electrode photoresist pattern 294d zone is carried out an etching work procedure, to remove second metal level 292 corresponding to pixel electrode photoresist pattern 294d, the electrode layer 290 that exposes part is with as pixel electrode 296, shown in Fig. 2 I.At last, remove remaining second photoresist layer 294.Carry out upper layer circuit photoresist pattern 294c, source/drain photoresist pattern 294a, in layer capacitance photoresist pattern 294b and the pixel electrode photoresist pattern 294d ashing operation, pixel region P more comprises outward and removes connection pad photoresist pattern 294e.Then, remove second metal level 292 corresponding to connection pad photoresist pattern 294e to form a connection pad pattern 298.
Fig. 2 J illustrates to after forming second metal level 292; more comprise and form a protective layer 293 on second metal level 292; and when coming patterning second metal level 292 with electrode layer 290 via the second half modes or grey mode photomask M2; while patterning protective layer 293 is so that protective layer 293 has identical pattern with second metal level 292.In the present embodiment, the material of protective layer 293 for example is silicon nitride, silica or organic material, and the method for its formation for example is with physical vaporous deposition or chemical vapour deposition technique.
In sum, in above-mentioned one pixel structure process method, use the first half modes or grey mode photomask M1 to form lower floor's line pattern 270, transistor pattern 250 and following layer capacitance pattern 260 (illustrating) as Fig. 2 C.Use another photomask patternization and carry out ion doping D, the one source pole 250a/ drain electrode 250b district (illustrating) of exposed portions serve lower floor line pattern 270, following layer capacitance pattern 260 and transistor pattern 250 as Fig. 2 E.Then, use the second half modes or grey mode photomask M2 to finish the making of dot structure 200.Owing to use less photomask number to make dot structure 200, thus compared to prior art five road photomask operations, can reduce cost of manufacture and reduce the tediously long defective that manufacture method caused.
Present embodiment proposes a kind of dot structure 200, be suitable for finishing by the above-mentioned steps made, please refer to Fig. 2 I, dot structure 200 comprises that substrate 210, patterning are laminated 256, pattern dielectric layer 280, patterned electrode layer 290 and patterning second metal level 292.Wherein substrate 210 has a pixel region P.Patterning laminated 256 is arranged on the substrate 210, patterning laminated 256 is included in the transistor pattern 250 and following layer capacitance pattern 260 of pixel region P, and the lower floor's line pattern 270 outside pixel region P, wherein transistor pattern 250 comprises the first metal layer 220, gate insulation layer 230 and semiconductor layer 240 respectively with following layer capacitance pattern 260, and lower floor's line pattern 270 comprises the first metal layer 220 and gate insulation layer 230, in other embodiments, lower floor's line pattern 270 can only be made of the first metal layer 220.280 of pattern dielectric layer are disposed on the substrate 210 and covering transistor pattern 250, layer capacitance pattern 260 and lower floor's line pattern 270 down, and pattern dielectric layer 280 exposes part lower floor line pattern 270, the part source electrode 250a/ drain electrode 250b district of layer capacitance pattern 260 and transistor pattern 250 down.Patterned electrode layer 290 is disposed on the pattern dielectric layer 280, and patterning second metal level 292 that is disposed on the patterned electrode layer 290 comprises layer capacitance pattern 262 on a upper layer circuit pattern 272 and the one source pole 252a/ drain electrode 252b pattern and.Upper layer circuit pattern 272, source electrode 252a/ drain electrode 252b pattern and go up layer capacitance pattern 262 and be electrically connected to lower floor's line pattern 270, source electrode 250a/ drain electrode 250b district and layer capacitance pattern 260 down respectively wherein, and patterning second metal level 292 in the pixel region P exposes patterned electrode layer 290 partly as a pixel electrode 296.In the present embodiment, the electrode layer 290 that outer patterning second metal level 292 of pixel region P more exposes part is as a connection pad 298, and connection pad 298 connects upper layer circuit pattern 272.
In addition, in one embodiment of this invention, dot structure 200 can also comprise that a protective layer 293 is disposed on patterning second metal level 292, and shown in Fig. 2 J, wherein the material of protective layer 293 for example is silica, silicon nitride or organic material.
[second embodiment]
Fig. 3 A～Fig. 3 I is the production method of pixel structure of second embodiment.The manufacture method and first embodiment of the dot structure 300 of present embodiment are similar, in the present embodiment, form the production method of transistor pattern 250, following layer capacitance pattern 260 and lower floor's line pattern 270 and pattern dielectric layer 280 and electrode layer 290, shown in Fig. 3 A～3D, itself and first embodiment Fig. 2 A～2D are similar, do not add at this and give unnecessary details.
In addition, please refer to Fig. 3 E, present embodiment is after pattern dielectric layer 280 and electrode layer 290, form doping semiconductor layer 240 ' on electrode layer 290, and make doping semiconductor layer 240 ' be connected to the source electrode 250a/ drain electrode 250b district of lower floor's line pattern 270, following layer capacitance pattern 260 and transistor pattern 250.Doping semiconductor layer 240 ' described here comprises P type doping semiconductor layer or N type doping semiconductor layer.Then, shown in Fig. 3 F, carry out a little shadow operation via the second half modes or grey mode photomask M2, form and similar second photoresist layer 294 of first embodiment, then, shown in Fig. 3 G, when to be mask to second metal level 292 carry out an etching work procedure with electrode layer 290 with second photoresist layer 294, also the etching doping semiconductor layer 240 ', and the etching work procedure that is carried out can utilize dry-etching operation or Wet-type etching operation here.
Afterwards, similar with first embodiment, carry out an ashing operation, etching work procedure and the glue process at quarter that delusters, utilize second photoresist layer 294 to have different thickness, remove second metal level 292 corresponding to pixel electrode photoresist pattern 294d (being illustrated in 3G), the electrode layer 290 that exposes part is with as pixel electrode 296, shown in Fig. 3 H.In addition, outside pixel region P, form a pair of should be in the upper layer circuit pattern 272 of upper layer circuit photoresist pattern 294c, in pixel region P, form corresponding to the source electrode 252a/ drain electrode 252b of source/drain photoresist pattern 294a (being illustrated in Fig. 3 G) and corresponding to the last layer capacitance pattern 262 of last layer capacitance photoresist pattern 294b (being illustrated in Fig. 3 G).
Fig. 3 I illustrates as Fig. 2 J of first embodiment, for after forming second metal level 292, also comprises forming a protective layer 293 on second metal level 292, does not add at this and gives unnecessary details.
In sum, please refer to Fig. 3 H, present embodiment proposes a kind of dot structure 300, and it is suitable for being finished by the above-mentioned steps made.Dot structure 300 is similar with dot structure 200, and dot structure 300 also comprises a doping semiconductor layer 240 ', it is disposed at patterning second metal level 292 bottoms, so that patterning second metal level 292 contacts with other rete via doping semiconductor layer 240 ', wherein doping semiconductor layer 240 ' for example is P type doping semiconductor layer or N type doping semiconductor layer, and the method for its formation for example is with physical vaporous deposition or chemical vapour deposition technique.In addition, dot structure 300 can comprise that more a protective layer 293 is disposed on patterning second metal level 292, and shown in Fig. 2 J, wherein the material of protective layer 293 for example is silica, silicon nitride or organic material.
In sum, production method of pixel structure proposed by the invention is suitable for utilizing less photomask operation to make, and compared to five road photomask operations of prior art, can significantly reduce production costs and improves productive rate.In addition, a production method of pixel structure of the present invention uses half mode or the grey mode photomask that have had the volume production technology to make, so the present invention has the high advantage of volume production feasibility.In addition, half mode that present technique is used or grey mode photomask also can be replaced by the exposure that two photomasks carry out different-energy respectively, do not limit the kind of photomask at this.Moreover in a dot structure of the present invention, transistor uses the structure of bottom grid, and it can reduce backlight (backlight) to transistorized influence, reduces photoelectric current, and then keeps performance of transistors.In addition, transistorized structure is adopted the design of etch stop layer (Etching Stop Layer), thus can promote the characteristic of driving component, and improve the production qualification rate.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion of being considered as being defined with accompanying claims.
Claims (20)
1. a production method of pixel structure is characterized in that, comprising:
One substrate is provided, and this substrate has a pixel region;
Form a first metal layer, a gate insulation layer and semi-conductor layer in regular turn on this substrate;
This first metal layer of patterning, this gate insulation layer and this semiconductor layer, to form a transistor pattern, layer capacitance pattern once, layer line road pattern once, wherein this transistor pattern and this time layer capacitance pattern comprise this first metal layer, this gate insulation layer and this semiconductor layer respectively, and this lower floor's line pattern comprises this first metal layer;
Form a dielectric layer and an electrode layer in regular turn on this substrate, wherein this dielectric layer and this electrode layer cover this transistor pattern, this time layer capacitance pattern and this lower floor's line pattern;
This dielectric layer of patterning and this electrode layer are to expose the source of this lower floor's line pattern of part, part this time layer capacitance pattern and this transistor pattern;
Form one second metal level on this electrode layer, and make this second metal level be electrically connected to this source/drain regions of this lower floor's line pattern, this time layer capacitance pattern and this transistor pattern; And
This second metal level of patterning and this electrode layer, forming layer capacitance pattern on a upper layer circuit pattern, the source pattern and, and this electrode layer that exposes part of this second metal level in this pixel region is with as a pixel electrode.
2. production method of pixel structure according to claim 1, it is characterized in that, also be included in after this dielectric layer of patterning and this electrode layer, as mask, this semiconductor layer of part of this time layer capacitance pattern and this semiconductor layer of this source/drain regions are carried out ion doping with this dielectric layer of patterning and this electrode layer.
3. production method of pixel structure according to claim 1, it is characterized in that this first metal layer of this patterning, this gate insulation layer and the step of this semiconductor layer are via half mode photomask operation, a grey mode photomask operation or via two photomask operations of different exposure energies.
4. production method of pixel structure according to claim 1, it is characterized in that this second metal level of this patterning and the step of this electrode layer are via half mode photomask operation, a grey mode photomask operation or via two photomask operations of different exposure energies.
5. production method of pixel structure according to claim 1 is characterized in that, also comprises:
After this dielectric layer of patterning and this electrode layer, form a doping semiconductor layer on this electrode layer, and make this doping semiconductor layer be connected to this source/drain regions of this lower floor's line pattern, this time layer capacitance pattern and this transistor pattern; And
When this second metal level of patterning and this electrode layer, while this doping semiconductor layer of patterning is so that this doping semiconductor layer has identical pattern with this second metal level.
6. production method of pixel structure according to claim 1 is characterized in that, also comprises:
After forming this second metal level, form a protective layer on this second metal level; And
When this second metal level of patterning and this electrode layer, while this protective layer of patterning is so that this protective layer has identical pattern with this second metal level.
7. production method of pixel structure according to claim 1, it is characterized in that, when also being included in this second metal level of patterning and this electrode layer, make this outer second metal level of this pixel region expose this electrode layer of part, with as a connection pad, wherein this connection pad connects this upper layer circuit pattern.
8. production method of pixel structure according to claim 1 is characterized in that, the method for this first metal layer of patterning, this gate insulation layer and this semiconductor layer comprises:
Form one first photoresist layer on this semiconductor layer;
Via one the first half mode photomask this first photoresist layer is carried out little shadow operation, have a transistor photoresist pattern of first thickness and layer capacitance photoresist pattern once in this pixel region, to form, and form the road of the layer line once photoresist pattern with second thickness outside this pixel region, wherein this first thickness is greater than this second thickness;
With this first photoresist layer is that mask carries out etching to this first metal layer, this gate insulation layer and this semiconductor layer, forms this lower floor's line pattern, this transistor pattern and this time layer capacitance pattern that correspond respectively to this lower floor's circuit photoresist pattern, this transistor photoresist pattern and this time layer capacitance photoresist pattern;
Remove this semiconductor layer in segment thickness, this lower floor's circuit photoresist pattern and this lower floor's line pattern of segment thickness, this time layer capacitance photoresist pattern of this transistor photoresist pattern; And
Remove remaining this first photoresist layer.
9. production method of pixel structure according to claim 8 is characterized in that, also comprises this gate insulation layer that removes in this lower floor's line pattern.
10. production method of pixel structure according to claim 1 is characterized in that, the method for this second metal level of patterning and this electrode layer comprises:
Form one second photoresist layer on this second metal level;
Via one the second half mode photomask this second photoresist layer is carried out little shadow operation, outside this pixel region, to form a upper layer circuit photoresist pattern with the 3rd thickness, and a pixel electrode photoresist pattern that in this pixel region, forms layer capacitance photoresist pattern on the source photoresist pattern and with the 3rd thickness and have the 4th thickness, wherein the 3rd thickness is greater than the 4th thickness;
With this second photoresist layer is that mask carries out etching to this second metal level and this electrode layer, forms and to correspond respectively to this source/drain photoresist pattern, this source/drain pattern, layer capacitance pattern and this upper layer circuit pattern on this of layer capacitance photoresist pattern and upper layer circuit photoresist pattern on this;
Carry out an ashing operation, with remove this source/drain photoresist pattern, segment thickness and this pixel electrode photoresist pattern of layer capacitance photoresist pattern and this upper layer circuit photoresist pattern on this;
Remove this electrode layer that this second metal level corresponding to this pixel electrode photoresist pattern exposes part with as this pixel electrode; And
Remove remaining this second photoresist layer.
11. production method of pixel structure according to claim 10 is characterized in that, also comprises:
When via this second half mode photomask this second photoresist layer being carried out little shadow operation, formation has a connection pad photoresist pattern of the 4th thickness this pixel region outside simultaneously;
Carry out an ashing operation, to remove connection pad photoresist pattern; And
Remove this second metal level corresponding to this connection pad photoresist pattern to form a connection pad pattern.
12. production method of pixel structure according to claim 1 is characterized in that, the material of this semiconductor layer comprises amorphous silicon or polysilicon.
13. production method of pixel structure according to claim 1 is characterized in that, the material of this electrode layer comprises transparent conductive material.
14. a dot structure is characterized in that, comprising:
One substrate has a pixel region;
One patterning is laminated, be arranged on this substrate, comprise a transistor pattern, once layer capacitance pattern and layer line road pattern once, wherein this transistor pattern and this time layer capacitance pattern comprise a first metal layer, a gate insulation layer and semi-conductor layer respectively, and this lower floor's line pattern comprises this first metal layer;
One pattern dielectric layer, be disposed on this substrate and cover this transistor pattern, this time layer capacitance pattern and this lower floor's line pattern, and this pattern dielectric layer exposes the source of this lower floor's line pattern of part, part this time layer capacitance pattern and this transistor pattern;
One patterned electrode layer is disposed on this pattern dielectric layer; And
One patterning, second metal level, be disposed on this patterned electrode layer, comprise layer capacitance pattern on a upper layer circuit pattern, the source pattern and, wherein this upper layer circuit pattern, this source/drain pattern and this last layer capacitance pattern are electrically connected to this lower floor's line pattern, this source/drain regions and this time layer capacitance pattern respectively, and this patterning second metal level in this pixel region exposes this patterned electrode layer of part as a pixel electrode.
15. dot structure according to claim 14 is characterized in that, this time of part layer capacitance pattern that this pattern dielectric layer exposed and this semiconductor layer of this source/drain regions are doping semiconductor layer.
16. dot structure according to claim 14, it is characterized in that, also comprise a doping semiconductor layer, it is disposed at this patterning second metal level bottom, so that this patterning second metal level contacts with this lower floor's line pattern, this source/drain regions and this time layer capacitance pattern via this doping semiconductor layer.
17. dot structure according to claim 14 is characterized in that, also comprises a protective layer, it is disposed on this patterning second metal level.
18. dot structure according to claim 14 is characterized in that, this electrode layer that this outer patterning second metal level of this pixel region more exposes part is as a connection pad, and this connection pad connects this upper layer circuit pattern.
19. dot structure according to claim 14 is characterized in that, the material of this semiconductor layer comprises amorphous silicon or polysilicon.
20. dot structure according to claim 14 is characterized in that, the material of this electrode layer comprises transparent conductive material.
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| US8357617B2 (en) * | 2008-08-22 | 2013-01-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of patterning a metal gate of semiconductor device |
| CN102023431B (en) * | 2009-09-18 | 2013-06-12 | 北京京东方光电科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
| TWI489191B (en) * | 2012-09-20 | 2015-06-21 | Au Optronics Corp | Pixel structure and thin film transistor |
| TWI482287B (en) * | 2013-04-24 | 2015-04-21 | Au Optronics Corp | Electroluminescent display panel and method of fabricating the same |
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