CN100490143C - Non-gate-controlled diode, electrostatic discharge protection circuit and manufacture method thereof - Google Patents
Non-gate-controlled diode, electrostatic discharge protection circuit and manufacture method thereof Download PDFInfo
- Publication number
- CN100490143C CN100490143C CNB021412871A CN02141287A CN100490143C CN 100490143 C CN100490143 C CN 100490143C CN B021412871 A CNB021412871 A CN B021412871A CN 02141287 A CN02141287 A CN 02141287A CN 100490143 C CN100490143 C CN 100490143C
- Authority
- CN
- China
- Prior art keywords
- diode
- gate
- esd
- supply line
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A non-gate-controlled diode structure of insulator-base epitaxial silicon is composed of an insulator-base epitaxial silicon substrate consiting of substrate, insulating layer and silicon layer, a pair of isolating structures in said silicon layer to form a trap region between isolating structures in silicon layer, the type-1 ion injection region and the type-2 ion injection region. It can be used in electrostatic protection circuit. Its preparing process is also disclosed.
Description
Technical field
The present invention relevant for a kind of non-gate diode element, manufacture method and application its electrostatic storage deflection (ESD) protection circuit and particularly about a kind of insulator-base epitaxial silicon (silicon on insulator, SOI) non-gate diode element, the manufacture method of manufacturing process technology and electrostatic storage deflection (ESD) protection circuit of using it utilized.
Background technology
Insulator-base epitaxial silicon (SOI) manufacturing process technology is the main competition technology of potentialization on present low-voltage and high-speed applications, because compared to general extensive (bulk) CMOS manufacturing process, the SOI manufacturing process technology has highly isolates (isolation) degree, avoids breech lock (latch-up) effect and lower junction capacitance or the like.At present, for the SOI manufacturing process, (electrostaticdischarge ESD) is a technology that the utmost point need develop to electrostatic discharge protective.
The protection class that the ESD protection circuit can provide depends on when the ESD circuit arrives small voltage with voltage clamping, the magnitude of current that the ESD circuit can be taken away.During esd pulse enters, thermic (thermal runaway) out of control splits destruction with continuous play and can do great damage to internal circuit element.In the SOI element, the heat biography rate (thermal conductivity) of the flush type oxide layer of SOI (buried oxide) only is about one of percentage of silicon; This causes element easier to be overheated because of ESD, and makes thermic acceleration out of control increase.
Fig. 1 represents the profile of SOI gate diode (gated diode), and it is for there being the esd protection circuit of CMOS on a kind of SOI.This structure is published in periodical " Proc.ofEOS/ESD Symp. ", 1996, pp.291-301 by people such as S.Voldman.As shown in Figure 1, SOI gate diode is formed on the SOI substrate, and it comprises substrate 10, flush type oxide layer 12 and silicon layer.In silicon layer, form shallow trench isolation from (shallow trench isolation, STI) structure 14.Between the STI isolation structure, have a p type diffusion region (diffusion region) (P+) 20 with N type diffusion region (N+) 16.In the middle of p type diffusion region 20 and the N type diffusion region 16 then is N type trap or P type well area 18.If this well area 18 is for injecting N type ion (N-), then p type diffusion region (P+) 20 forms the SOI diode with N trap (N-) 18; Otherwise if this well region 18 is for injecting P type ion (P-), then N type diffusion region 20 (N+) forms the SOI diode with P trap (P-) 18.Also have a grid structure on well region 18, it comprises P+ district 24 and N+ district 22 (both are as grid), spaced walls 26 and grid oxic horizon 28 etc.
P type diffusion region (P+) 20 is connected respectively to voltage V1, V2 with N type diffusion region (N+) 16, and two voltages as the SOI diode apply end points separately.Forming the SOI diodes with p type diffusion region (P+) 20 with N trap (N-) 18 is example, if voltage V1 with respect to voltage V2 for just, then this SOI diode is forward to setover; Otherwise, if voltage V2 with respect to voltage V1 for just, then this SOI diode is reverse biasing.
If ESD voltage is very little in the heat that knot produced of 18 of p type diffusion region (P+) 20/N type traps (N-), the SOI diode can bear higher ESD voltage.Heat is created in the regional area of PN junction.Most of heat on PN junction is Joule heat.Second breakdown occurs in its intrinsic temperature (intrinsic temperature) T of maximum temperature arrival in the SOI diode
IntrinsticThe time.Therefore, in order to obtain preferable ESD degree of protection, just must reduce power density and not have joule's heat energy.
Summary of the invention
Therefore the objective of the invention is to propose its electrostatic storage deflection (ESD) protection circuit of a kind of non-gate diode element, manufacture method and application, this non-gate diode has low power density.
Another object of the present invention is to propose its electrostatic storage deflection (ESD) protection circuit of a kind of non-gate diode element, manufacture method and application, and this non-gate diode can be applied to the electrostatic discharge protection circuit of SOI circuit, and can improve its ESD pressure withstanding degree.
Another object of the present invention is to propose its electrostatic storage deflection (ESD) protection circuit of a kind of non-gate diode element, manufacture method and application, and this non-gate diode can be suitable for SOI manufacturing process or extensive CMOS manufacturing process.
For reaching above-mentioned and other purposes, the present invention proposes a kind of non-gate diode element structure, uses the electrostatic storage deflection (ESD) protection circuit and the non-gate diode element manufacture method of this non-gate diode element, and it is summarized as follows:
The invention provides a kind of non-gate diode structure of insulator-base epitaxial silicon, comprising: an insulator-base epitaxial silicon substrate, it has substrate, insulating barrier and silicon layer and piles up in regular turn; To isolation structure, be arranged in silicon layer, make between to isolation structure with in the silicon layer to have a well region; The first type ion implanted region and one second type ion implanted region are arranged in well region and are close to each isolation structure respectively.
The present invention also proposes the non-gate diode structure of another kind of insulator-base epitaxial silicon, comprising: insulator-base epitaxial silicon substrate, and it has substrate, insulating barrier and silicon layer and piles up in regular turn; To isolation structure, be arranged in silicon layer, make between to isolation structure with in the silicon layer to have first well region and second well region, wherein first well region is adjacent with second well region; The first type ion implanted region and the second type ion implanted region lay respectively in first and second well region, and are close to each isolation structure respectively, make the face that connects of becoming first and second well region of the non-gate diode element of insulator-base epitaxial silicon with this.
The present invention also provides a kind of electrostatic storage deflection (ESD) protection circuit of non-gate diode element, and it is coupled between input welding block and the internal circuit.This protection circuit comprises following element.High Voltage Power Supply line and low voltage power supply line all are coupled to this internal circuit; First diode, its anode are coupled to the High Voltage Power Supply line and its negative electrode is coupled to a node; Second diode, its negative electrode are coupled to the low voltage power supply line and its anode is coupled to node; The first diode string is made of the series connection of a plurality of diodes, and wherein its anode is coupled to the High Voltage Power Supply line and its negative electrode is coupled to node; The second diode string, constitute by a plurality of diode series connection, its negative electrode is coupled to the low voltage power supply line and its anode is coupled to node, wherein in each diode in this first diode string, each diode in this second diode string, this first diode, this second diode one of them is non-gate diode at least.
When the positive voltage with respect to the High Voltage Power Supply line put on the input welding block, the electrostatic storage deflection (ESD) protection circuit of non-gate diode element provided one via the discharge path of first diode to the High Voltage Power Supply line.When the negative voltage with respect to the low voltage power supply line put on the input welding block, the electrostatic storage deflection (ESD) protection circuit of non-gate diode element provided one via the discharge path of second diode to the low voltage power supply line.When the negative voltage with respect to the High Voltage Power Supply line put on the input welding block, the electrostatic storage deflection (ESD) protection circuit of non-gate diode element provided one via second diode, the second diode string and the first diode string discharge path to the High Voltage Power Supply line.When the positive voltage with respect to this low voltage power supply line put on the input welding block, the electrostatic storage deflection (ESD) protection circuit of non-gate diode element provided one via first diode, the first diode string and the second diode string discharge path to the low voltage power supply line.
The present invention also provides a kind of electrostatic storage deflection (ESD) protection circuit of non-gate diode element, and it is coupled between output welding block and the pre-driver.This protection circuit comprises following element.A High Voltage Power Supply line and a low voltage power supply line are couple to pre-driver respectively; First diode, its anode are coupled to this High Voltage Power Supply line and its negative electrode is coupled to a node; Second diode, its negative electrode are coupled to the low voltage power supply line and its anode is coupled to node; The first diode string is made of a plurality of diode series connection, and its anode is coupled to the High Voltage Power Supply line and its negative electrode is coupled to node; The second diode string is made of a plurality of diode series connection, and its negative electrode is coupled to the low voltage power supply line and its anode is coupled to node; The first type MOS transistor, its source electrode is couple to the High Voltage Power Supply line, and its drain electrode is couple to node, and its grid is couple to pre-driver; And the second type MOS transistor, its source electrode is coupled to the low voltage power supply line, its drain electrode is couple to node, its grid is couple to first this grid of type MOS transistor, wherein in each diode in this first diode string, each diode in this second diode string, this first diode, this second diode one of them is non-gate diode at least.
Wherein when the positive voltage with respect to the High Voltage Power Supply line put on the output welding block, the electrostatic storage deflection (ESD) protection circuit of non-gate diode element provided one via the discharge path of first diode to the High Voltage Power Supply line.When the negative voltage with respect to the low voltage power supply line put on the output welding block, the electrostatic storage deflection (ESD) protection circuit of non-gate diode element provided one via the discharge path of second diode to the low voltage power supply line.When the negative voltage with respect to the High Voltage Power Supply line put on the input welding block, the electrostatic storage deflection (ESD) protection circuit of non-gate diode element provided one via second diode, the second diode string and the first diode string discharge path to the High Voltage Power Supply line.When the positive voltage with respect to the low voltage power supply line put on the output welding block, the electrostatic storage deflection (ESD) protection circuit of non-gate diode element provided one via first diode, the first diode string and the second diode string discharge path to the low voltage power supply line.
The present invention also proposes a kind of electrostatic storage deflection (ESD) protection circuit of non-gate diode element, and it is coupled between input welding block and the internal circuit.This protection circuit comprises with lower member.High Voltage Power Supply line and low voltage power supply line all are coupled to internal circuit; First diode is connected with one second diode, and wherein the anode of first diode is coupled to a node, and the negative electrode of second diode is coupled to the High Voltage Power Supply line; The 3rd diode is connected with the 4th diode, and wherein the anode of the 3rd diode is coupled to the low voltage power supply line, and the negative electrode of the 4th diode is coupled to node; First end that resistance has is coupled to node and second end is coupled to internal circuit; The grid of MOS transistor is coupled to the low voltage power supply line with source electrode, and drain electrode is coupled to second end of resistance; And ESD (Electrostatic Discharge) clamp circuit, be coupled between High Voltage Power Supply line and the low voltage power supply line, wherein above-mentioned ESD (Electrostatic Discharge) clamp circuit is in series by a plurality of diodes, its anode is couple to the High Voltage Power Supply line and its negative electrode is couple to the low voltage power supply line, wherein in each diode in this first diode string, each diode in this second diode string, this first diode, this second diode one of them is non-gate diode at least.
The present invention also proposes a kind of method that forms the non-gate diode of insulator-base epitaxial silicon.At first, provide an insulator-base epitaxial silicon substrate, it piles up substrate, insulating barrier and silicon layer in regular turn; Form a pair of isolation structure in silicon layer, make between to isolation structure with in the silicon layer to have a well region.Form the first type ion implanted region and the second type ion implanted region in well region, and be close to each isolation structure respectively.
The present invention also proposes a kind of method that forms the non-gate diode of insulator-base epitaxial silicon.At first, provide an insulator-base epitaxial silicon substrate, it piles up substrate, insulating barrier and silicon layer in regular turn and piles up in regular turn.Form a pair of isolation structure in this silicon layer.Form first well region and second well region between to isolation structure with silicon layer in, wherein first well region is adjacent with second well region.Form the first type ion implanted region and the second type ion implanted region, lay respectively at first with this second well region in, and be close to each isolation structure respectively, make the knot of becoming first and second well region of the non-gate diode element of insulator-base epitaxial silicon with this.
The present invention also provides a kind of extensive COMS non-gate diode structure, comprising: the substrate with a trap; A pair of isolation structure is arranged in this substrate and is arranged in this trap; The first type ion implanted region is arranged in above-mentioned trap; The a pair of second type ion implanted region is arranged in trap and is close to respectively this isolation structure respectively, wherein should separate with this first type ion implanted region with this trap respectively the second type ion implanted region.
The present invention also provides a kind of method that forms the non-gate diode of extensive COMS, comprising: a substrate is provided, forms a trap in this substrate; Form a pair of isolation structure in this substrate, described isolation structure is arranged in this trap; Form in one first type ion implanted region and this trap, and between this is to isolation structure; Form a pair of second type ion implanted region in this well region, and be close to respectively this isolation structure respectively, respectively this second type ion implanted region separates with this first type ion implanted region with this trap respectively.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, hereinafter enumerate preferred embodiment, and conjunction with figs., it is as follows to be elaborated:
Description of drawings
Fig. 1 represents the profile of the gate diode (gated diode) of SOI, and it is for there being the esd protection circuit of CMOS on a kind of SOI;
Fig. 2 is according to the described generalized section that has with the non-gate diode (non-gated diode) of STI barrier structure (STI-blockingstructure) of one embodiment of the invention;
Fig. 3 A and Fig. 3 B express the top view of STI isolation structure and STI barrier structure respectively;
Fig. 4 A to Fig. 4 G represents to produce the isolation structure with STI with the SOI manufacturing process;
Fig. 5 A to Fig. 5 G represents to produce the isolation structure with STI with the SOI manufacturing process;
Fig. 6 A to Fig. 6 G represents to produce the isolation structure with STI with extensive CMOS manufacturing process;
Fig. 7 A to Fig. 7 G represents to produce the isolation structure with STI with extensive CMOS manufacturing process;
Fig. 8 represents that the girth of gate NAND gate control SOI diode and the comparison figure between the ESD voltage are arranged;
Fig. 9 is according to the described generalized section that has with the non-gate diode of STI barrier structure of another embodiment of the present invention;
Figure 10 is that the application of non-gate diode element of the present invention on the input electrostatic storage deflection (ESD) protection circuit used in expression;
Figure 11 is that the application of non-gate diode element of the present invention on the output electrostatic storage deflection (ESD) protection circuit used in expression;
Figure 12 is that the another kind application of non-gate diode element of the present invention on the input electrostatic storage deflection (ESD) protection circuit used in expression; And
Figure 13 is that expression utilizes non-gate diode element of the present invention to realize the ESD clamped circuit of Figure 12.
Label declaration
10 substrates, 12 insulating barriers
14 sti structures, 16 N+ diffusion regions
18 N-(or P-) trap, 20 P+ diffusion regions
24 P+ districts (grid), 22 N+ districts (grid)
26 clearance walls
40 substrates, 42 insulating barriers
44 sti structures, 46 N+ diffusion regions
48 N-(or P-) trap, 50 P+ diffusion regions
60,70 sti structures, 62,72 insulating barriers
64,66,68 ion implanted regions
74,76,78 ion implanted regions
100a/b substrate 102a/b insulating barrier
104a/b silicon layer 106a/b silicon nitride layer
108a/b photoresist 110a/b sti structure
112a/b photoresist 114a/b well region
116a/b photoresist 118a/b ion implanted region
120 well regions
200a/b substrate 202a/b well region
204a/b silicon nitride layer 206a/b photoresist
208a/b sti structure 210a/b photoresist
212a/b ion implanted region 214a/b photoresist
216a/b ion implanted region 218 well regions
300 input welding blocks, 302 first diode strings
304 second diode strings, 306 internal circuits
310 output welding blocks, 312 first diodes
314 second diode strings, 316 predrive circuits
320 input welding blocks, 322 internal circuits
324 ESD clamped circuits
330 input welding blocks, 332 internal circuits
334 diode strings
Embodiment
Fig. 2 is the generalized section according to the non-gate diode (non-gated diode) of the barrier structure of the described STI of having of one embodiment of the invention (STI-blockingstructure).As shown in Figure 2, SOI gate diode is formed on the SOI substrate, and it comprises substrate 40, insulating barrier 42 and silicon layer.Substrate 40 can be P-type or N-type substrate, and insulating barrier 42 then can be as the flush type oxide layer.SOI diode with STI barrier structure then is formed among the silicon layer.In silicon layer, the SOI diode is formed between two sti structures 44, that is the ion implanted region of formation SOI diode is all isolated by two sti structures.On the insulating barrier 42 and then form the well region 50 of lighter P type of concentration or N type ion (P-trap or N-trap) between two sti structures.In addition, form higher p type diffusion region of concentration (P+) 48 and N type diffusion region (N+) 46 respectively in the corner of P-or N-trap 50 and in abutting connection with two 44 of sti structures.
To illustrate that then forming sti structure in the SOI manufacturing process has two kinds: STI isolation structure (STI-isolating structure) and the barrier structure (STI-blocking structure) that does not have STI.Fig. 3 A and Fig. 3 B express the top view of these two kinds of structures respectively.The following description will point out that STI isolation structure (STI-isolating structure) can't form the SOI diode, because each ion implanted region is all kept apart by sti structure.As shown in Figure 3A, form several sti structures 60 in the silicon layer on insulating barrier (flush type oxide layer) 62, ion implanted region 64 (N+), 66 (P+) and 68 (N+) then are formed at individually between the sti structure 60, do not connect each other in twos, therefore can't form the P-N knot of diode.Secondly, shown in Fig. 3 B, form two sti structures 70 in the silicon layer on insulating barrier (flush type oxide layer) 72, ion implanted region 74 (N+), 76 (P+) and 78 (N+) then all are formed between two sti structures 70, therefore can form the P-N knot of diode.
Fig. 4 A to Fig. 4 G represents to produce the isolation structure with STI with the SOI manufacturing process, and Fig. 5 A to Fig. 5 G represents to produce the isolation structure with STI with the SOI manufacturing process.The ion implanted region that is had as can be seen by the result in the manufacturing process of isolation structure of STI does not connect in twos each other, therefore can't form the P-N knot of diode.
Please refer to Fig. 4 A and Fig. 5 A, a substrate 100a, 100b at first are provided.Then, on substrate 100a, 100b, form insulating barrier 102a, 102b respectively.Afterwards, on insulating barrier 102a, 102b, form a silicon layer.Insulating barrier 102a, 102b can be the flush type oxide layers.In addition, inject P type ion, to form P type well region 104a, 104b at silicon layer.So far, the step of two kinds of manufacturing process is still identical.
Then, with reference to figure 4B and Fig. 4 C, continue to form a welding block oxide layer (pad oxide) 106b and photoresist 108b, and expose the zone that will form sti structure.Then, be mask with welding block oxide layer 106b and photoresist 108b, P type trap (silicon layer) 106 is etched groove after, remove welding block oxide layer 106b and photoresist 108b again.Afterwards, insert groove with insulating material again, and carry out planarization to form sti structure.With reference to figure 4D, then form photoresist 112b on part P type trap 104b and part sti structure 110b, and expose wherein one by P type well region 104b that sti structure crossed.Then, carry out the ion implantation step, P type ion is injected the P type well region 104b that comes out, to form P+ type zone 114b.At last, shown in Fig. 4 E, 112b removes with photoresist.Then, shown in Fig. 4 F, form photoresist 116b in P+ zone 114b, and carry out the ion implantation step.N type ion is flow in the P type well region that exposes, to form N+ zone 118b.At last, remove photoresist 116b, shown in Fig. 4 G.
Then, with reference to figure 5B and Fig. 5 C, continue to form a welding block oxide layer 106a and photoresist 108a, and expose the zone that will form sti structure.Then, be mask with welding block oxide layer 106b and photoresist 108a, P type trap (silicon layer) 104a is etched groove after, remove welding block oxide layer 106a and photoresist 108a again.Afterwards, insert groove with insulating material again, and carry out planarization to form sti structure.With reference to figure 5D, then form photoresist 112a on part P type trap 104a and part sti structure 110a, and expose part P type well region 104a.Then, carry out the ion implantation step, P type ion is injected the P type well region 104a that comes out, to form P+ type zone 114a.At last, shown in Fig. 5 E, 112a removes with photoresist.Then, shown in Fig. 5 F, form photoresist 116a in P+ zone 114a, and carry out the ion implantation step.The P+ zone 114a that covers under the width of photoresist 116a is slightly larger than.Then, N type ion is flow among the P type well region 104a that exposes, to form N+ zone 118a.At last, remove photoresist 116a, shown in Fig. 5 G.Because the P+ that covers under the width of photoresist 116a is slightly larger than zone 114a so can have P-well region 120 between N+ zone 118a and P+ zone 114a, has width S P.
As mentioned above, comparison diagram 4G and Fig. 5 G can learn to have only the manufacturing process of the barrier structure (STI-blocking structure) with STI can form the SOI diode.
The major parameter of diode of non-gate STI barrier structure that influence is applied to the SOI CMOS manufacturing process of ESD protection circuit be the negative electrode node of diode size, well region ion implantation concentration and diode and the internodal interval of anode (spacing, SP).Wherein the parameter of SP not only influences under diode is forward setovered at interval, the conducting resistance of esd discharge (on-resistance), and it also influences the reverse breakdown voltage of diode.Therefore, by control interval SP value suitably, can produce any suitable reverse breakdown voltage value in esd protection circuit.
Fig. 6 A to Fig. 6 G is a diode element of representing to produce with extensive CMOS manufacturing process the isolation structure with STI, and Fig. 7 A to Fig. 7 G represents to produce the diode element with STI isolation structure with extensive CMOS manufacturing process.
Please refer to Fig. 6 A and Fig. 7 A, a substrate 200a, 200b at first are provided.Then, on substrate 200a, 200b, form P type well region 202a, 202b respectively.So far, the step of two kinds of manufacturing process is still identical.
Then, with reference to figure 6B and Fig. 6 C, continue to form a welding block oxide layer (pad oxide) 204b and photoresist 206b, and expose the zone that will form sti structure.Then, be mask with welding block oxide layer 204b and photoresist 206b, P type trap 202b is etched groove after, remove welding block oxide layer 204b and photoresist 206b again.Afterwards, insert groove with insulating material again, and carry out planarization to form sti structure.With reference to figure 6D, then form photoresist 210b on part P type trap 202b and part sti structure 208b, and expose wherein one by P type well region 202b that sti structure crossed.Then, carry out the ion implantation step, P type ion is injected the P type well region 202b that comes out, to form P+ type diffusion zone 212b.At last, shown in Fig. 6 E, 210b removes with photoresist.Then, shown in Fig. 6 F, form photoresist 214b in P+ diffusion zone 212b, and carry out the ion implantation step.N type ion is flow among the P type well region 202b that exposes, to form N+ diffusion zone 216b.At last, remove photoresist 214b, shown in Fig. 6 G.
Then, with reference to figure 7B and Fig. 7 C, continue to form a welding block oxide layer 204a and photoresist 206a, and expose the zone that will form sti structure.Then, be mask with welding block oxide layer 204b and photoresist 206a, P type trap 202a is etched groove after, remove welding block oxide layer 204a and photoresist 206a again.Afterwards, insert groove with insulating material again, and carry out planarization to form sti structure 208a.With reference to figure 7D, then form photoresist 210a on part P type trap 202a and part sti structure 208a, and expose part P type well region 202a.Then, carry out the ion implantation step, P type ion is injected the P type well region 202a that comes out, to form P+ type zone 212a.At last, shown in Fig. 7 E, 210a removes with photoresist.Then, shown in Fig. 7 F, form photoresist 214a in P+ zone 212a, and carry out the ion implantation step.The P+ zone 212a that covers under the width of photoresist 214a is slightly larger than.Then, N type ion is flow among the P type well region 202a that exposes, to form N+ zone 216a.At last, remove photoresist 212a, shown in Fig. 7 G.Because the P+ that covers under the width of photoresist 214a is slightly larger than zone 212a so can have P-well region 218 between N+ zone 216a and P+ zone 212a, has width S P.
As mentioned above, comparison diagram 6G and Fig. 7 G can learn to have only the manufacturing process of the barrier structure (STI-blocking structure) with STI can form adjacent diode structure.
The major parameter of diode of non-gate STI barrier structure that influence is applied to the extensive CMOS manufacturing process of ESD protection circuit be the negative electrode node of diode size, well region ion implantation concentration and diode and the internodal interval of anode (spacing, SP).Wherein the parameter of SP not only influences under diode is forward setovered at interval, the conducting resistance of esd discharge (on-resistance), and it also influences the reverse breakdown voltage of diode.Therefore, by control interval SP value suitably, can produce any suitable reverse breakdown voltage value in esd protection circuit.
Fig. 8 represents that the girth of gate NAND gate control SOI diode and the comparison figure between the ESD voltage are arranged.Some conclusion as seen from the figure.First: the girth of diode is long more, and the esd discharge voltage that element can bear is big more, also can protect internal circuit more.Second: clearly, the ESD voltage that non-gate SOI diode can bear is greater than gate SOI diode (SOI lubistor diode) is arranged.Because the pass between ESD pressure withstanding degree (ESD robustness) and diode girth is a linear relationship.Therefore, can utilize the non-gate diode of SOI of the present invention to estimate and design the ESD grade of ESD protection circuit easily.
Fig. 9 is the generalized section according to the non-gate diode of the described isolation structure that does not have a STI of another embodiment of the present invention.As shown in Figure 9, SOI gate diode is formed on the SOI substrate, and it comprises substrate 90, insulating barrier 92 and silicon layer.Substrate 90 can be P-type or N-type substrate, and insulating barrier 92 then can be as the flush type oxide layer.The SOI diode that does not have the STI isolation structure then is formed among the silicon layer.In silicon layer, the SOI diode is formed between two sti structures 94, that is the ion implanted region of formation SOI diode is all isolated by two sti structures.Then forming the lighter P type of two adjacent concentration and the well region of N type ion (P-trap or N-trap) on the insulating barrier 92 and between two sti structures.In addition, form the higher p type diffusion region of concentration (P+) 96b and N type diffusion region (N+) 96a at the P-and N-well region 98b, the 98a outside respectively with 94 of sti structures.The difference of the embodiment of this embodiment and Fig. 2 is that the PN junction of the non-gate diode of SOI shown in Figure 9 is the centre of total, and PN junction shown in Figure 2 then is positioned at a side.
Then the ESD protection circuit of using the non-gate diode of SOI of the present invention is described with several examples.
Figure 10 is the ESD protection circuit that the non-gate diode of SOI of Fig. 2 of the present invention or Fig. 9 is used in expression.As shown in figure 10, ESD protects this circuit and comprises an input welding block (input pad) 300, the first diode D1 and the second diode D2, the first diode string 302, the second diode string 304, input resistance R, and High Voltage Power Supply line (Vdd voltage supply rail) Vdd and low voltage power supply line (Vssvoltage supply rail) Vss.Internal circuit 306 is connected between High Voltage Power Supply line Vdd and low voltage power supply line Vss and the input resistance R.The negative electrode of the first diode D1 is connected to Vdd, and anode is connected to welding block 300; The anode of the second diode D2 is connected to Vss, and negative electrode is connected to welding block 300.The first diode string 302 is by a plurality of diode Du1, Du2 ..., Dun is one another in series in the anode-cathode mode, and wherein the anode of diode Du1 is connected to Vdd, and the negative electrode of diode Dun is connected to welding block 300.The second diode string 304 is by a plurality of diode Dd1, Dd2 ..., Ddn is one another in series in anode negative electrode mode, and wherein the anode of diode Dd1 is connected to welding block 300, and the negative electrode of diode Ddn is connected to Vss.Each diode in the first above-mentioned diode D1, the second diode D2, first and second diode string 302/304 all can be earlier figures 2 or the non-gate diode of SOI shown in Figure 9.In addition, input resistance R also can be connected on the input buffer (not shown) in the internal circuit 306.
The working method of the ESD protection circuit of Figure 10 then is described.When the esd event that with respect to High Voltage Power Supply line Vdd is positive voltage was input to input welding block 300, the first diode D1 was forward biasing; And because low voltage power supply line Vss is for floating, so not effect of the second diode D2.Therefore, this esd event (voltage) can discharge into High Voltage Power Supply line Vdd via the first diode D1.In like manner, when the esd event that with respect to low voltage power supply line Vss is negative voltage was input to input welding block 300, the second diode D2 was forward biasing; And because High Voltage Power Supply line Vdd is for floating, so not effect of the first diode D1.Therefore, this esd event (voltage) can discharge into low voltage power supply line Vss via the second diode D2.
When the esd event that with respect to High Voltage Power Supply line Vdd is negative voltage was input to input welding block 300, the first diode D1 was reverse biasing.Because low voltage power supply line Vss is for floating, so the voltage on Vss can be caught up with the negative voltage that puts on input welding block 300.Because the forward conducting voltage of the second diode D2 and conducting resistance forward have slight voltage difference at Vss with input welding block 300 and exist.At this moment, the first diode string 302 (Du1, Du2 ..., Dun) be forward biasing, thus the esd discharge electric current can via the first diode string 302 (Du1, Du2 ..., Dun) discharge into Vdd.
When the esd event that with respect to low voltage power supply line Vss is positive voltage was input to input welding block 300, the second diode D2 was reverse biasing.Because High Voltage Power Supply line Vdd is for floating, so the voltage on Vdd can be caught up with the positive voltage that puts on input welding block 300.Because the forward conducting voltage of the first diode D1 and conducting resistance forward have slight voltage difference at Vdd with input welding block 300 and exist.At this moment because the second diode string 304 (Dd1, Dd2 ..., Ddn) be forward biasing, thus the esd discharge electric current can via the second diode string 304 (Dd1, Dd2 ..., Ddn) discharge into Vss.
Figure 11 represents to use the ESD protection circuit of the non-gate diode of SOI of Fig. 2 of the present invention or Fig. 9.As shown in figure 11, the ESD protection circuit comprises an output welding block (output pad) 310, the first diode D1 and the second diode D2, the first diode string 312, the second diode string 314, PMOS transistor Mp, nmos pass transistor Mn, and High Voltage Power Supply line (Vdd voltage supply rail) Vdd and low voltage power supply line (Vss voltage supply rail) Vss.Predrive circuit 316 is connected between the grid of High Voltage Power Supply line Vdd and low voltage power supply line Vss and PMOS transistor Mp and nmos pass transistor Mn.The negative electrode of the first diode D1 is connected to Vdd, and anode is connected to welding block 310; The anode of the second diode D2 is connected to Vss, and negative electrode is connected to welding block 310.The first diode string 312 is by a plurality of diode Du1, Du2 ..., Dun is one another in series in anode negative electrode mode, and wherein the anode of diode Du1 is connected to Vdd, and the negative electrode of diode Dun is connected to welding block 310.The second diode string 314 is by a plurality of diode Dd1, Dd2 ..., Ddn is one another in series in anode negative electrode mode, and wherein the anode of diode Dd1 is connected to welding block 310, and the negative electrode of diode Ddn is connected to welding block Vss.The source electrode of PMOS transistor Mp is connected to Vdd, and the source electrode of nmos pass transistor Mn is connected to Vss.The drain electrode of PMOS transistor Mp and the drain electrode of nmos pass transistor Mn link together to welding block 310.Each diode in the first above-mentioned diode D1, the second diode D2, first and second diode string 302/304 all can be earlier figures 2 or the non-gate diode of SOI shown in Figure 9.
The working method of the ESD protection circuit of Figure 11 then is described.When the esd event that with respect to High Voltage Power Supply line Vdd is positive voltage was input to output welding block 310, the first diode D1 was forward biasing; And because low voltage power supply line Vss is for floating, so not effect of the second diode D2.Therefore, this esd event (voltage) can discharge into High Voltage Power Supply line Vdd via the first diode D1.In like manner, when the esd event that with respect to low voltage power supply line Vss is negative voltage was input to input welding block 310, the second diode D2 was forward biasing; And because High Voltage Power Supply line Vdd is for floating, so not effect of the first diode D1.Therefore, this esd event (voltage) can discharge into low voltage power supply line Vss via the second diode D2.
When the esd event that with respect to High Voltage Power Supply line Vdd is negative voltage was input to output welding block 310, the first diode D1 was reverse biasing.Because low voltage power supply line Vss is for floating, so the voltage on Vss can be caught up with the negative voltage that puts on output welding block 310.At this moment because the first diode string 312 (Du1, Du2 ..., Dun) be forward biasing, thus the esd discharge electric current can via the first diode string 312 (Du1, Du2 ..., Dun) discharge into Vdd.
When the esd event that with respect to low voltage power supply line Vss is positive voltage was input to output welding block 310, the second diode D2 was reverse biasing.Because low voltage power supply line Vdd is for floating, so the voltage on Vdd can be caught up with the positive voltage that puts on output welding block 310.At this moment because the second diode string 314 (Dd1, Dd2 ..., Ddn) be forward biasing, thus the esd discharge electric current can via the second diode string 314 (Dd1, Dd2 ..., Ddn) discharge into Vss.
Figure 12 is the ESD protection circuit that the non-gate diode of SOI of Fig. 2 of the present invention or Fig. 9 is used in expression.As shown in figure 12, ESD protects this circuit and comprises an input welding block (input pad) 320, the first diode D1, the second diode D2, the 3rd diode D3, the 4th diode D4, input resistance R, High Voltage Power Supply line (Vdd voltage supply rail) Vdd, low voltage power supply line (Vss voltage supplyrail) Vss, nmos pass transistor Mn and ESD clamped circuit (ESD clamp circuit) 324.Internal circuit 322 is connected between the drain electrode of High Voltage Power Supply line Vdd and low voltage power supply line Vss, input resistance R and nmos pass transistor Mn.The first diode D1 and the second diode D2 are cascaded, and wherein the anode of the first diode D1 is connected to input welding block 330, and the negative electrode of the second diode D2 is connected to Vdd.The 3rd diode D3 and the 4th diode D4 are cascaded, and wherein the anode of the 3rd diode D3 is connected to Vss, and the negative electrode of the 4th diode D4 is connected to input welding block 320.The end of input resistance R is connected to welding block 320 and the other end is connected to drain electrode and the internal circuit 322 of nmos pass transistor Mn.The grid of nmos pass transistor Mn then is connected to Vss with source electrode.Above-mentioned diode D1, D2, D3 and D4 all can be earlier figures 2 or the non-gate diode of SOI shown in Figure 9.
The circuit operation of Figure 12 is identical with front Figure 10 or Figure 11 basically, at this just not in many narrations.As shown in figure 12, first and second diode D1, D2 are the diode D1 that is used for replacing among Figure 10 or Figure 11, and the 3rd and the 4th diode D3, D4 are used for replacing the diode D2 among Figure 10 or Figure 11.The parasitic junction capacitance of supposing diode D1 is C1, and the parasitic junction capacitance of diode D2 is C2, and the parasitic junction capacitance of diode D3 is C3, and the parasitic junction capacitance of diode D4 is C4.Then the input capacitance Cin of Figure 10 is C1+C2, and is [C1C2/ (C1+C2)]+[C3C4/ (C3+C4)] at the input capacitance Cin ' of present embodiment (Figure 12).If diode D1, D2, D3 are all identical with D4, then represent C1=C2=C3=C4=C.So can obtain Cin=2C, and Cin '=C.Therefore, the input capacitance of the example of Figure 12 just reduces, and also causes the RC time constant to diminish.By reducing input delay, this ESD protection circuit just can be applied to high frequency (high frequency, HF) circuit.
Figure 13 is that one of expression Figure 12 changes example.One diode string 334 is formed between Vdd and the Vss, and diode string 334 is as the usefulness of ESD clamped circuit.Diode string 334 comprise the diode DP1, the Dp2 that are connected in series ..., Dpn, all can be earlier figures 2 or the non-gate diode of SOI shown in Figure 9.
Therefore, advantage of the present invention is as follows:
1. non-gate diode of the present invention is compatible mutually with manufacturing process fully.That is no matter SOICMOS manufacturing process (as Fig. 5 A to shown in Fig. 5 G) or extensive CMOS manufacturing process (as Fig. 7 A to shown in Fig. 7 G) are all suitable.
2. owing to than gate diode more PN junction zone is arranged, SOI provided by the invention is non-, and the gate diode has lower power density.
3. owing to than gate diode more PN junction zone is arranged, the non-gate diode of SOI provided by the invention has higher anti-ESD degree.
4. the non-gate diode of SOI provided by the invention can be applied in mixed-voltage and analog/digital is used.In addition, the non-gate diode of SOI provided by the invention more can be used as output and goes into the ESD protection circuit, and under the situation of forward biasing as the protective circuit between Vdd and Vss.
In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; when can carrying out various changes and improvement, so protection scope of the present invention is as the criterion with the appending claims restricted portion.
Claims (47)
1. the non-gate diode structure of an insulator-base epitaxial silicon comprises:
One insulator-base epitaxial silicon substrate comprises that a substrate, an insulating barrier and a silicon layer pile up in regular turn;
A pair of isolation structure is arranged in this silicon layer, makes between this is to isolation structure with in this silicon layer to have a well region;
One first type ion implanted region and one second type ion implanted region are arranged in this well region and are close to respectively this isolation structure respectively.
2. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.
3. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this well region injects the P type ion of low concentration.
4. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this well region injects the N type ion of low concentration.
5. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this insulating barrier is the flush type oxide layer.
6. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this is a fleet plough groove isolation structure to isolation structure.
7. the non-gate diode structure of an insulator-base epitaxial silicon comprises:
One insulator-base epitaxial silicon substrate comprises that a substrate, an insulating barrier and a silicon layer pile up in regular turn;
A pair of isolation structure is arranged in this silicon layer, makes between this is to isolation structure with in this silicon layer to have one first well region and one second well region, and wherein this first well region is adjacent with this second well region;
One first type ion implanted region and one second type ion implanted region, lay respectively at this first with this second well region in, and next-door neighbour's this isolation structure respectively respectively, with this make in the non-gate diode element of this insulator-base epitaxial silicon become this first with the knot of this second well region.
8. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 7, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.
9. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 8, wherein this first injects the P type and the N type ion of low concentration respectively with this second well region.
10. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 7, wherein this insulating barrier is the flush type oxide layer.
11. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 7, wherein this is a fleet plough groove isolation structure to isolation structure.
12. the non-gate diode structure of extensive COMS comprises:
One substrate, this substrate has a trap;
A pair of isolation structure is arranged in this substrate and is arranged in this trap;
One first type ion implanted region is arranged in this trap, and between this is to isolation structure; And
The a pair of second type ion implanted region is arranged in trap and is close to respectively this isolation structure respectively, wherein should separate with this first type ion implanted region with this trap respectively the second type ion implanted region.
13. the non-gate diode of extensive COMS as claimed in claim 12, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.
14. the non-gate diode of extensive COMS as claimed in claim 12, wherein this well region injects the P type ion of low concentration.
15. an application rights requires the electrostatic storage deflection (ESD) protection circuit of any one described non-gate diode element in 1 to 14, is coupled between an input welding block and the internal circuit, comprising:
An one High Voltage Power Supply line and a low voltage power supply line all are coupled to this internal circuit;
One first diode, its anode are coupled to this High Voltage Power Supply line and its negative electrode is coupled to a node;
One second diode, its negative electrode are coupled to this low voltage power supply line and its anode is coupled to this node;
One first diode string is made of the series connection of a plurality of diodes, and wherein its anode is coupled to this High Voltage Power Supply line and its negative electrode is coupled to this node; And
One second diode string, constitute by a plurality of diode series connection, its negative electrode is coupled to this low voltage power supply line and its anode is coupled to this node, wherein in each diode in this first diode string, each diode in this second diode string, this first diode, this second diode one of them is non-gate diode at least.
16. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein when the positive voltage with respect to this High Voltage Power Supply line put on this input welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via the discharge path of this first diode to this High Voltage Power Supply line.
17. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein when the negative voltage with respect to this low voltage power supply line put on this input welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via the discharge path of this second diode to this low voltage power supply line.
18. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein when the negative voltage with respect to this High Voltage Power Supply line put on this input welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via this second diode, this second diode string and this first diode string discharge path to this High Voltage Power Supply line.
19. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein when the positive voltage with respect to this low voltage power supply line put on this input welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via this first diode, this first diode string and this second diode string discharge path to this low voltage power supply line.
20. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein this first with this second diode with this first with this second diode string in each diode be non-gate diode, and utilize the manufacturing process making of insulator-base epitaxial silicon (SOI).
21. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein this first with this second diode with this first with this second diode string in each diode be non-gate diode, and utilize the manufacturing process making of mass metal oxide semiconductor.
22. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein this first measure-alike with this second diode all has equal junction capacitance.
23. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein this is first inequality with the size of this second diode, and its junction capacitance is all inequality.
24. an application rights requires the electrostatic storage deflection (ESD) protection circuit of any one described non-gate diode element among the 1-14, is coupled between an output welding block and the pre-driver, comprising:
An one High Voltage Power Supply line and a low voltage power supply line are couple to this pre-driver respectively;
One first diode, its anode are coupled to this High Voltage Power Supply line and its negative electrode is coupled to a node;
One second diode, its negative electrode are coupled to this low voltage power supply line and its anode is coupled to this node;
One first diode string is made of the series connection of a plurality of diodes, and wherein its anode is coupled to this High Voltage Power Supply line and its negative electrode is coupled to this node;
One second diode string is made of a plurality of diode series connection, and its negative electrode is coupled to this low voltage power supply line and its anode is coupled to this node;
One first type MOS transistor, its source electrode are couple to this High Voltage Power Supply line, and its drain electrode is couple to this node, and its grid is couple to this pre-driver; And
One second type MOS transistor, its source electrode are couple to this low voltage power supply line, and its drain electrode is couple to this node, and its grid is couple to this this grid of first type MOS transistor,
Wherein in each diode in this first diode string, each diode in this second diode string, this first diode, this second diode one of them is non-gate diode at least.
25. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein when the positive voltage with respect to this High Voltage Power Supply line put on this output welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via the discharge path of this first diode to this High Voltage Power Supply line.
26. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein when the negative voltage with respect to this low voltage power supply line put on this output welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via the discharge path of this second diode to this low voltage power supply line.
27. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein when the negative voltage with respect to this High Voltage Power Supply line put on this output welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via this second diode, this second diode string and this first diode string discharge path to this High Voltage Power Supply line.
28. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein when the positive voltage with respect to this low voltage power supply line put on this output welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via this first diode, this first diode string and this second diode string discharge path to this low voltage power supply line.
29. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this first with this second diode with this first with this second diode string in each diode be non-gate diode, and utilize the manufacturing process making of insulator-base epitaxial silicon (SOI).
30. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this first with this second diode with this first with this second diode string in each diode be non-gate diode, and utilize the manufacturing process making of mass metal oxide semiconductor.
31. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this first measure-alike with this second diode all has equal junction capacitance.
32. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this is first inequality with the size of this second diode, and its junction capacitance is all inequality.
33. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this first type MOS transistor is the PMOS transistor, and this second type MOS transistor is a nmos pass transistor.
34. an application rights requires the electrostatic storage deflection (ESD) protection circuit of any one described non-gate diode element among the 1-14, is coupled between an input welding block and the internal circuit, comprising:
An one High Voltage Power Supply line and a low voltage power supply line all are coupled to this internal circuit;
One first diode and one second diode are connected together, and wherein the anode of this first diode is coupled to a node, and the negative electrode of this second diode is coupled to this High Voltage Power Supply line;
One the 3rd diode and one the 4th diode are connected together, and wherein the anode of the 3rd diode is coupled to this low voltage power supply line, and the negative electrode of the 4th diode is coupled to this node; And
One ESD (Electrostatic Discharge) clamp circuit is coupled between this High Voltage Power Supply line and this low voltage power supply line,
Wherein this ESD (Electrostatic Discharge) clamp circuit is in series by a plurality of diodes, and its anode is couple to this High Voltage Power Supply line and its negative electrode is couple to this low voltage power supply line,
Wherein in the 3rd diode, the 4th diode, this first diode, this second diode one of them is non-gate diode at least.
35. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein this first, this second, the 3rd with the 4th diode and this ESD (Electrostatic Discharge) clamp circuit in each diode be non-gate diode, and utilize the manufacturing process of insulator-base epitaxial silicon (SOI) to make.
36. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein this first, this second, the 3rd is non-gate diode with the 4th diode, and utilizes the manufacturing process of mass metal oxide semiconductor to make.
37. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein each diode in this ESD (Electrostatic Discharge) clamp circuit is non-gate diode, and utilizes the manufacturing process of insulator-base epitaxial silicon (SOI) to make.
38. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein each diode in this ESD (Electrostatic Discharge) clamp circuit is non-gate diode, and utilizes the manufacturing process of mass metal oxide semiconductor to make.
39. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein this first, this second, the 3rd measure-alike with the 4th diode, all have equal junction capacitance.
40. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein this first, this is the second, the 3rd inequality with the size of the 4th diode, its junction capacitance is all inequality.
41. a method that forms the non-gate diode of insulator-base epitaxial silicon comprises:
One insulator-base epitaxial silicon substrate is provided, comprises that a substrate, an insulating barrier and a silicon layer pile up in regular turn; Form a pair of isolation structure in this silicon layer, make between this is to isolation structure with in this silicon layer to have a well region;
Form one first type ion implanted region and one second type ion implanted region in this well region, and be close to respectively this isolation structure respectively.
42. the method for the non-gate diode of formation insulator-base epitaxial silicon as claimed in claim 41, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.
43. the method for the non-gate diode of formation insulator-base epitaxial silicon as claimed in claim 41, wherein this well region injects the P type ion of low concentration.
44. the method for the non-gate diode of formation insulator-base epitaxial silicon as claimed in claim 41, wherein this well region silicon injects the N type ion of low concentration.
45. a method that forms the non-gate diode of extensive COMS comprises:
One substrate is provided, forms a trap in this substrate;
Form a pair of isolation structure in this substrate, described isolation structure is arranged in this trap;
Form one first type ion implanted region in this trap, and between this is to isolation structure; And
Form a pair of second type ion implanted region in this well region, and be close to respectively this isolation structure respectively, respectively this second type ion implanted region separates with this first type ion implanted region with this trap respectively.
46. the method for the non-gate diode of the extensive COMS of formation as claimed in claim 45, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.
47. the method for the non-gate diode of the extensive COMS of formation as claimed in claim 45, wherein this well region injects the P type ion of low concentration.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/060,743 US6933573B2 (en) | 2002-01-23 | 2002-01-30 | Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof |
| US10/060,743 | 2002-01-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1435883A CN1435883A (en) | 2003-08-13 |
| CN100490143C true CN100490143C (en) | 2009-05-20 |
Family
ID=27658331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021412871A Expired - Lifetime CN100490143C (en) | 2002-01-30 | 2002-07-05 | Non-gate-controlled diode, electrostatic discharge protection circuit and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100490143C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100454553C (en) * | 2004-07-23 | 2009-01-21 | 精工爱普生株式会社 | Thin film semiconductor device and method of manufacturing the same, electro-optical device, and electronic apparatus |
| CN100353494C (en) * | 2005-04-27 | 2007-12-05 | 上海华虹Nec电子有限公司 | Improvement for ESD transistor source leaked capacitance |
| US8906751B2 (en) | 2011-01-06 | 2014-12-09 | International Business Machines Corporation | Silicon controlled rectifiers (SCR), methods of manufacture and design structures |
| CN106206565B (en) * | 2015-05-08 | 2019-04-23 | 创意电子股份有限公司 | Diode and diode string circuit |
| CN105680107B (en) * | 2016-03-16 | 2018-09-25 | 中国科学院上海微系统与信息技术研究所 | A kind of battery management chip circuit based on SOI technology |
| KR20170143194A (en) * | 2016-06-21 | 2017-12-29 | 에스케이하이닉스 주식회사 | Apparatus for protecting semiconductor circuit |
-
2002
- 2002-07-05 CN CNB021412871A patent/CN100490143C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1435883A (en) | 2003-08-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7141484B2 (en) | Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof | |
| US6861680B2 (en) | Silicon-on-insulator diodes and ESD protection circuits | |
| US6444511B1 (en) | CMOS output circuit with enhanced ESD protection using drain side implantation | |
| US7525779B2 (en) | Diode strings and electrostatic discharge protection circuits | |
| US6909149B2 (en) | Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies | |
| CN1652331B (en) | Device for electrostatic discharge protection and circuit thereof | |
| JP4856803B2 (en) | Lateral bipolar device with substrate-triggered electrostatic breakdown protection or electrical overstress protection | |
| US6838328B1 (en) | Back-biased MOS device fabrication method | |
| CN100477205C (en) | Transistors for electrostatic discharge protection and method for forming two transistors close to each other | |
| US5883414A (en) | Electrostatic discharge protection device | |
| KR20050122166A (en) | Separated power esd protection circuit and integrated circuit thereof | |
| CN100541800C (en) | Buffer circuits with electrostatic discharge protection | |
| US5898193A (en) | Electrostatic discharge protecting circuit formed in a minimized area | |
| US6590264B2 (en) | Hybrid diodes with excellent ESD protection capacity | |
| CN100490143C (en) | Non-gate-controlled diode, electrostatic discharge protection circuit and manufacture method thereof | |
| US6826026B2 (en) | Output buffer and I/O protection circuit for CMOS technology | |
| CN101159263A (en) | Electrostatic discharge protection of a clamp | |
| TWI224380B (en) | Improving the triggering of an ESD NMOS through the use of an n-type buried layer | |
| TW202236428A (en) | Silicon-controlled rectifier | |
| KR20040082832A (en) | Protecting device of semiconductor device | |
| KR100220384B1 (en) | Electrostatic electricity protection device | |
| US20230223397A1 (en) | Electrostatic protection structure and method for fabricating electrostatic protection structure | |
| US7667280B2 (en) | Semiconductor device | |
| KR960016483B1 (en) | Semiconductor integrated circuit device & method for manufacturing the same | |
| JP3434747B2 (en) | Input protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20090520 |
|
| CX01 | Expiry of patent term |