CN100487810C - MP3 decoding filter system based on reconfigurable arithmetic unit - Google Patents

Abstract

The invention is a MP3 decoding filter system based on reconfigurable operation unit in the information technical field, comprising: reconfigurable operation unit, and control unit, where the reconfigurable operation unit can complete arithmetic operation according to different setting modes and operating instructions and writes the final results into corresponding storage units or directly outputs them; and the control unit dynamically sets the reconfigurable operation unit and supplies operation instructions to it to control it to complete MP3 decoding filter according to MP3 decoding filter standard, the reconfigurable operation unit mainly comprises operation unit ALU and storage units ROM and RAM and concretely completes MP3-decoded data processing, and the used storage mode maximumly considers the symmetrical character of MP3 decoding filter so as to least occupy ROM and RAM. And it takes into account decoding efficiency and hardware implementation.

Description

MP3 decoding filter system based on reconfigurable arithmetic unit

Technical field

What the present invention relates to is a kind of decode system of areas of information technology, specifically a kind of MP3 decoding filter system based on reconfigurable arithmetic unit.

Background technology

The compound filter system that the standard MP3 decoding process that MPEG 1 audio compress standard in 1993 proposes has adopted contrary improvement discrete cosine transform (IMDCT) and quadrature mirror filter bank (QMF) to combine.Wherein, only QMF just will take nearly 40% decode time.Simultaneously, compound filter is counted based on multiply-add operation and computing and is had nothing in common with each other.This will use a large amount of storage unit to store various coefficients and intermediate data when hardware is realized, make that the hardware resource expense is big, and chip area is big, real-time is poor, causes the raising of power consumption and cost.At present, the realization of MP3 decoding filter system mainly contains based on general processor with based on dedicated IC chip.But the former provides special-purpose arithmetic element, can improve to carry out efficient be difficult to the power consumption that provides lower.And the latter is not quite flexible aspect program upgrade, but can provide low-power consumption with low-cost, can provide best cost performance by rational design of hardware and software, therefore is the better selection towards mobile voice applications.

Find that by prior art documents the realization of MP3 decoding filter system mainly concentrates on explores efficiently system architecture being fit to various fast algorithms, thereby improves the performance of system.Byeong Gi Lee had proposed discrete cosine transform (DCT) fast algorithm and butterfly computation structure in 1984.Scott B Marovich in 2000 has proposed to realize based on the MP3 wave filter of inverse discrete cosine transform (IDCT) in document " Faster MPEG-1 Layer III Audio Decoding " (HP Laboratories Palo Alto, June 2000).The MP3 decoding filter system that adopts such scheme the to realize employing more system resources of having nothing for it but comprises arithmetic element and storage unit.Reason is that system realizes yielding to simply in the software fast algorithm having ignored implement of hardware system optimization.Though DCT algorithm has with discrete Fourier transform (DFT) (FFT) and has similar butterfly computation structure, the coefficient of its each node is not positive and negative one, so needs to open up extra storage space in the system and deposit the node coefficient.And in the decode procedure request of storage unit has also just been reduced the processing speed of system.Simultaneously, according to the relation of counting of the computing in the whole filter system, system has to construct the DCT kernel operation module of different bases, makes that final hardware system resource overhead is huge.

In order to change the undue dependence of said system for the software fast algorithm, a lot of MP3 decoding solution suppliers have adopted the system based on FFT nuclear to form mode, and total system adds that round FFT kernel operation module peripheral storage unit and control module constitute.But this system has introduced a lot of extra arithmetic elements, has increased the expense of system hardware realization resource.

In sum, present most document and scheme more are partial to seeking the compromise that a kind of decoding speed and hardware are realized, but all can not satisfactory to both parties neat U.S..From the angle towards mobile voice applications, principle of design should be minimum in the hardware resource expense preferably, and the volume minimum is least in power-consuming and satisfy under the condition of real-time decoding, improves decoding speed most possibly.

Summary of the invention

The present invention is directed to the deficiencies in the prior art and defective, a kind of MP3 decoding filter system based on reconfigurable arithmetic unit is provided.MPEG 1 Layer III proposes that decoding function that standard MP3 decoding filter process and aforementioned numerous optimized Algorithm and prioritization scheme all be based on each step divides filter system, the present invention then is based on hard-wired function and comes the division of this filter system is divided, and has taken into account decoding efficiency and hard-wired system.

The present invention is achieved by the following technical solutions, and the MP3 decoding filter system that the present invention is based on reconfigurable arithmetic unit comprises: reconfigurable arithmetic unit and control module two parts.Comprise: reconfigurable arithmetic unit, control module, reconfigurable arithmetic unit is finished arithmetic operator according to different set-up modes and operational order, and net result is write corresponding storage unit or directly output.Control module is according to MP3 decoding filtering standard, dynamically reconfigurable arithmetic unit is provided with and provides its operational order, control it and finish MP3 decoding filtering, reconfigurable arithmetic unit mainly is made up of arithmetic unit ALU and storage unit ROM and RAM, specifically finish the processing of MP3 decoding data, the storage mode that adopts has been considered the symmetry characteristics in the MP3 decoding filtering to greatest extent, makes the use of ROM and RAM be minimum.

System of the present invention has " streamline " and " circulation " two kinds of processing modes based on the design of restructural thought.Reconfigurable arithmetic unit is finished the data operation under the different working modes, and control module provides its execution parameter and processing instruction according to MP3 standard configuration reconfigurable arithmetic unit working method.So-called " restructural " can dynamically arrange according to current configuration parameter with regard to being meant arithmetic element of the present invention, thereby realizes sharing of calculation function modules different in the MP3 decoding filtering.So-called " streamline " processing mode is that 3 counters are postponed one-period in turn, the operation that each counter is corresponding different.So-called " circulation " processing mode is that 1 counter is set to the analytic accounting number, carries out corresponding operation in the different moment, and another one or two counters carry out cycle count.

The present invention is based on the MP3 decoding wave filter, this wave filter is the compound filter that combines against improvement discrete cosine transform IMDCT and accurate quadrature mirror filter PQMF (comprising the different IMDCT that count of IMDCT and a QMF with the front).It comprises all processing that anti-aliasing in the MP3 decoding process (Anti-Aliasing) is later, the IMDCT of long window or short window is specifically arranged, aliasing addition, IMDCT among the PQMF and the QMF among the PQMF.

Advantage of the present invention is as follows: (1) the present invention realizes towards concrete hardware, adopted advanced restructural thought to realize that from hardware functional perspective is divided into a reconfigurable arithmetic unit and a control module with the MP3 decoding filter system, make hardware not have the submodule of repeat function when realizing, significantly reduced the expense of hardware resource.Thereby reduced chip area, reduced power consumption, can satisfy the needs of mobile audio frequency apparatus well.(2) the present invention uses minimum at hardware resource, the volume minimum, least in power-consuming and satisfy under the condition of real-time decoding, excavated the symmetry characteristics in the MP3 decoding process to greatest extent, introduce the filter process mode that three class pipeline is handled, improved decoding speed greatly.Simultaneously, with the control module matching Design ROM and the RAM allocation scheme of minimum MP3 decoding filter system, all computings are also undertaken by the mode of asking a shared arithmetic element, have further reduced hardware and have realized the expense of resource and final chip area.(3) because the present invention does not adopt the various fast algorithms of existing document, and therefore symmetry characteristics ubiquity in current audio and video standard has very strong extendability.Be easy to thought of the present invention and characteristics are applied in other media application.

Description of drawings

Fig. 1 is the structural representation of reconfigurable arithmetic unit of the present invention

Fig. 2 is pipeline system of the present invention and recycle design synoptic diagram

Fig. 3 is the mode that the reads synoptic diagram of the special ROM of the present invention

Fig. 4 is the read-write mode synoptic diagram of the special RAM of the present invention

Embodiment

As shown in Figure 1, system of the present invention comprises the two large divisions: control module and reconfigurable arithmetic unit.Reconfigurable arithmetic unit is finished arithmetical operation according to different set-up modes and operational order, and net result is write corresponding storage unit or directly output.Control module is according to MP3 decoding filtering standard, dynamically reconfigurable arithmetic unit is provided with and its operational order is provided, and controls it and finishes MP3 decoding filtering.Reconfigurable arithmetic unit mainly is made up of arithmetic unit ALU and storage unit ROM and RAM, specifically finishes the processing of MP3 decoding data.The storage mode that adopts has been considered the storage data in the MP3 decoding filtering and the symmetry of process data to greatest extent, makes the use of ROM and RAM be minimum.

As shown in Figure 2, two kinds of mode of operation synoptic diagram of the present invention.Reconfigurable arithmetic unit by with 1 static data memory module ROM, 4 pilot process data memory module RAM (corresponding granularity RAM of RAM1, the corresponding stack of RAM2 RAM, the RAM of the corresponding PQMF of RAM3, the audio frequency PCM buffer memory of the corresponding output of RAM4), 1 arithmetical logic and arithmetic unit ALU, three internal counters and form with the instruction and data interface of external control unit have " streamline " and " circulation " two kinds of processing modes.

" streamline " processing mode postpones one-period in turn by 3 inner countings and realizes that correspondence is read ROM respectively, different disposal such as read-write RAM and request ALU.In the MP3 decoding filtering, reconfigurable arithmetic unit adopts the three class pipeline mode, corresponding long piece IMDCT, windowing and stack, IMDCT among the PQMF and QMF decoding." circulation " processing mode realizes by 2 internal counters.One is basic counter, utilizes different count values or scope to unify correspondence and reads ROM, different disposal such as read-write RAM and request ALU.Another then carries out cycle count to it.The only corresponding short block IMDCT of this mode in MP3 decoding filtering.

Control module carries out the real-time and dynamic setting according to MP3 decoding filtering standard to reconfigurable arithmetic unit, makes it have different computing characteristics and function, and its different operational order is provided simultaneously.This inside, unit also is provided with the counter of the overall situation, " streamline " and " circulation " counting mode of reconfigurable arithmetic unit inside is carried out the cycle count of the overall situation.

The storage space minimum of static data and intermediate data is a key character of system of the present invention.

The smallest allocation mode of ROM is based on dynamic windowing coefficient, the minimizing of the D coefficient storage of QMF among IMDCT cosine coefficient and the PQMF among the PQMF.Their storage numerical value is as follows:

24 dynamic windowing coefficients

$\mathrm{win}\left(n\right)=\left\{\begin{array}{c}\sin \left(\frac{\mathrm{\π}}{36}(n+\frac{1}{2})\right),n=\mathrm{0,1},..,17\\ \sin \left(\frac{\mathrm{\π}}{12}(n-18+\frac{1}{2})\right),n=\mathrm{18,19},...,23\end{array}\right.$

IMDCT cosine coefficient among 512 PQMF

$\cos \left[\frac{(n+33)(2k+1)\mathrm{\π}}{64}\right],k=\mathrm{0,1},...,15;n=\mathrm{0,1},...,31$

D[1 in 512 D coefficients that provide in the D coefficient of the QMF store M P3 standard among the PQMF] to D[256] totally 256 points.

The mode that the reads synoptic diagram of these three ROM storage unit is only stored different numerical value and non-0, non-positive and negative 1 coefficient as shown in Figure 3.For the address of reading that symmetrical numerical value adopts symmetry, avoid repeated storage.

The smallest allocation mode of RAM is based on 18 Different Results of long window IMDCT, current 32 address spaces that will upgrade shared and reduce by half and special read-write mode for the output result's of the IMDCT among the PQMF memory space among 24 Different Results of short window IMDCT and the RAM3.The ram memory cell that these are special share and the read-write mode synoptic diagram as shown in Figure 4, only store non-0 and non-positive and negative 1 data.Data for symmetry are only stored once, and read-write is carried out according to the symmetric relation of data, avoids repeated storage.

The concrete job step of system of the present invention is as shown in table 1:

Table 1 is based on the MP3 decoding filter system workflow and the setting of reconfigurable arithmetic unit

The first step: IMDCT

According to the input data is that long piece or short block are provided with reconfigurable arithmetic unit by step 1a or 1b in the table 1 respectively.Analyze as can be known by the IMDCT to standard MP3, the gained result has following symmetric relation:

$\left\{\begin{array}{c}x(\frac{N}{2}-1-n)=-x\left(n\right)\\ x(\frac{N}{2}+n)=x(N-1-n)\end{array}\right.,n=\mathrm{0,1},...,\frac{N}{4}-1$

Wherein, N counts for the output result's, and long piece is 36, and short block is 12.Therefore, half in the middle of only need calculate according to following formula be counted and just can be obtained all IMDCT values.

$x\left(n\right)=\underset{k=0}{\overset{N/2-1}{\mathrm{\Σ}}}X\left(k\right)\cos \left[\frac{\mathrm{\π}}{2N}(2k+1)(2n+1+N)\right],n=\mathrm{0,1},...,\frac{N}{2}-1$

Counter I correspondence in the reconfigurable arithmetic unit reads cosine coefficient among the ROM and the input data of RAM1; Counter j corresponding requests ALU carries out multiply-add operation; Counter k correspondence count down at every turn at 18 o'clock current I MDCT result is write RAM3.Whole process adopts the three class pipeline mode to carry out to raise the efficiency.External counting is counted IMDCT result.Long piece gained result need store 18 address spaces into, can share with current 32 address spaces that need to upgrade of PQMF.

Windowing and overlap-add operation between short block IMDCT also needs to carry out soon to 3 sub-pieces are so be arranged to recycle design with reconfigurable cell.Basic counter I from 0 to 5 correspondence reads the cosine coefficient the ROM, and 6 and 7 correspondences read the windowing coefficient of ROM; Basic counter I from 0 to 5 correspondence reads the input data the RAM1, and 6 and 7 correspondences read back 6 IMDCT results of the last sub-piece among the RAM3, the 8 and 9 corresponding positions that current IMDCT result write two symmetries among the RAM3; Basic counter I from 1 to 8 corresponding requests ALU carries out multiply-add operation.Counter j carries out cycle count 6 times to I.External counting carries out cycle count to 3 sub-pieces.3 short blocks will obtain 24 IMDCT results altogether, need 24 address spaces to store, and also can share with current 32 address spaces that need to upgrade of PQMF.

The first step has been finished single IMDCT to long piece, short block has been finished the windowing and the stack of IMDCT and sub-interblock.Current 32 address spaces that need to upgrade are shared among gained IMDCT result and the PQMF.

Second step: windowing and stack

Only finished IMDCT for the long piece first step, then will be to 36 IMDCT windowings as a result, and back 18 IMDCT values stack of the previous frame same position among preceding 18 IMDCT values and the RAM2 and value will be upgraded 18 values of current block among the RAM1.Because windowing and stack just constitute multiply-add operation, two steps of this of long piece can merge to raise the efficiency.Back 18 IMDCT values of this moment will be used for upgrading 18 previous frame IMDCT results of RAM2.

For short block, in first step IMDCT process, carried out windowing, only need carry out in this step with RAM2 in back 18 IMDCT results' the stack and the renewal of previous frame same position.

The MP3 standard provides 3 kinds 36 long window and a kind of short window, 120 windowing coefficients altogether at 12.The present invention obtains its symmetrical characteristics by the analysis to these coefficients, has only stored 24 following windowing coefficients in ROM, has reduced memory space.Specifically read in the process of ROM windowing coefficient as long as read the address according to the type adjustment of window.

$\mathrm{win}\left(n\right)=\left\{\begin{array}{c}\sin \left(\frac{\mathrm{\π}}{36}(n+\frac{1}{2})\right),n=\mathrm{0,1},..,17\\ \sin \left(\frac{\mathrm{\π}}{12}(n-18+\frac{1}{2})\right),n=\mathrm{18,19},...,23\end{array}\right.$

According to step 2 in the table 2 reconfigurable arithmetic unit is set.External counting is to superpose in 0 o'clock.During long piece, counter I correspondence reads the windowing coefficient among the ROM, reads back 18 IMDCT values of previous frame among the RAM2, reads current preceding 18 the IMDCT values among the RAM3; Counter j corresponding requests ALU takes advantage of and adds processing; Counter k correspondence writes RAM1 with the result of IMDCT windowing and stack.External counting is 1 to upgrade.During long piece, counter I correspondence reads the windowing coefficient among the ROM, reads back 18 values of the current I MDCT of RAM3 kind; Counter j correspondence writes RAM2 and upgrades; Counter k does not carry out any processing.

For short block, have only 24 effective IMDCT values according to the standard of MP3, to fill 60 sequences of synthesizing at 36 at two ends.Do not fill 0 processing in the present invention.As long as when handling short block, to external counting be 0 o'clock 0 to 5 and external counting at counter I be 13 to 18 o'clock of 1 hour counter I be provided with the value of reading from RAM3 be 0 or these the time do not read RAM3 and get final product.

The 3rd step: the IMDCT among the PQMF

The IMDCT among the PQMF and the IMDCT of front are basic identical, are 32 points but count.By the IMDCT among the PQMF in the MP3 standard is analyzed as can be known, have following symmetric relation among 64 IMDCT results:

$\left\{\begin{array}{cc}y(32-n)=-y\left(n\right)& n=\mathrm{0,1},...,15\\ y(32+n)=y(64-n)& n=\mathrm{1,2},...,15\\ y\left(16\right)=0& \end{array}\right.$

Therefore, 32 values that can be calculated as follows n from 17 to 48 get final product.

$y\left(i\right)=\underset{k=0}{\overset{15}{\mathrm{\Σ}}}S\left(k\right)\cos \left[\frac{(n+33)(2k+1)\mathrm{\π}}{64}\right]+{(-1)}^{n+1}\underset{k=16}{\overset{31}{\mathrm{\Σ}}}S\left(k\right)\cos \left[\frac{(n+33)(2(31-k)+1)\mathrm{\π}}{64}\right],i=\mathrm{0,1},...,31$

Here considered the symmetry of cosine function, making the cosine coefficient that is stored in ROM is 512, than being a half in the standard.Can find that further n is at 31 o'clock, cosine coefficient is-1, therefore can reduce by 16 storages of cosine coefficient in ROM again.Therefore, the minimum memory quantity of cosine coefficient herein in ROM is 496.

In addition, all having opened up size for each sound channel in the MP3 standard is that the RAM of 1024 data carries out PQMF.The present invention is based on the symmetry that proposes above, with 64 IMDCT result cunchu32 that need in the standard to store, half reads by symmetry in addition, therefore only is required to be the RAM that each sound channel is opened up 512 data, significantly reduces storage space.

According to step 3 in the table 1 reconfigurable arithmetic unit is set.Counter I correspondence reads cosine coefficient among the ROM, and correspondence reads the subband data among the RAM1; Counter j corresponding requests ALU carries out multiply-add operation; The corresponding counting of counter k write RAM3 with IMDCT result at full 32 o'clock.External counter is counted to IMDCT and is carried out 32 countings.

The 4th step: the QMF among the PQMF

QMF among the PQMF mainly carries out windowing to the IMDCT data of the PQMF among the RAM3 to be taken advantage of and adds, output PCM value.512 D coefficients are provided in the MP3 standard, by getting following symmetric relation to its analysis:

$\left\{\begin{array}{c}D(257+i)=-D(255-i),i=\mathrm{0,1},...,254,i\≠\mathrm{63,127,191}\\ D(257+i)=D(255-i),i=\mathrm{63,127,191}\\ D\left(0\right)=0\end{array}\right.$

Therefore, the present invention has only stored 256 D coefficients in ROM, is minimum stored number.

According to step 4 in the table 1 reconfigurable arithmetic unit is set.Counter I correspondence reads the D coefficient among the ROM, reads the IMDCT value among the PQMF among the RAM3; Counter j corresponding requests ALU carries out multiply-add operation; Full 16 o'clock PCM values with output of the each counting of counter k write the PCM buffer memory.The outside is carried out 32 countings by a counter to the PCM value quantity of output, and another counter is counted 18 pieces.

According to four steps in the table 1 a MP3 granularity (Granule, 576 data) is carried out the wave filter decoding, each frame is handled two granularities totally 1152 data.Here the counter of mentioning not is powerful counter, be a variable among the corresponding RTL, so itself can not introduce very big hardware resource expense yet.

Claims (4)

1. MP3 decoding filter system based on reconfigurable arithmetic unit, comprise: control module, reconfigurable arithmetic unit, it is characterized in that, reconfigurable arithmetic unit is finished arithmetic operator according to different set-up modes and operational order, and net result is write corresponding storage unit or directly output; Control module is according to MP3 decoding filtering standard, dynamically reconfigurable arithmetic unit is provided with and its operational order is provided, and controls it and finishes MP3 decoding filtering; Reconfigurable arithmetic unit mainly is made up of arithmetic operator unit and ROM (read-only memory) and random access memory, this reconfigurable arithmetic unit is specifically finished the processing of MP3 decoding data, the smallest allocation mode that adopts has been utilized the symmetry characteristics in the MP3 decoding filtering, and feasible use to ROM (read-only memory) and random access memory obtains reducing.

2. the MP3 decoding filter system based on reconfigurable arithmetic unit according to claim 1, it is characterized in that, described reconfigurable arithmetic unit is by 1 ROM (read-only memory), 4 random access memory, 1 arithmetic operator unit and three internal counters are formed, wherein, the corresponding granularity random access memory of first random access memory, the corresponding stack of second random access memory random access memory, the random access memory of the corresponding accurate quadrature mirror filter of the 3rd random access memory, the pulse code modulation (PCM) buffer memory of the corresponding output of the 4th random access memory, this reconfigurable arithmetic unit has " streamline " and " circulation " two kinds of processing modes.

3. the MP3 decoding filter system based on reconfigurable arithmetic unit according to claim 1 and 2, it is characterized in that, described ROM (read-only memory), its smallest allocation mode minimizes based on the contrary D coefficient storage of improving quadrature mirror filter bank in discrete cosine transform cosine coefficient and the accurate quadrature mirror filter in dynamic windowing coefficient, the accurate quadrature mirror filter, and their storage numerical value is as follows:

24 dynamic windowing coefficients

$\mathrm{win}\left(n\right)=\left\{\begin{array}{c}\sin \left(\frac{\mathrm{\π}}{36}(n+\frac{1}{2})\right),n=\mathrm{0,1},...,17\\ \sin \left(\frac{\mathrm{\π}}{12}(n-18+\frac{1}{2})\right),n=18,19,...,23\end{array}\right.$

The contrary discrete cosine transform cosine coefficient that improves in 512 accurate quadrature mirror filters

$\cos \left[\frac{(n+33)(2k+1)\mathrm{\π}}{64}\right],k=\mathrm{0,1},...,15;n=\mathrm{0,1},...,31$

D[1 in 512 D coefficients that provide in the D coefficient of the quadrature mirror filter bank store M P3 standard in the accurate quadrature mirror filter] to D[256] totally 256 points; Described ROM (read-only memory) is only stored different numerical value and non-0, non-positive and negative 1 coefficient, the address of reading of adopting symmetry for symmetrical numerical value.

4. the MP3 decoding filter system based on reconfigurable arithmetic unit according to claim 1, it is characterized in that, described control module, inside are provided with the counter of the overall situation, " streamline " and " circulation " counting mode of reconfigurable arithmetic unit inside are carried out the cycle count of the overall situation.

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