CN100485924C - Semiconductor device, substrate, equipment board, method for producing semiconductor device, and semiconductor chip - Google Patents

Abstract

A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.

Description

Semiconductor device, substrate, device board, method, semi-conductor device manufacturing method and semiconductor chip

The cross reference of related application

The application comprises the relevant theme of submitting to Japan Patent office with on August 24th, 2004 of Japanese patent application JP2004-244019, quotes its full content as a reference at this.

Technical field

The manufacture method that the present invention relates to semiconductor device, substrate, device board, semiconductor device is used semiconductor chip with communicating by letter, more specifically, the manufacture method that relates to the semiconductor device that can reduce size of semiconductor device, substrate, device board, semiconductor device is used semiconductor chip with communicating by letter.

Background technology

Along with being extensive use of of electronic installation, the lamination techniques and the chip chamber wiring technique (for example, referring to the open No.8-316408 of Japanese unexamined patent) of the system (SIP) in encapsulation of multicore sheet and the encapsulation that realizes with low cost proposed.

Above-mentioned stacked a plurality of substrate has been described openly, another substrate joined on the side of stacked substrate and via joining stacked suprabasil substrate is connected to the terminal of stacked substrate the terminal that is provided with in lower area method to.

In the method that illustrates in the open No.8-316408 of Japanese unexamined patent, the quantity of terminal is subjected to the restriction of width of the side of substrate.In order to increase the quantity of terminal, must increase the quantity that joins the substrate on the side to.Because substrate only has four sides, so the available maximum length of terminal is four times of width of the side of substrate.Therefore, the quantity of terminal be increased, the width of the side of substrate must be increased.But the width that increases the side of substrate also can increase the overall dimensions of semiconductor device.

Semiconductor device can provide a large amount of terminals to reduce the overall dimensions of semiconductor device simultaneously according to an embodiment of the invention.

Summary of the invention

Semiconductor device comprises first substrate of platysome according to an embodiment of the invention, and this platysome has first surface and the second surface substantially parallel with first surface that is used to install electronic unit.First and second surfaces are set to be parallel to each other along the Width of substrate.First substrate comprises: be used to install first district on the platysome of electronic unit, comprise second district that is used on the platysome of/a plurality of first communication units of being provided with from the mode to troop of the second substrate transmission and received signal, in first district or the imput output circuit that is provided with of second district and being used to control the control circuit of the input and output of imput output circuit.Imput output circuit is corresponding to first communication unit, and each of imput output circuit comprise be used for signal output to second substrate corresponding with first communication unit the second communication unit output circuit and be used to receive the input unit of the signal that sends from corresponding second communication unit.Control circuit constitutes the input and output of control imput output circuit and is set in first district or second district of first substrate.

Semiconductor device can comprise the connection commutation circuit of the connection between the predetermined terminal of of being used for switching first communication unit and electronic unit.In first district of first substrate or second district, the connection commutation circuit is set.

In semiconductor device, first communication unit can be first through hole.First through hole in second district of first substrate is electrically connected with second suprabasil second through hole in the position corresponding with first through hole in second district of first substrate via first salient point.It is adjacent and substantially parallel with the platysome of first substrate that second substrate is set to.

Semiconductor can also comprise and is set to planar metal film substantially parallel with the platysome of first substrate and that separate.Metallic film engages with first substrate by second salient point, and wherein second salient point is inserted between metallic film and the substrate.

In semiconductor device, electronic unit can be set to contact setting with metallic film, makes that the heat that is produced by electronic unit can be left.

In semiconductor device, can in second district of first substrate, metallic film be set, make metallic film surround each first communication unit.

In semiconductor device, the part of metallic film can protrude through the outside, first district of first substrate.

In semiconductor device, metallic film can be via first salient point to the electronic unit feed.

In semiconductor device, first communication unit can be antenna.

Semiconductor device according to another embodiment of the present invention comprises a plurality of substrates, and these a plurality of substrates comprise first substrate to the, four substrates.Each of first substrate to the, four substrates comprises the platysome with the first surface that is used to install electronic unit and second surface substantially parallel with first surface, and this first and second surface is set to be parallel to each other along the Width of substrate.First electronic unit is installed in first substrate.Second electronic unit is installed in second substrate.When being set, second substrate make the first surface of the substrate of winning relative with the first surface of second substrate.The 3rd electronic unit is installed in the 3rd substrate.Quadrielectron parts are installed in the 4th substrate.When being set, the 4th substrate makes that the first surface of the 3rd substrate is relative with the first surface of the 4th substrate.On about the corresponding mutually position of second substrate and the 3rd substrate, second substrate and with the 3rd contiguous substrate of second substrate on be formed for the antenna of received signal.

In semiconductor device, can on the platysome of each substrate, form antenna in the mode of trooping.

Semiconductor device can also comprise the connection commutation circuit of the connection between the predetermined terminal of of being used for switched antenna and electronic unit.

Semiconductor device can also comprise the dull and stereotyped substantially parallel planar metal film that is set to respectively with substrate, and wherein, metallic film is to being arranged on suprabasil electronic unit feed.

In semiconductor device, metallic film can comprise: be set to first metallic film substantially parallel with the platysome of first and second substrates and that separate and be connected with first and second substrates via salient point; Be set to second metallic film substantially parallel with the platysome of third and fourth substrate and that separate and be connected with third and fourth substrate via salient point.First metallic film and second metallic film interconnect.

In semiconductor device, metallic film can comprise: be set to first metallic film substantially parallel with the platysome of first substrate and that separate and be connected with first substrate via closing line; Be set to second metallic film substantially parallel with the platysome of second substrate and that separate and be connected with second substrate via closing line; Be set to the 3rd metallic film substantially parallel with the platysome of the 3rd substrate and that separate and be connected with the 3rd substrate via closing line; Be set up the 4th metallic film substantially parallel with the platysome of the 4th substrate and that separate and be connected with the 4th substrate via closing line; First to fourth metallic film interconnects.

In semiconductor device, first substrate can comprise the 5th substrate, the 5th substrate has a plurality of via holes and is connected with first substrate via salient point, second substrate can comprise the 6th substrate, the 6th substrate has a plurality of via holes, be connected with second substrate via salient point, and be connected via the via hole of salient point with the 5th substrate that on the position corresponding, is provided with the via hole of second substrate, the 3rd substrate can comprise the 7th substrate, the 7th substrate has a plurality of via holes and is connected with the 3rd substrate via salient point, the 4th substrate can comprise the 8th substrate, and the 8th substrate has a plurality of via holes, be connected with the 4th substrate via salient point, and be connected via the via hole of salient point with the 7th substrate that on the position corresponding, is provided with the via hole of the 4th substrate.

In semiconductor device, first substrate can comprise first dividing plate with the first end that engages with first dividing plate, and second substrate can comprise the second partition that has the first end that engages with second substrate and be used in the second end that the salient point put between first dividing plate and the second partition engages with first dividing plate; The 3rd substrate can comprise the 3rd dividing plate with the first end that engages with the 3rd dividing plate, the 4th substrate can comprise have the first end that engages with the 4th substrate and be used in the 3rd dividing plate and the 4th dividing plate between the 4th dividing plate of the second end that engages with the 3rd dividing plate of the salient point put into.

Substrate according to another embodiment of the present invention comprises: be used to install first district on the platysome of electronic unit; Comprise second district that is used on the platysome of/a plurality of first communication units of being provided with from the mode to troop of the second substrate transmission and received signal; The imput output circuit that in first district or second district, is provided with, this imput output circuit is corresponding with first communication unit; Go up the control circuit of the input and output of the imput output circuit that is provided with first district that is used to be controlled at first substrate or second district.Each of imput output circuit comprises the input unit that is used for the output circuit and being used to that signal outputs to the second communication unit of second substrate corresponding with first communication unit is received the signal that sends from corresponding second communication unit.

Device board according to another embodiment of the present invention comprises: the semiconductor device that comprises a plurality of interior substrates that electronic unit is set on it; The first outer substrate of semiconductor device is installed; With prepare first outside, to be provided with on the position of installation semiconductor device in the substrate second outside substrate.At least substrate has the antenna that is used for received signal in outmost. and the first outer substrate is included in the antenna that is provided with on the corresponding position of the antenna that comprises with semiconductor device.

The manufacture method of semiconductor device according to another embodiment of the present invention may further comprise the steps: form antenna on about the corresponding mutually a plurality of suprabasil precalculated position of substrate; On the precalculated position on the first surface of each substrate, chip is set; Form manyly, make that the first surface of substrate is relative substrate; Assemble each to substrate, make antenna be positioned on the precalculated position of mutual correspondence and make second pair of substrate moulding.

The communication that is provided with in substrate comprises the two-way array of communication module with semiconductor chip.Each of communication module comprises: the antenna that is formed by coil pattern that is used to send or receives radio signals; Be used for to the transmitter circuit of antenna transmission signal and be used at least one from the acceptor circuit of antenna receiving signal; Be used for supply capability and wiring lines to transmitter circuit and acceptor circuit.

Use in the semiconductor chip in communication, in the communication module each can comprise transmitter circuit and acceptor circuit simultaneously, antenna can be connected with the output of transmitter circuit and the input of acceptor circuit, and transmitter circuit and acceptor circuit can comprise can by be made as individually enable with disabled status in one terminal.

Communication can also comprise the control unit that is used for controlling jointly a plurality of communication modules with semiconductor chip.

Use in the semiconductor chip in communication, in the acceptor circuit of communication module at least one can be the asynchronous receiver circuit, and other acceptor circuit is the synchronous receiver circuit, and communication can also comprise the modulation circuit that is used for based on supply with the clock signal of synchronous receiver circuit from the signal modulation of asynchronous receiver circuit with semiconductor chip.

Semiconductor device according to another embodiment of the present invention comprises a plurality of substrates of semiconductor chip, and this semiconductor chip has predetermined function and is set to and is parallel to each other substantially. these semiconductor chips are used to communicate by letter and are set at about the corresponding mutually position of substrate.In the semiconductor chip each comprises the two-way array of a plurality of communication modules, and these communication modules have the antenna that is formed by coil pattern that is used to receive or send radio signal.

In semiconductor device, other radio communication semiconductor device of semiconductor chip can be installed in the substrate outside being set to be installed on of substrate of substrate outside the most contiguous.

In semiconductor device, can with substrate outside on form groove on the communication of the installing position corresponding with semiconductor chip.

In semiconductor device, each in the communication module can comprise: antenna; Be used for to the transmitter circuit of antenna transmission signal and be used for from the acceptor circuit of antenna receiving signal at least one, be used for supply capability and wiring lines to transmitter circuit and acceptor circuit.

In semiconductor device, in the communication module each can comprise transmitter circuit and acceptor circuit simultaneously, antenna can be connected with the output of transmitter circuit and the input of acceptor circuit, and transmitter circuit and acceptor circuit can comprise a plurality of terminals of one that can be made as individually in initiate mode and the disabled status.

Semiconductor device can also comprise the control unit that is used for controlling jointly a plurality of communication modules.

In semiconductor device, in the acceptor circuit of communication module at least one can be the asynchronous receiver circuit, other acceptor circuit is the synchronous receiver circuit, and communication also can comprise the modulation circuit that is used for based on modulate the clock signal of supplying with to the synchronous receiver circuit from the signal of asynchronous receiver circuit with semiconductor chip.

According to embodiments of the invention, be provided for installing first district on the platysome of electronic unit and comprise second district that is used on the platysome of/a plurality of first communication units of being provided with from the mode to troop of the second substrate transmission and received signal.The input and output circuit corresponding with each first communication unit is set.

According to embodiments of the invention, assembling by opposed first surface with electronic unit form many to substrate, and in second substrate be set to a plurality of antennas of formation in three substrate adjacent of corresponding mutually position with second substrate.

According to embodiments of the invention, form second district in the substrate in the zone beyond first district that comprises electronic unit with the communication unit of trooping.

According to embodiments of the invention, substrate outside first is set in the substrate outside second, and outside first, on the precalculated position on substrate and the semiconductor device that outside first, is provided with in the substrate antenna is set.

According to embodiments of the invention, on the precalculated position on the first surface of substrate, chip is set, make two substrates paired, make that the first surface with chip is relative, and the assembling substrate is right, make coil be set on the corresponding position, and make the substrate moulding.

The semiconductor chip of installing in substrate according to an embodiment of the invention comprises a plurality of communication units that are set to two-way array.In communication unit, send signal via the antenna that constitutes by coil pattern from transmitter circuit, and by the signal of acceptor circuit reception from antenna.

According to embodiments of the invention, in substrate, the semiconductor chip that can implement intended function is set uses semiconductor chip with communicating by letter.Communication comprises a plurality of communication modules that have with the antenna that is made of coil pattern of the form setting of two-way array with semiconductor chip, and signal is sent out and receives via antenna.

Description of drawings

Fig. 1 is the cross-section side view of 3-D multi-chip according to an embodiment of the invention; And

Fig. 2 is the plane graph of the 3-D multi-chip shown in Fig. 1;

Fig. 3 is the plane graph that comprises the 3-D multi-chip of crossover bus switch (cross-bus switch);

Fig. 4 is the block diagram of the structure of crossover bus switch;

Fig. 5 is the plane graph that comprises the 3-D multi-chip of crossover bus switch and ternary controller;

Fig. 6 is the plane graph of metallic film;

Fig. 7 is the cross-section side view of 3-D multi-chip, and wherein metallic film and insertion plate are assembled;

Fig. 8 is the plane graph that is used to illustrate the relation between metallic film and the chip;

Fig. 9 is the cross-section side view of 3-D multi-chip, and wherein metallic film and insertion plate are assembled;

Figure 10 is the cross-section side view of 3-D multi-chip, wherein forms antenna on the insertion plate;

Figure 11 is the plane graph of the 3-D multi-chip shown in Figure 10;

Figure 12 is the perspective view that comprises the 3-D multi-chip of antenna;

Figure 13 is used to illustrate the transmission and the reception of antenna;

Figure 14 is the perspective view of the structure of device board;

Figure 15 is the flow chart that is used for the manufacture method of devices illustrated plate;

Figure 16 is the cross-section side view by the two-dimentional multicore sheet of the manufacturing of the method shown in Figure 15;

Figure 17 is the cross-section side view by the 3-D multi-chip of the manufacturing of the method shown in Figure 15;

Figure 18 is the cross-section side view by the semiconductor device of the manufacturing of the method shown in Figure 15;

Figure 19 is the flow chart that is used for the manufacture method of devices illustrated plate;

Figure 20 is the cross-section side view by the two-dimentional multicore sheet of the manufacturing of the method shown in Figure 19;

Figure 21 is the cross-section side view by the 3-D multi-chip of the manufacturing of the method shown in Figure 19;

Figure 22 is the cross-section side view by the semiconductor device of the manufacturing of the method shown in Figure 19;

Figure 23 is the cross-section side view of multicore sheet encapsulation according to an embodiment of the invention;

Figure 24 is the plane graph of the multicore sheet encapsulation shown in Figure 23;

Figure 25 is the cross-section side view of multicore sheet encapsulation according to an embodiment of the invention;

Figure 26 is the plane graph of the multicore sheet encapsulation shown in Figure 25;

Figure 27 is used to illustrate communication module;

Figure 28 is the plane graph that is used for the communication chip of asynchronous communication;

Figure 29 is the plane graph of the communication module shown in Figure 28;

Figure 30 is the block diagram that is used to send the communication module of asynchronous communication;

Figure 31 is the block diagram that is used to receive the communication module of asynchronous communication;

Figure 32 is the circuit diagram that is used to illustrate the structure of the transmitter circuit that is used for asynchronous communication;

Figure 33 is the oscillogram that is used to illustrate the action of the transmitter circuit shown in Figure 32;

Figure 34 is the circuit diagram that is used to illustrate the structure of the asynchronous receiver circuit that is used for asynchronous communication;

Figure 35 is the oscillogram that is used to illustrate the action of the transmitter circuit shown in Figure 34;

Figure 36 is the plane graph that is used for the communication chip of synchronous communication;

Figure 37 is the plane graph of the communication module shown in Figure 36;

Figure 38 is used to illustrate the block diagram of using the structure of communication module with the transmission of clock synchronization action;

Figure 39 is used to illustrate the block diagram of using the structure of communication module with the reception of clock synchronization action;

Figure 40 is the block diagram that is used to illustrate the structure of DLL circuit;

Figure 41 is the oscillogram that is used to illustrate the action of the DLL circuit shown in Figure 40;

Figure 42 is the circuit diagram that is used to illustrate with the structure of the transmitter circuit of clock synchronization action;

Figure 43 is the oscillogram that is used to illustrate the action of the transmitter circuit shown in Figure 42;

Figure 44 is the circuit diagram that is used to illustrate with the structure of the synchronous receiver circuit of clock synchronization action;

Figure 45 is the circuit diagram that is used to illustrate the structure of the clock synchronization amplifier shown in Figure 44;

Figure 46 is the cross-section side view that is illustrated in the structure of the multicore sheet encapsulation of installing in the wiring substrate; And

Figure 47 is the cross-section side view that is illustrated in another structure of the multicore sheet encapsulation of installing in the wiring substrate.

Embodiment

Below, with reference to the description of drawings various embodiments of the present invention.

Fig. 1 is the sectional drawing of 3-D multi-chip according to an embodiment of the invention.Fig. 2 is the plane graph of the 3-D multi-chip shown in Fig. 1.By successively stacked insertion plate 12-1 in the substrate 11 and insert plate 12-2 (below, when inserting plate 12-1 and insert plate 12-2 needn't distinguishing mutually the time, insert plate 12-1 and insert plate 12-2 be generically and collectively referred to as insert plate 12), form 3-D multi-chip 1.Substrate 11 has the surperficial 11A and the 11B on the plane that is parallel to each other substantially as broad ways.Surface 11B links to each other with other device (not shown in the accompanying drawing) via salient point 22-0.The insertion plate 12-1 that has as a plurality of through hole 21-1 of transmitting element is set on surperficial 11A.Insert surperficial 12-1A and 12-1B that plate 12-1 has the plane that is parallel to each other substantially as broad ways.On the salient point 22C-1 that is provided with on the surperficial 12-1B, chip 31-1 and 32-1 are being set.

On the surperficial 12-1B that inserts plate 12-1, be provided with and insert plate 12-2. and insert plate 12-2 and also have as the surperficial 12-2A and the 12-2B that are set to the plane that broad ways is parallel to each other substantially.On the salient point 22C-2 that is provided with on the surperficial 12-2B, chip 31-2 and 32-2 are set.

Therefore, in 3-D multi-chip 1, stack gradually insertion plate 12-1 and insertion plate 12-2, make surperficial 12-2A and surperficial 12-2B that chip is set face up as substrate according to present embodiment.

The edge that inserts the through hole 21-2 on the surperficial 12-2A of plate 12-2 is connected via the edge of the through hole 21-1 on the surperficial 12-2B of salient point 22A-2 and insertion plate 12-1.The edge that inserts the through hole 21-1 on the surperficial 12-1A of plate 12-1 is connected with prescribed route pattern (not shown in the accompanying drawing) on the surperficial 11A of substrate 11.

As shown in Figure 2, on the plane of each insertion plate 12, limit the zone 52 that the zone 51 of chip is set and forms a plurality of through holes 21 in the mode of trooping.In the present embodiment, zone 52 is positioned at the left side on the plane of respectively inserting plate 12.Fig. 2 illustrates 3 * 5 matrixes of through hole 21. still, do not limit the quantity of through hole 21.In zone 51, be provided as the chip 31 and 32 of the electronic unit that constitutes by integrated circuit (IC) or large scale integrated circuit (LSI).Do not limit the quantity of preparing to be installed in the chip in the zone 51.Can directly chip be embedded and insert in the plate 12.

Chip 31 and each terminal of 32 are connected via one in the circuit of wiring pattern 41 and the through hole 21 in the zone 52.

Insert localized area 51 and 52 in the plate 12 at each.Particularly, insert the through hole 21. that forms equal number on the same position of plate 12 in zone 52 with respect to each each remaining area that inserts on the plate 12 is defined as the zone 51 that chip is set.

By regulation zone 51 and 52 in through hole 21 and the same area in each insertion plate 12 is set in same position, can connect a plurality of insertion plates 12 reliably successively.

Though the quantity of the through hole 21 that in zone 52, forms without limits as mentioned above, but be provided with quantity at least with the through hole 21 of the quantity of the terminal of the chip of on 3-D multi-chip 1, installing (that is, must send independently with the signalling channel of received signal quantity) correspondence.For example, comprise ten terminals, need 40 passages so altogether as among fruit chip 31-1,31-2,32-1 and the 32-2 each.Thus, in zone 52, form at least four ten through holes 21.The inner surface of through hole 21 is formed by electric conducting material, makes to send signal between the edge of each through hole 21.

For example, to between the outside of the terminal of chip 31-2 and 3-D multi-chip 1, send and received signal, reserved passageway then, wherein, this passage comprise the salient point 22C-2 that is connected with the terminal of chip 31-2, the wiring pattern (not shown in the accompanying drawing) that on the insertion plate 12-2 that is connected with salient point 22C-2, forms, the through hole 21-2 that is connected with wiring pattern, the through hole 21-1 that forms on the insertion plate 12-1 that is connected with salient point 22A-2 with substrate 11 that salient point 22A-1 is connected on the wiring pattern (not shown in the accompanying drawing) that forms.

In the salient point 22A-2 that connects through hole 21-1 that inserts plate 12-1 and the through hole 21-2 that inserts plate 12-2, can ignore the salient point 22A-2 of the passage that comprises in each layer that is not used on the insertion plate 12-2 that sends signal to 3-D multi-chip 1 outside.Like this, can reduce the quantity of salient point 22A-2 to reduce manufacturing cost.But, also can be connected all through holes 21 that corresponding position forms, to help manufacturing via salient point 22A.

Can select untapped passage by crossover bus switch 61 described below, make, after the through hole of preparing to use 21 lost efficacy, can use another through hole 21 alternatively.Like this, can prevent the inefficacy of whole 3-D multi-chip 1.

Though all through holes 12 that form on the relevant position interconnect,, can pass through to use input and output circuit 110 below with reference to Fig. 5 explanation, insert plate 12 for each and select connection or disconnected.

Fig. 3 illustrates according to one in the insertion plate 12 of another embodiment.In the present embodiment, chip 31 is connected with crossover bus switch 61 via wiring pattern 41-1 with 32 terminal, and crossover bus switch 61 is connected with through hole 21 in the zone 52 via wiring pattern 41-2.In the present embodiment, crossover bus switch 61 is set in the zone 51.But crossover bus switch 61 also can be set in the zone 52.

Crossover bus switch 61 has the structure shown in Fig. 4. and in the present embodiment, wiring pattern line 41-1-1～41-1-m and chip 31 are connected with 32 predetermined terminal. and one in wiring pattern line 41-2-1～41-2-n and the through hole 21 is connected.

In Fig. 4, as shown in the figure, horizontal wiring pattern lines 41-2-1～41-2-n and vertical wirings pattern lines 41-2-1～41-2-n interconnect by the switch 82-1-1～82-n-m near the district intersection point.Switch 82-1-1～82-n-m is connected with trigger 81-1-1～81-n-m corresponding to switch 82-1-1～82-n-m.Connect trigger 81-1-1～81-n-m successively along the scan chain of representing by the dotted line in the accompanying drawing.Be set to logical value 1 or 0 along scan chain trigger 81-1-1～81-n-m successively.Connection is corresponding to the level and the vertical wirings pattern lines of the trigger that is set to logical value 1.For example,, open switch 82-(n-1)-2 so if trigger 81-(n-1)-2 is set to logical value 1, and connecting wiring pattern lines 41-2-(n-1) and 41-1-2.And, for example,, then close swap switch 82-n-m if trigger 81-n-m is set to logical value 0, and not connecting wiring pattern 42-2-n and 41-1-m.

Like this, by the crossover bus switch 61 and the corresponding switch of structure trigger,, also can change connection status by changing the setting of trigger even so after connecting.

On the other hand, for example, have the crossover bus switch 61 of the fuse read-only memory (ROM) of the fuse that between the contact point of level and vertical wirings pattern lines, inserts, can connect or disconnect predetermined pattern lines by structure.But, in this case, can only set up unalterable connection status or notconnect state.

As shown in Figure 4, if crossover bus switch 61 is made of trigger, so, for example, the intersection master controller that is made of nonvolatile memory also can be provided, be used to be stored as the logical value 0 and 1 that trigger is provided with, the pattern of trigger is set with the logical value 0 and 1 based on storage.

Fig. 5 illustrates another embodiment of the present invention.In the present embodiment, imput output circuit 110 is connected with through hole 21.On insertion plate 12, directly form this imput output circuit 110.According to each of the imput output circuit 110 of present embodiment comprise inverter 112 as input circuit, be used for output circuit inverter 111, be used for controlling output circuit enable inverter 113 and transistor 114.Ternary controller 101 is set on each zone 51.For example, if supply with logical values 1 from ternary controller 101 to the inverter 113 enabled of each through hole 21, inverter 11 is opened so, with the output signal from the inverse value of the logical value of chip 31 and 32 output signal outputs.When inverter 113 was enabled in logical value 0 input, the output of inverter 111 was always 0.

The logical value 0 or 1 that 112 conversions of the inverter that is used to import are supplied with from through hole 21, and opposite logical value sent to terminal corresponding to chip 31 and 32.

Like this, be connected to through hole 21 by imput output circuit 110, can prevent delay owing to the data transmission of the generation of the parasitic capacitance between the circuit with correspondence, and, what are no matter insert the quantity of plate 12, can stably insert transmission and received signal between the plate at each.

Also can use interface imput output circuit, as imput output circuit 110 such as stub series connection termination logic (SSTL) circuit or low-voltage differential signaling (LVDS) circuit.And, can chip 31 and 32 and through hole 21 between the precalculated position on the circuit that needs interface in the imput output circuit 110 is set, such as serial conversion circuit in parallel.

Fig. 6 illustrates according to the plane graph of the 3-D multi-chip of another embodiment and cross-section side view.In the present embodiment, setting and the corresponding conductive metal film 151-1～151-3 of insertion plate 12-1～12-3.As shown in Figure 7, inserting plate 12-1 engages with metallic film 151-1 by the salient point 22B-1 that puts between insertion plate 12-1 and metallic film 151-1.Chip 31-1 is connected with prescribed route pattern on the surperficial 12-1B that inserts plate 12-1.The opposite side of chip 31-1 is set to contact with metallic film 151-1.In the present embodiment, as shown in Figure 6, each metallic film 151 is made of four metallic film 151A～151D substantially.The rear side of chip 31 facing surfaces of the surface that is connected with substrate by the salient point of putting between surface and substrate (that is, with) contacts with metallic film 151A～151D.The part of the heat that produces in chip 31 is conducted by metallic film 151A～151D and is dispersed into the outside.In order to improve radiating efficiency, localized area, the outside 201 in zone 51.In zone 201, at the arranged outside metallic film 151A～151D that inserts plate 12.

Use identical structure for inserting plate 12-2 with 12-3.Particularly, insert plate 12-2 by engaging with thin metal layer 151-2 inserting the salient point 22B-2 that puts between plate 12-2 and the thin metal layer 151-2.Chip 31-2 is connected with insertion plate 12-2 via salient point 22C-2.The rear side of chip 31-2 contacts with thin metal layer 151-2.

Insert plate 12-3 by engaging with thin metal layer 151-3 inserting the salient point 22B-3 that puts between plate 12-3 and the thin metal layer 151-3.Chip 31-3 is connected with insertion plate 12-3 via salient point 22C-3.The rear side of chip 31-3 contacts with thin metal layer 151-3.

The end of the side of the surperficial 12-1B of the through hole 21-1 on the insertion plate 12-1 is connected with the surperficial 11B of substrate 11 via salient point 22A-1.The end of the side of the surperficial 12-1A of the through hole 21-1 on the insertion plate 12-1 is connected with the end of the side of the surperficial 12-2B that inserts plate 12-2 via salient point 22A-2.The end of the side of the surperficial 12-2A of the through hole 21-2 on the insertion plate 12-2 is connected with the end of the side of the surperficial 12-3B of the through hole 21-3 that inserts plate 12-3 via salient point 22A-3.

As shown in Figure 6, in zone 52, metallic film 151B is set, shields 161 to form between the salient point that surrounds each salient point 22.Like this, each salient point conductively-closed, and can prevent the leakage of the signal that sends and receive via salient point 22.

Metallic film 151 is not only as thermal radiator, also with the power supply that acts on from the outside to chip 31 and 32 feeds.Particularly, supply with the electric power of supplying with metallic film 151 from the outside to the wiring pattern that inserts plate 12 via salient point 22B.Thereby, via salient point 22C from wiring pattern to chip 31 supply capabilities.

Therefore, can shorten the line length that the power supply that forms is used wiring pattern on each insertion plate 12.

By on metallic film 151 chip being set, the whole thickness of semiconductor device increases.In order to prevent this point, can also not contact with the back of chip 31 that when chip 31 is set, makes shown in Figure 9 as Fig. 8 with metallic film 151.In the present embodiment, as shown in Figure 8, metallic film 151 be not set at the regional corresponding zone that chip 31 is set in.

Compare with the structure shown in Fig. 7 with Fig. 6, in this structure, heat conducting efficient reduces.But, since metallic film 151 be set at chip 31 near, therefore the part of the heat that is produced by chip 31 is left by metallic film 151.

Silicon often is used to constitute insertion plate 12.But, is difficult in the insertion plate of making by silicon and forms through hole, so manufacturing cost is higher.Therefore, for example, the antenna of trooping as communication unit can be set in zone 52 as shown in Figure 10 and Figure 11, make and not form transmission and received signal between the insertion plate of through hole.In the present embodiment, as shown in figure 10, in substrate 11, be provided with and insert plate 12-1, on insertion plate 12-1, be provided with and insert plate 12-2, and at last insertion plate 12-3 is set on insertion plate 12-2.On the surperficial 12-1B that inserts plate 12-1, salient point 22C-1 is set, and, on salient point 22C-1, chip 31-1 and 32-1 are set.Also on the surperficial 12-1B that inserts plate 12-1, form antenna 251-1.On the surperficial 12-2B of the insertion plate 12-2 that chip 31-2 and 32-2 are set, form antenna 251-2.On the surperficial 12-3B that inserts plate 12-3, form antenna 251-3.In the present embodiment, on insertion plate 12-3, chip is not set.

Via the closing line 211 that connects from substrate 11 to inserting plate 12-3 supply capability.Though not shown in the accompanying drawings, via closing line respectively to the surperficial 12-1B and the 12-2B feed that insert plate 12-1 and 12-2.

As shown in figure 11, each antenna 251 is connected with acceptor circuit 252 with transmitter.Antenna is by constituting at the coil wiring pattern that inserts setting on the plate 12.This transmitter and acceptor circuit 252 are embedded into and insert in the plate 12.Can form transmitter and acceptor circuit 252 in any in 52 in zone 51 or zone.Be controlled at transmitter and the acceptor circuit 252 that is provided with on the identical insertion plate 12 by transmitter and receiver controller 102.

Figure 12 illustrates the reduced graph of the lamination that inserts plate 12-1 and 12-2.In the present embodiment, the surperficial 12-2B of insertion plate 12-2 is connected with 32-2 with chip 31-2 via salient point. on surperficial 12-2B, receiver element 301, transmitter and receiver controller 241-2 and crossover bus switch 61-2 are set.In regional 52-2, the antenna 251-2 (matrix of 2 * 4 antennas shown in the figure) that troops is set.

The insertion plate 12-1 that is provided with below inserting plate 12-2 also has and inserts the identical structure of plate 12-2.

Implement radio communication (electromagnetic induction) between the antenna 251-2 among the regional 52-2 of the insertion plate 12-2 that antenna 251-1 in the regional 52-1 that inserts plate 12-1 and position are corresponding with antenna 251-1.

In other words, as shown in figure 13, each antenna 251 is made of transmitting antenna 251T and reception antenna 251R.The end of transmitting antenna 251T is connected with 353 with NAND (with non-) circuit 352.The input terminal of the input terminal of NAND circuit 352 and NAND circuit 353 links to each other and further is connected with transmission and reception controller 241-2.Another input terminal of NAND circuit 353 directly is connected with transmission and reception controller 241-2, but another input terminal of NAND circuit 352 is connected via the another terminal of inverter 351 with NAND circuit 353.

When transmission and reception controller 241-2 with one in shared input of logical value 1 input NAND circuit 352 and 353, and during with another input terminal of logical value 0 input NAND circuit 353, logical value 1 is by another input terminal via inverter 351 input NAND circuit 352.As a result, the output of NAND circuit 353 and NAND circuit 352 is respectively logical value 1 and 0.As a result, apply electric current from NAND circuit 353 to NAND circuit 352 to antenna 251T.This state is opposite corresponding to logical value 1., when with one in shared input of logical value 0 input NAND circuit 352 and 353, and during with another input terminal of logical value 1 input NAND circuit 353, logical value 0 is by another input terminal via inverter 351 input NAND circuit 352.As a result, in this case, because the output of NAND circuit 353 is logical values 0, and the output of NAND circuit 352 is logical values 1, therefore, applies electric current from NAND circuit 352 to NAND circuit 353 to antenna 251T.This state is corresponding to logical value 0.

When as mentioned above when antenna 251T applies electric current, received by the reception antenna 251R that another inserts plate 12 as the resultant magnetic flux of electric current.When antenna 251R detects the variation of magnetic flux, detect the electric power corresponding and it is outputed to crossover bus switch 61-2 with this variation by sensor amplifier 361.

As mentioned above, the antenna by the position in correspondence is provided with sends and received signal between different insertion plates.

Though not shown in the accompanying drawing, the aforesaid 3-D multi-chip that constitutes by the lamination that inserts plate by resin forming to make semiconductor device.Like this, for example, make SIP and multi-chip module (MCM).

Figure 14 illustrates the device board according to an embodiment of the invention 400 that comprises the SIP that makes as mentioned above.Device board 400 is made of the substrate 401 that wave point substrate 411-1～411-3 is set at preposition.Among wave point substrate 411-1～411-3 each comprises a plurality of antennas 251.On wave point substrate 411-1～411-3, SIP412-1～412-3 is installed respectively.Also in the substrate on the most approaching surface at SIP412-1～412-3 that correspondence position is connected with wave point substrate 411-1～411-3, antenna 251 is set.Like this, owing between the antenna of correspondence, implement communication, therefore, can make SIP412-1～412-3 at an easy rate by on the precalculated position on wave point substrate 411-1～411-3, being provided with and engaging SIP412-1～412-3.

In the device board of making as mentioned above 400, embed various electronic units.

Below, with reference to the manufacture method of the flowchart text device board shown in Figure 15.Make the device board shown in Figure 16～Figure 18 by this method with SIP.

In step S1, on the insertion plate, form the pattern that comprises antenna.For example, as shown in figure 16, on the surperficial 12B that inserts plate 12, form the wiring pattern that comprises antenna 251.Each antenna 251 comprises transmitter and acceptor circuit 252.Also form crossover bus switch 61 and transmission and reception controller 102.

In step S2, salient point and chip are set on preposition.As shown in figure 16, chip 31 is connected with prescribed route pattern on the surperficial 12B that inserts plate 12 via salient point 22C.On the precalculated position on the surperficial 12B, be provided for the salient point 22B of jointing metal film 151.Like this, make two-dimentional multicore sheet 501.

By implementing identical technology, form a plurality of two-dimentional multicore sheets 501.

Then, in step S3, two two-dimentional multicore sheets 501 are put together, make that the surface of chip 31 with two-dimentional multicore sheet 501 is opposed mutually with metallic film 151.In other words, as shown in figure 17, on the insertion plate 12-1 that is connected with chip 31-1 via salient point 22C-1, being connected with metallic film 151 via salient point 22B-1. the insertion plate 12-2 that is connected with chip 31-2 via salient point 22C-2 is connected with metallic film 151 via salient point 22B-2. and the rear side of chip 31-1 and 31-3 contacts with metallic film 151.To insert plate 12-1 and 12-2 and put together, make that surperficial 12-1B and 12-2B with chip 31-1 and 31-2 are opposed mutually.Then, Yu Ding wiring pattern is connected with 12-2 with insertion plate 12-1 via the diameter salient point 22A bigger than salient point 22B.Like this, make 3-D multi-chip 511.

As mentioned above, make a plurality of 3-D multi-chips 511 by two two-dimentional multicore sheets 501 are put together and made.

Then, in step S4, at least two 3-D multi-chips 511 are put together, make that the position of antenna is corresponding mutually.Then, in step S5, outside current feed terminal is connected to metallic film and makes its moulding.Figure 18 illustrates the exemplary configurations of making as mentioned above as the SIP of semiconductor device.According to this structure, be brought together and by resin 551 moulding, to make semiconductor device 531 (SIP412) by the 3-D multi-chip 511-1 that constitutes that inserts plate 12-1-1 and 12-2-1 with by the 3-D multi-chip 511-2 that constitutes that inserts plate 12-1-2 and 12-2-2.

Chip 31-1-1 is connected with the surperficial 12-1-1B that inserts plate 12-1-1 via salient point 22C-1-1.The rear side of chip 31-1-1 contacts with metallic film 151-1.Metallic film 151-1 is connected with the surperficial 12-1-1B that inserts plate 12-1-1 via salient point 22B-1-1.

Chip 31-2-1 is connected with the surperficial 12-2-1B that inserts plate 12-2-1 via salient point 22C-2-1.The rear side of chip 31-2-1 contacts with metallic film 151-1.Metallic film 151-1 is connected with insertion plate 12-2-1 via salient point 22B-2-1.Connect prescribed route pattern that inserts plate 12-1-1 and the prescribed route pattern that inserts plate 12-2-1 via salient point 22A-1.

Chip 31-1-2 is connected with the surperficial 12-1-2B that inserts plate 12-1-2 via salient point 22C-1-2.The rear side of chip 31-1-2 is connected with metallic film 151-2.Metallic film 151-2 is connected with insertion plate 12-1-2 via salient point 22B-1-2.Chip 31-2-2 is connected with insertion plate 12-2-2 via salient point 22C-2-2.The rear side of chip 31-2-2 is connected with metallic film 151-2.Metallic film 151-2 is connected with insertion plate 12-2-2 via salient point 22B-2-2.Connect prescribed route pattern that inserts plate 12-1-2 and the prescribed route pattern that inserts plate 12-2-2 via salient point 22A-2.

To insert plate 12-1-1 and 12-2-1 and put together, make that respectively the surperficial 12-1-1B and the 12-2-1B that are connected with 31-2-1 with chip 31-1-1 are opposed mutually.Similarly, will insert plate 12-1-2 and 12-2-2 and put together, make that respectively the surperficial 12-2-1B and the 12-2-2B that are connected with 31-2-2 with chip 31-1-2 are opposed mutually.

As a result, when 3-D multi-chip 511-1 and 511-2 are put together, be separated with the distance corresponding respectively inserting the antenna 251-2-1 that forms on the plate 12-2-1 and inserting the antenna 251-1-2 that forms on the plate 12-1-2 with inserting plate 12-2-1 and 12-1-2.As a result, for example, with the surperficial 12-1B that will comprise chip as shown in figure 12 and 12-2B to compare towards the stacked situation of the mode of equidirectional (among Figure 12 for upwards), can increase the distance between antenna 251-2-1 and the 251-1-2.Therefore, can between antenna, set up communication reliably.

Metallic film 151-1 interconnects with 151-2 and is connected with the outside current feed terminal 552 of drawing from resin 551.

In step S6, the wave point substrate is set in the substrate of device board.Particularly, as shown in figure 14, wave point substrate 411～411-3 is set in substrate 401.More specifically, as shown in figure 18, wave point substrate 411 is connected with the surperficial 401B of substrate 411 via salient point 22A-0.On the surperficial 411B of wave point substrate 411, form antenna 251-0.In step S7, to join to by the semiconductor device of resin 511 moulding in the wave point substrate 411, make antenna 251-0 relative with the antenna 251-1-1 that is provided with on insertion plate 12-1-1, this insertion plate 12-1-1 is the outmost insertion plate of wave point substrate 411 1 sides in the insertion plate by resin 511 moulding.

In step S8, outside current feed terminal is connected with substrate on the device board.Particularly, outside current feed terminal 552 is connected with predetermined feed pattern in the substrate 401.As a result, the electric power of supplying with substrate 401 is supplied with thin metal layer 151-1 and 151-2 from outside current feed terminal 552 via the pattern in the substrate 401.Thereby, supply with the electric power of thin metal layer 151-1 and supply with the feed pattern that inserts plate 12-1-1, and further supply with chip 31-1-1 via salient point 22C-1-1 via salient point 22B-1-1.Supply with the electric power of thin metal layer 151-1 and also supply with the feed pattern that inserts plate 12-2-1, and further supply with chip 31-2-1 via salient point 22C-2-1 via salient point 22B-2-1.

Electric power also is fed into chip 31-1-2 and the 31-2-2 that installs on plate 12-1-2 and the 12-2-2 inserting respectively.

The salient point 22A that is connected with antenna 251 can guide inputing or outputing of the predetermined terminal of inserting the chip on the plate separately.For example, the output from the predetermined lead-out terminal that inserts the chip 31-1-1 on the plate 12-1-1 is fed into the corresponding wiring line pattern that inserts on the plate 12-1-1 via the salient point 22C-1-1 that is connected with lead-out terminal.Then, this output is wirelessly transmitted to antenna 251-0 in the wave point substrate 411 from antenna 251-1-1.Then, will export from the wiring pattern that is connected with antenna 251-0 in the wave point substrate 411 via salient point 22A-0 and send to wiring pattern in the substrate 401.

On the other hand, when signal was input to the predetermined input terminal of chip 31-1-1 from the outside, this signal was fed into wiring pattern in the wave point substrate 411 via salient point 22A-0 from the predetermined pattern in the substrate 401.This signal is fed into the antenna 251-0 that is connected with wiring pattern via wiring pattern.This signal is wirelessly sent to corresponding antenna 251-1-1.Then, via the wiring pattern that inserts plate 12-1-1 this signal is supplied with the input terminal of the chip 31-1-1 that is connected with salient point 22C-1-1 from salient point 22C-1-1.

For received signal, reserve antenna, salient point, wiring pattern, to form designated lane.

Similarly, when via salient point 22C-2-2 from outside the predetermined lead-out terminal that inserts the chip 31-2-2 that plate 12-2-2 is connected is guided to signal the time, salient point 22C-2-2 by being connected successively with lead-out terminal, insert the wiring pattern of plate 12-2-2, salient point 22A-2, insert the wiring pattern of plate 12-1-2, insert the antenna 251-1-2 of plate 12-1-2, insert the antenna 251-2 of plate 12-2-1, insert the wiring pattern of plate 12-2-1, salient point 22A-1, insert the wiring pattern of plate 12-1-1, insert the antenna 251-1-1 of plate 12-1-1, antenna 251-0 in the wave point substrate 411, wiring pattern in the wave point substrate 411, wiring pattern in the substrate 401 of salient point 22A-0 and device board 400 sends signal.

Reserve salient point, wiring pattern and antenna, to be formed for sending the designated lane of signal.Though ignore detailed explanation here, reserve antenna, wiring pattern and salient point similarly to form the designated lane that signal is input to the input terminal of chip 31-2-2.

The manufacture method of above-mentioned steps S1～S8 constitution equipment plate.Step S1～S5 also constitutes the manufacture method of semiconductor device.

Because the semiconductor device shown in Figure 16～18 uses a large amount of salient points, therefore, the thickness of device can attenuation, but compares with the manufacturing cost of the semiconductor device that uses closing line, and manufacturing cost increases.Below, using by in some parts, using closing line to make the manufacture method of the device board of the semiconductor device that manufacturing cost reduces with reference to the flowchart text shown in Figure 19. the semiconductor device of making in this technology has and the identical structure of structure shown in Figure 20～22.

In step S31, form the pattern that comprises antenna on the plate inserting. in step S32, chip is set on preposition, has the insertion plate and the dividing plate of via hole, and, then, connect preposition with closing line.In step S33, plate will be inserted and thin metal layer is put together.Like this, as shown in figure 20, inserting formation antenna 251 and wiring pattern on the plate 12S.Inserting plate 12S can be made of silicon.Like this, can obtain stable properties.

On the surperficial 12SB that inserts plate 12S, chip 31. is set can embed chip 31 among the insertion plate 12S in advance.The predetermined terminal of chip 31 is connected with prescribed route pattern on inserting plate 12S via closing line 612.Prepare another and insert plate 12X.Inserting plate 12X is made of the material beyond the silicon that wherein can form through hole at an easy rate.For example, inserting plate 12X can be made of glass epoxy resin, polyimide resin or phenolic resins.

Have as the insertion plate 12X of the via hole 21V of one type through hole via salient point 22C with insert plate 12S and be connected.To insert plate 12S and metallic film 151 is put together.Metallic film 151 is connected with predetermined feed wiring pattern on inserting plate 12S via closing line 612. what insert plate 12S dividing plate 611 is set on every side.Like this, make two-dimentional multicore sheet 601.

In step S34, by opposed have chip the surface and via salient point connecting path hole, two two-dimentional multicore sheets are put together.Like this, as shown in figure 21, make 3-D multi-chip 621.This 3-D multi-chip 621 is made by two-dimentional multicore sheet 601-1 and 601-2 are put together.In two-dimentional multicore sheet 601-1, chip 31-1 is installed, and the terminal of chip 31-1 is connected with prescribed route pattern on the surperficial 12S-1B via closing line 612-1 on the surperficial 12S-1B that inserts plate 12S-1.The prescribed route pattern of surface on the 12S-1B is connected with via hole 21V-1 on the insertion plate 12X-1 via salient point 22C-1.On the surperficial 12S-1B that inserts plate 12S-1, form antenna 251-1.Insert plate 12S-1 around, dividing plate 611-1 is set and will inserts plate 12S-1 and metallic film 151-1 puts together.

Two dimension multicore sheet 601-2 comprises insertion plate 12S-2.On the surperficial 12S-2B that inserts plate 12S-2, chip 31-2 is set.The predetermined terminal of chip 32-2 is connected with wiring pattern on the surperficial 12S-2B via closing line 612-2.On the precalculated position on the surperficial 12S-2B, form antenna via closing line 612-2.Prescribed route pattern on the 12S-2B of surface is connected with the via hole 21V-2 that inserts plate 12X-2 via salient point 22C-2.To insert plate 12S-2 and metallic film 152-2 puts together.Around insertion plate 12S-2, dividing plate 611-2 is set.Connect dividing plate 611-2 and 611-2 by salient point 22B.Connect via hole 21V-1 that inserts plate 12X-1 and the via hole 21V-2 that inserts plate 12X-2 via salient point 22C-2.

In step S35, at least two 3-D multi-chips are put together, make antenna corresponding mutually.In step S36, outside current feed terminal is connected to metallic film and makes its moulding.In other words, metallic film 151-1-1～151-2-2 interconnects and is connected with outside current feed terminal 552 then.Like this, as shown in figure 22, make semiconductor 681 (SIP412).

This semiconductor 681 is by with 3-D multi-chip 621-1 with 621-2 puts together and with resin their moulding are made.

In this case, the distance between the antenna 251-1-2 of the insertion plate 12S-3 of the antenna 251-2-1 of the insertion plate 12S-2 of 3-D multi-chip 621-1 and 3-D multi-chip 621-1 is also by the thickness decision of inserting plate 12S-2 and 12S-3.Therefore, and compare by the semi-conductive thickness of making towards the stacked a plurality of two-dimentional multicore sheets 601 shown in Figure 20 of unidirectional mode with surperficial 12SB, semi-conductive thickness can attenuation.As a result, can between antenna, be communicated by letter reliably.

By after making semiconductor device 681 according to the manufacture method of the semiconductor device of step S31～S36, in step S37, the wave point substrate is set in the substrate of device board.In step S38, in the wave point substrate, semiconductor device is set.In step S39, current feed terminal is connected with the substrate of device board.

Because the technology of step S37～S39 is identical with the step S6～S8 of the flow chart shown in Figure 15, so ignores and be described.

In semiconductor device 681, for example, predetermined feed pattern from substrate 401, outside current feed terminal 552, metallic film 151-2-2, closing line 612-2-2, insert prescribed route pattern on the plate 12S-4, closing line 612-2-2 current feed terminal, successively electric power is supplied with chip 31-2-2 to chip 31-2-2.

For example, the terminal of chip 31-2-2 and the receive path between the outside by from the terminal of chip 31-2-2 to closing line 612-2-2, insert the wiring pattern of plate 12S-4, salient point 22C-2-2, insert the via hole 21V-2-2 of plate 12X-2-2, salient point 22C-3-2, insert the via hole 21V-1-2 of plate 12X-1-2, salient point 22C-1-2, insert the wiring pattern of plate 12S-3, antenna 251-1-2, antenna 251-2-1, insert the wiring pattern of plate 12S-2, salient point 22C-2-1, insert the via hole 21V-2-1 of plate 12X-2-1, salient point 22C-3-1, insert the via hole 21V-1-1 of plate 12X-1-1, salient point 22C-1-1, insert the wiring pattern of plate 12S-1, antenna 251-1-1 and antenna 251-0, the wiring pattern of wave point substrate 411, salient point 22A-0, constitute to the path that the wiring pattern of substrate 401 forms successively at last.

In each embodiment, do not implement the order of each step in the method for limiting.Can be successively or implement these steps simultaneously, perhaps can implement each step individually.

As mentioned above, on insertion plate, form antenna as substrate.But, can form antenna on the semiconductor chip, and on the insertion plate, these semiconductor chips are set then, to set up the communication of inserting between the plate.Figure 23 and Figure 24 illustrate the semiconductor device with this structure.

Comprise that as the multicore sheet of semiconductor device encapsulation 1001 the insertion plate 1011-1, the 1011-2 that are made of silicon and 1011-3. on nethermost insertion plate 1011-1, connect as communication chip 1015-1 and the communication chip 1016 of communication with semiconductor chip via salient point 1014-1.Though do not illustrate in the accompanying drawings, communication chip 1015-1 and communication chip 1016 can be by inserting the wiring pattern received signal that forms on the plate 1011-1.Insert plate 1011-1 and receive required electric power from power supply 1017 via closing line 1018-1.

Inserting plate 1011-2 is connected with 1013-2 with functional chip 1012-2 with communication chip 1015-2 via salient point 1014-2.Can be by using the wiring pattern that forms on the plate 1011-2 inserting, to/each transmission and received signal from communication chip 1015-2 and functional chip 1012-2 and 1013-2.From power supply 1017 required electric power is supplied with insertion plate 1011-2 via closing line 1018-2.

Inserting plate 1011-3 is connected with 1013-3 with functional chip 1012-3 with 1015-3 via salient point 1014-3. the wiring pattern that can on insertion plate 1011-3, form by use, to/each transmission and received signal from communication chip 1015-3 and functional chip 1012-2 and 1013-3.From power supply 1017 required electric power is supplied with insertion plate 1011-3 via closing line 1018-3.

Functional chip 1012-2,1012-3,1013-2 and 1013-3 for example are the semiconductor chips such as CPU and memory that can implement intended function.

Figure 25 and Figure 26 illustrate the semiconductor device according to another embodiment. in this embodiment, from power supply 1017 required electric power is supplied with copper coin 1032-1 via salient point 1014-1.Via salient point 1014-1 this electric power is supplied with insertion plate 1011-1.

The copper coin 1032-2 that electric power is supplied with on the copper coin 1032-1 from power supply 1017 via salient point 1031-1, copper coin 1032-1 and salient point 1031-2.Via salient point 1014-2 this electric power is supplied with insertion plate 1011-2.Similarly, the copper coin 1032-3 that electric power is supplied with on the copper coin 1032-3 from power supply 1017 via salient point 1031-1, copper coin 1032-1, salient point 1031-2 and copper coin 1032-2.Via salient point 1014-3 this electric power is supplied with insertion plate 1011-3.Other structure is identical with the structure shown in Figure 23 and Figure 24.

In copper coin 1032-1, form a plurality of holes in the position corresponding with communication chip 1015-1 and 1016, make copper coin 1032-1 directly not contact with 1016 with communication chip 1015-1.Similarly, on copper coin 1032-2, form a plurality of holes in the position corresponding with communication chip 1015-2 and functional chip 1012-2 and 1013-2, and, on copper coin 1032-3, form a plurality of holes in the position corresponding with communication chip 1015-3 and functional chip 1012-3 and 1013-3.

Communication chip 1015-1,1015-2 shown in Figure 23 and Figure 25 and 1015-3 be vertical arrangement in the accompanying drawings.Therefore, as shown in figure 27, communication chip 1015-2, the communication module 1052-2 that forms and the communication module 1052-3 that inserts on plate 1011-2, the insertion plate 1011-3 is being set on the corresponding mutually position on communication chip 1015-3.Each member is radio communication (electromagnetic induction of minimum distance communication) mutually.

Figure 28 is the plane graph that is used for the communication chip 1015 of asynchronous communication.In this embodiment, as shown in drawings, a plurality of pads 1051 are set to form square shape along the periphery of communication chip 1015.Pad 1051 comprises inputoutput buffer.Via closing line or salient point connection pads 1051.Pad 1051 is connected with communication module 1052 via wiring pattern.

According to present embodiment, in the inboard of pad 1051, with 3 * 5 two-way arrays 15 communication module 1052. each communication modules 1052 are set altogether and are numbered and 01～15. control unit 1053. control units 1053 control communication modules 1052 are set on the lower part of communication module 1052, produce reference voltage and this reference voltage is supplied with communication module 1052.

Figure 29 is one a plane graph in the communication module 1052.As shown in figure 29, in leftmost zone, sending device circuit 1073 is set,, asynchronous receiver circuit 1074 is set,, antenna 1077 is set on the right of asynchronous receiver circuit 1074 on the right of sending device circuit 1073.Along transmitter circuit 1073, asynchronous receiver circuit 1074 and antenna 1077 wiring 1070 is set.This wiring 1070 receives electric power and signal.

15 communication modules 1052 in the communication chip 1015 or all be used for sending, or all be used for receiving (, need to send with communication chip simultaneously and receive and use communication chip) in order to implement two-way communication.As an alternative, the part in 15 communication modules 1052 can be used for sending, and all the other are used for receiving.

As shown in figure 30, each in the communication module 1052 comprises data terminal 1071, amplifier 1072, transmitter circuit 1073, asynchronous receiver circuit 1074, amplifier 1075, lead-out terminal 1076 and antenna 1077 substantially.Data terminal (DATA) 1071 will be imported data and supply with amplifier 1072.Amplifier 1072 amplifies from the signal of data terminal 1071 inputs in the future, and amplifying signal is sent to the data terminal (DATA) of transmitter circuit 1073.The lead-out terminal N1 of transmitter circuit 1073 is connected with N4 with the input terminal N3 of asynchronous receiver circuit 1074 respectively with N2, wherein inserts antenna 1077 between transmitter circuit 1073 and asynchronous receiver circuit 1074.Asynchronous receiver circuit 1074 goes out the signal of (OUT) output from input terminal N3 and N4 transmission from input terminal.This output is exaggerated device 1075 amplifications and exports from lead-out terminal (OUT) 1076.

Transmitter circuit 1073 comprises enables terminal EN.When enabling terminal EN and apply high reference voltage V DD, transmitter circuit 1073 is activated, when applying low reference voltage V SS, transmitter circuit is disabled. similarly, when when enabling terminal EN and apply high reference voltage V DD, asynchronous receiver circuit 1074 is activated, and when applying low reference voltage ground VSS, asynchronous receiver circuit 1074 is disabled.The communication module 1052 according to present embodiment shown in Figure 30 is to send to use communication module.Therefore, transmitter circuit 1073 is activated, and asynchronous receiver circuit 1074 is disabled.

In this case, the signal of importing from data terminal 1071 is exaggerated amplifier 1072, and is imported into transmitter circuit 1073 then.1073 pairs of input signals of transmitter circuit carry out waveform shaping, and the signal behind antenna 1077 output Shapings.

Figure 31 illustrates one the structure that sends with in the communication module in the communication chip 1015.In Figure 31 (with the Figure 39 that the following describes), the numeral 01～15 of the communication module shown in numeral Figure 28 (Figure 36) of the hyphen back that comprises in the Reference numeral.In the present embodiment, discuss with Figure 28 in the centre illustrate and by the communication module of Reference numeral 08 expression corresponding communication module 1052-08 and with Figure 28 in communication module communication module 1052-01 corresponding and that represent by Reference numeral 01.Low reference voltage V SS is supplied with the terminal of enabling of transmitter circuit 1073-08 and 1073-01.Therefore, transmitter circuit 1073-08 and 1073-01 are disabled.

High reference voltage V DD is supplied with communication module 1052-08 asynchronous receiver circuit 1074-08 enable terminal, to enable asynchronous receiver circuit 1074-08.As a result, asynchronous receiver circuit 1074-08 receives the signal that is received by antenna 1077-08 on input terminal N3 and N4, and goes out (OUT) from terminal signal is outputed to amplifier 1075-08.Amplifier 1075-08 amplification input signal also outputs to terminal 1076-08 with amplifying signal.

Similarly, high reference voltage V DD is supplied with communication module 1052-01 asynchronous receiver circuit 1074-01 enable terminal, to enable asynchronous receiver circuit 1074-08.As a result, asynchronous receiver circuit 1074-01 receives the signal that is received by antenna 1077-01 on input terminal N3 and N4, and goes out (OUT) from terminal signal is outputed to amplifier 1075-01.Amplifier 1075-01 amplification input signal also outputs to terminal 1076-01 with amplifying signal.

Controller unit 1053 is supplied with reference voltage V R1 and VR2 to asynchronous receiver circuit 1074-08 and 1074-01 respectively.As following with reference to Figure 34 described, in asynchronous receiver circuit 1074-08 and 1074-01, detect positive pulse and negative pulse, wherein, reference voltage V R1 and VR2 are threshold values.

Figure 32 is the detail drawing of transmitter circuit 1073.Detect the transformation of the signal of the data terminal that is input to transmitter circuit 1073 by transition detection unit 1111.When detecting transformation, transition detection unit 1111 produces positive pulses, and this positive pulse is outputed to node N0.The positive pulse that sends to node N0 is imported into NAND circuit 1112.Another input of NAND circuit 1112 receives from enabling the high reference voltage V DD of terminal feeding.The output of NAND circuit 1112 is connected with node N5.Node N5 also is connected with 1117 control electrode with tristate buffer 1116.To supply with other Control Node of tristate buffer 1116 and 1117 by the output from NAND circuit 1112 (output of node N6) of inverter 1113 inversions.

Tristate buffer 1116 is received in the signal that data terminal sends from inverter 1114 and 1115.Tristate buffer 1117 receives the output of inverter 1114.To send to the two ends that send with antenna 1077T from lead-out terminal N1 and N2 from the output of tristate buffer 1116 and 1117.Lead-out terminal N1 is connected with transistor 1118 with N2, and is connected with 1120 series circuit with transistor 1119.The control electrode of transistor 1118,1119,1120 is connected with node N5.Transistor 1119 is connected with reference voltage HVD with 1120 tie point.The voltage of reference voltage HVD for example is half of voltage of high reference voltage V DD.

For example, when will the signal shown in Figure 33 A being input to data terminal, transition detection unit 1111 detect among Figure 33 B the rising edge and the trailing edge of signal, and positive pulse outputed to node N0.Shown in Figure 33 C, the positive pulse that sends to node N0 is by 1112 inversions of NAND circuit, and is output to node N5 as negative pulse.The negative pulse that sends to node N5 is output to node 6 by inverter 1113 inversions and as positive pulse.Therefore, in the timing of supplying with negative pulse and positive pulse respectively to node 5 and 6, tristate buffer 1116 and 1117 is activated, and, be sent to antenna 1077T via the signal of inverter 1114 and 1115 inputs or the signal of importing via inverter 1114.As a result, shown in Figure 33 D, electric current is applied on the antenna 1077T.When the voltage of node N5 hanged down, transistor 118～1120 was switched off, and with permission electric current is applied on the antenna 1077T.When the signal that is input to data terminal was in high level and low level, the electric current I LT that is applied on the antenna 1077T flowed along opposite direction.

The antenna 1077T that sends with communication module 1052 is connected with the antenna 1077R that receives with communication module 1052 by coupling factor K.Therefore, when electric current I LT was supplied with antenna 1077T, electric current was applied on the antenna 1077R, and shown in Figure 33 E, produced voltage on the input terminal N3 of acceptor circuit 1074 and N4.Shown in Figure 33 D and Figure 33 E, shown in the solid line among Figure 33 E, produce with antenna 1077T on the corresponding voltage of rising edge of electric current I LT, and, shown in the dotted line among Figure 33 E, the corresponding voltage of trailing edge of the electric current I LT on generation and the antenna 1077T.

Figure 34 illustrates the structure of asynchronous receiver circuit 1074.Input terminal N3 is connected with the input terminal of amplifier 1143 with N4.Transistor 1141 and 1142 is connected between input terminal N3 and the N4.Between transistor 1141 and 1142, supply with reference voltage V REF.Non-inverter input of hysteresis comparator 1144 and inverter input of hysteresis comparator 1146 are supplied with in the output of amplifier 1143.Reference voltage V R1 is supplied with inverter input of hysteresis comparator 1146, and reference voltage V R2 is supplied with non-inverter input of hysteresis comparator 1144.

The output of comparator 1144 (node N5) is connected via one in the input of inverter 1145 and NAND circuit 1148, and this NAND circuit 1148 constitutes with NAND circuit 1149 and intersects latch circuits.The output of comparator 1146 (node N6) is connected via one in the input of inverter 1147 and NAND circuit 1149.The output of NAND circuit 1148 is connected with another input of NAND circuit 1149, and the output of NAND circuit 1149 is connected with another input of NAND circuit 1148.

When from transmitter side transmission signal (Figure 35 A), because electromagnetic induction is gone up generation voltage (Figure 35 B) at antenna 1077 (input terminal N3 and N4).Amplifier 1143 amplifies from the signal of antenna 1077 inputs and this amplifying signal is outputed to node VA (Figure 35 C).Comparator 1144 will be compared with reference voltage V R1 from the signal that amplifier 1143 sends, and, if reference voltage V R1 is bigger, then to node N5 output positive pulse (Figure 35 D).Similarly, comparator 1146 will be compared with reference voltage V R2 from the signal that amplifier 1143 sends, and, if reference voltage V R2 is less, then to node N6 output positive pulse (Figure 35 E)., and intersected latch circuit and pin respectively by inverter 1145 and 1147 inversions from the output of node N5 and N6, this intersection latch circuit will exported inversion (Figure 35 F) when negative pulse is transfused to.

When implementing communication, use all structures as shown in figure 36 with communication chip 1015 with synchronous clock.Basic structure is identical with basic structure shown in Figure 28.But, in the embodiment shown in Figure 36, delay locked loop (DLL) circuit 1161 is added in this structure.In the communication module 1052 by Reference numeral 01～15 expression, at least one for example by Reference numeral 08 expression that, can be implemented asynchronous communication, and can implement synchronous communication by other communication module of Reference numeral 01～07 and 09～15 expression.

Figure 37 is the plane graph that can implement one (that is, by one in the communication module 1052 of Reference numeral 01～07 and 09～15 expression) in the communication module 1052 shown in Figure 36 of synchronous communication (can implement the plane graph by the communication module 1152 of Reference numeral 08 expression of asynchronous communication shown in Figure 29).As shown in figure 37, the communication module 1052 that can implement synchronous communication comprises transmitter circuit 1183, synchronous receiver circuit 1184, antenna 1187 and wiring.The plane of communication module 1052 that can implement synchronous communication is identical with plane graph among Figure 29, and just asynchronous receiver circuit 1074 is replaced by synchronous receiver circuit 1184.

As shown in figure 38, synchronous communication for example comprises data terminal 1181, amplifier 1182, transmitter circuit 1183, synchronous receiver circuit 1184, amplifier 1185, lead-out terminal 1186 and antenna 1187 (asynchronous communication by Reference numeral 08 expression has the structure identical with structure shown in Figure 30 with communication module 1052) with communication module 1052.The basic structure of the communication module 1052 shown in Figure 38 and the asynchronous communication shown in Figure 30 are basic identical with communication module 1052, just transmitter circuit 1183 and synchronous receiver circuit 1184 have clock (CLK) terminal, and with the input clock signal synchronization action.Other structure is identical with the structure shown in Figure 30.

Figure 38 illustrates the transmission communication module according to present embodiment.Therefore, enable terminal EN owing to low-voltage VSS is fed into, so the synchronous receiver circuit 1184 shown in Figure 38 is disabled.Because high voltage VDD is fed into and enables terminal EN, so transmitter 1183 is activated.

Figure 39 illustrates the reception that can implement synchronous communication with being connected substantially between the communication module 1052-08 of the communication module 1052 of communication chip 1015 and the communication module 1052-01.Low-voltage VSS be fed into the transmitter circuit 1183-08 of communication module 1052-08 and communication module 1052-01 transmitter circuit 1183-01 enable terminal, the result, transmitter circuit 1183-08 and 1183-01 are disabled.On the contrary, high voltage VDD is fed into the terminal of enabling of asynchronous receiver circuit 1184-08 and synchronous receiver circuit 1184-01, the result, and asynchronous receiver circuit 1184-08 and 1184-01 are activated.

Therefore, the signal that is received by antenna 1187-08 is sent to amplifier 1185-08 via asynchronous receiver circuit 1184-08 and is exaggerated.From terminal 1186-08 amplifying signal is supplied with DLL circuit 1161.Particularly, via antenna 1187-08 from as the clock of the transmitter circuit 1183-08 output of the communication module 1052-08 of the communication module shown in the Figure 38 that is used to send, be output as clock via antenna 1187-08, asynchronous receiver circuit 1184-08 and amplifier 1185-08 as the communication module 1052-08 of the communication module shown in the Figure 38 that is used to receive.

DLL circuit 1161 postpones the clock CLK1 that sends from terminal 1186-08 (promptly with predetermined amount of time, modulating clock CLK1), and the clock CLK1 that postpones is sent to synchronous receiver circuit 1184-01 as clock CLK2, and (though not shown in the accompanying drawing, clock CLK2 also is sent to and receives with synchronous receiver circuit 1184-02～1184-07 and 1184-09～1184-15).Synchronous receiver circuit 1184-01 and clock CLK2 synchronization action.Particularly, the signal that is received by antenna 1187-01 is received by synchronous receiver circuit 1184-01 and clock synchronization, is exaggerated in amplifier 1185-01, and is output from terminal 1186-01.

Control unit 1053 is supplied with asynchronous receiver circuit 1184-08 (having the structure identical with the synchronous receiver circuit 1074 shown in Figure 34) with reference voltage V R1 and VR2.It is predetermined that the value of reference voltage V R1 and VR2 is based on experiment.

Figure 40 illustrates the structure as the DLL circuit 1161 of modulation circuit.DLL circuit 1161 comprises variable delay unit 1201, clock distribution late replicating 1202 and control unit 1203.Variable delay unit 1201 postpones input clock CLK1 with predetermined amount of time Ta, and output clock CLK2.Clock CLK2 is delayed with predetermined amount of time Tb in clock distribution late replicating 1202, and is output as clock CLK2A.The time quantum Ta that control unit 1203 controls are postponed by variable delay unit 1201, and, when the phase place of clock CLK2A is delayed, increase time quantum Ta, when the phase place of clock CLK2A is accelerated, reduce time quantum Ta, make between clock CLK2A and clock CLK1, not have phase difference.

Particularly, shown in Figure 41 A, when the signal (clock) that is received by antenna 1187-08 was sent to the terminal N3 of the asynchronous receiver circuit 1184-08 shown in Figure 39 and N4, this signal was imported into DLL circuit 1161 (Figure 41 B) as clock CLK1.DLL circuit 1161 is delayed with the time quantum Ta of clock CLK1, and output clock CLK2 (Figure 41 C).

For example, when the signal that is received by antenna 1187-01 is sent to the terminal N3 of asynchronous receiver circuit 1184-01 and N4 (Figure 41 D), must carry out timing to clock CLK2, so that it is suitable for handling this signal.In other words, with reference to Figure 45 explanation, the node NC1 of synchronous receiver circuit 1184-01 and each of NC2 all need to have the clock (Figure 41 E and Figure 41 F) of predetermined timing as following.Clock distribution late replicating 1202 is modulated this timing by with time quantum Tb delayed clock CLK2 and produce clock CLK2A.In other words, there is not phase difference, can implements accurate clock synchronisation by the phase place of modulating clock CLK1 and clock CLK2A is feasible.

Figure 42 illustrates the structure of the transmitter circuit 1183 (Figure 38) that moves with clock synchronization.Inverter 1221 detects the rising edge of clock by delay circuit 1222 and NAND circuit 1223.NAND circuit 1223, non-inverter 1224～1226, tristate buffer 1227 and 1228 and the structure of transistor 1229～1231 and NAND circuit 1222, inverter 1113～1115, tristate buffer 1116 and 1117 and the structure of transistor 1180～1220 basic identical.

When clock (Figure 43 A) when being transfused to clock terminal, inverter 1221, delay circuit 1222 and NAND circuit 1223 detect the rising edge of clocks.Simultaneously, the negative pulse synchronous with the rising edge of clock (Figure 43 B) is sent to the output (node N3) of NAND circuit 1223, and inverter 1224 output positive pulses.Like this, tristate buffer 1227 and 1228 is activated in negative pulse is output to the process of node N3, and supplies with input data (Figure 43 C) to antenna 1187T.Therefore, electric current I LT (Figure 43 D) is applied on the antenna 1187T.Because electromagnetic induction, electric current are applied to coupling factor K on the antenna for receiving 1187R that is coupled with antenna 1187T, and, voltage (Figure 43 E) produced at the input terminal N3 and the N4 of acceptor circuit 1184.

Figure 44 illustrates synchronous receiver circuit 1184 (Figure 39).As shown in figure 44, the terminal N3 of antenna 1187 is connected with the input terminal of clock synchronization amplifier 1253 with N4.Between terminal N3 and N4, connect transistor 1251 and 1252.Reference voltage V REF is supplied with the tie point of transistor 1251 and 1252.The lead-out terminal NA1 of clock synchronization amplifier 1253 is connected with comprising the intersect latch circuit of NAND circuit 1254 with 1255 with NA2.

The signal that sends from antenna 1187 is by 1253 synchronizations of clock synchronization amplifier and amplification, and pinned by the intersection latch circuit of NAND circuit 1254 and 1255.

For example, the structure of the amplifier of clock synchronization shown in Figure 45 1253.As shown in figure 45, in clock synchronization amplifier 1253, transistor 1271 and 1272 grid interconnect.The source of transistor 1271 is connected with the leakage of transistor 1273, and the source of transistor 1272 is connected with the leakage of transistor 1274.The common tie point in transistor 1273 and 1274 source is connected with the leakage of transistor 1279.The grid and the source of transistor 1272 are connected.Transistor 1275 and 1276 grid interconnect.The grid and the source of transistor 1275 are connected.The source of transistor 1275 is connected with the leakage of transistor 1277, and the source of transistor 1278 is connected with the leakage of transistor 1278. and the common tie point in transistor 1277 and 1278 source is connected with the leakage of transistor 1279.

Transistor 1273 is connected with terminal N3 with 1277 grid, and transistor 1274 is connected with terminal N4 with 1278 grid.

Transistor 1280,1281 is connected with node NC1 with 1283 grid.The source of transistor 1280 is connected with the grid of transistor 1287 and the leakage of transistor 1283. and the source of transistor 1280 also is connected with 1284 source with transistor 1281.The source of transistor 1284 is connected with 1284 the leakage and the source of transistor 1276 with transistorized 1281.The source of transistor 1283 also is connected with the grid of transistor 1288.The grid of transistor 1284 are connected with node NC1B.

The leakage of the source of transistor 1285 and transistor 1287 is connected with transistorized 1286 grid.The source of transistor 1286 is connected with the grid of transistor 1285 and the leakage of transistor 1288. Transistor 1287 and 1288 source interconnect, and this tie point is connected with the leakage of transistor 1289.

Transistor 1290,1291 is connected with node NC2 with 1292 grid.The source of transistor 1290 is connected with the source of transistor 1291, the source of transistor 1293 and the leakage of transistor 1287.The source of transistor 1292 and transistor 1291 are connected with 1293 the leakage and the source of transistor 1286.The source of transistor 1290 is connected with terminal NA2 with transistorized 1287 leakage, and the leakage of the source of transistor 1292 and transistor 1288 is connected with terminal NA1.

The grid of transistor 1279 and 1289 will be supplied with from the clock CLK2 of clock distribution late replicating 1202 outputs as shown in figure 40.After clock CLK2 was by inverter 1311 inversions, clock CLK2 is delayed circuit 1312 to postpone.Be delayed clock that circuit 1312 postpones by inverter 1313 inversion again and be output to node NC1, then inverter 1314 again inversion the clock inversion and send it to node NC1B.The clock that sends to node NC1B is delayed circuit 1315 further to postpone.Be delayed clock that circuit 1315 postpones by inverter 1316 inversions and be sent to node NC2.Then, the clock on the node NC2 is by inverter 1317 inversions and be output to node NC2B.

Inverter 1311 comprises transistor 1321 and 1322.Similarly, inverter 1313 comprises transistor 1323 and 1324, and inverter 1314 comprises transistor 1325 and 1326, and inverter 1315 comprises transistor 1327 and 1328, and inverter 1317 comprises transistor 1329 and 1330.

Compare with the clock CLK2 of first circuit that is used to comprise transistor 1271～1279, the clock (clock that is used for node NC1 and NC1B) that is used to comprise the second circuit of transistor 1280～1289 is delayed circuit 1312 with predetermined amount of time to postpone, and the clock (clock that is used for node NC2 and NC2B) that is used to comprise the tertiary circuit of transistor 1290～1293 further is delayed circuit 1315 with predetermined amount of time to postpone.Each circuit, be exaggerated and exported from the signal of terminal N3 and N4 transmission from terminal NA1 and NA2.

As mentioned above, multicore sheet encapsulation 1001 for example is installed on the exterior base as Figure 46 and 47 explanations.Figure 46 illustrates the multicore sheet encapsulation 1001 before being installed in the wiring substrate 1331.Figure 47 illustrates the multicore sheet encapsulation 1001 after being installed in the wiring substrate 1331.

As shown in drawings, in the bottom of multicore sheet encapsulation 1001, be arranged on wiring substrate 1331 on the corresponding position of communication chip 1332 on form groove 1351.When in wiring substrate 1331, the multicore sheet being installed and encapsulating 1001, the communication chip 1332 in the communication chip 1016 in the multicore sheet encapsulation 1001 and the substrate 1331 of connecting up be set to relative and the phase mutual edge distance fully near.

The current electrode 1017A that is arranged on the left side of accompanying drawing is set among the through hole 1341A, and being connected with second wiring 1334 from the top of wiring substrate 1331. the current electrode 1017B that is arranged on the left side of accompanying drawing is set at the through hole 1341B, and is connected with the 3rd wiring 1335 from the top of wiring substrate 1331.Wiring substrate 1331 comprises the metal line 1333～1336 that is used for to the each several part feed.

With compare as the thin and smooth situation in the bottom of Figure 23 and multicore sheet as shown in Figure 25 encapsulation 1001, by as Figure 46 and Figure 47, on the position corresponding, forming groove 1351, have only the part corresponding to form with the thickness of attenuation with groove 1351 with the communication chip installed on as the wiring substrate 1331 of exterior base 1332.Like this, can protect the inside of multicore sheet encapsulation 1001 reliably.

In various embodiments of the present invention, term " system " expression constitutes the device of a plurality of devices.

Semiconductor device can comprise a large amount of terminals and have less size according to an embodiment of the invention.

Semiconductor device manufacturing cost is lower according to an embodiment of the invention, and manufacturing time is shorter.

Substrate can comprise a large amount of terminals and have less size according to an embodiment of the invention.And the manufacturing cost of this substrate is lower, and manufacturing time is shorter.

Device board is easy to manufacture according to an embodiment of the invention, and cost is lower.

Semiconductor device can comprise a large amount of terminals and have less size according to an embodiment of the invention, and manufacturing cost is lower.

By semiconductor chip is installed in the substrate, communication can easily communicate between predetermined substrate with semiconductor chip according to an embodiment of the invention.Therefore, communication needn't form in substrate with through hole, makes substrate have common structure and simplifies the design of substrate.

Communicating by letter according to an embodiment of the invention with in the semiconductor chip, the substrate with common structure can be used to the communication semiconductor chip, and therefore can provide semiconductor device with lower manufacturing cost.

It will be appreciated by those skilled in the art that in the scope of appended claim and its equivalent, can carry out various changes, combination and recombinant and modification according to design needs and other factors.

Claims (18)

1. semiconductor device comprises:

First substrate comprises platysome, and this platysome has and is used to install the first surface of electronic unit and the second surface parallel with described first surface, and described first surface and described second surface are set to be parallel to each other along the thickness direction of described substrate;

Wherein, described first substrate comprises:

First district is positioned on the described platysome, is used to install described electronic unit;

Second district is positioned on the described platysome, comprise be used for to/from a plurality of first communication units of the second substrate transmission/received signal, described a plurality of first communication units are provided with in the mode of trooping;

Imput output circuit, be set in described first district or described second district, described imput output circuit is corresponding with described first communication unit, and each of described imput output circuit comprises: the input unit that is used for the output circuit and being used to that signal outputs to the second communication unit of described second substrate corresponding with described first communication unit is received the signal that sends from described corresponding second communication unit; With

Control circuit is used to control the input and output of described imput output circuit, and described control circuit is set in described first district or described second district of described first substrate.

2. according to the semiconductor device of claim 1, also comprise:

Connect commutation circuit, be used for switching the connection between the predetermined terminal of of described first communication unit and described electronic unit, described connection commutation circuit is set in described first district or described second district of described first substrate.

3. according to the semiconductor device of claim 1, it is characterized in that,

Described first communication unit is first through hole, and

Described first through hole in described second district of described first substrate is via first salient point, be electrically connected with described second suprabasil second through hole in the position corresponding with described first through hole in described second district of described first substrate, and it is adjacent and parallel with the described platysome of described first substrate that described second substrate is set to.

4. according to the semiconductor device of claim 1, also comprise:

The planar metal film is set to parallel with the described platysome of described first substrate and separates,

It is characterized in that described metallic film engages with described first substrate with second salient point, described second salient point is inserted between described metallic film and described first substrate.

5. according to the semiconductor device of claim 4, it is characterized in that,

Described electronic unit is set to contact with described metallic film, makes that the heat that is produced by described electronic unit is left.

6. according to the semiconductor device of claim 4, it is characterized in that,

Described metallic film is provided so that described metallic film surrounds each in described first communication unit.

7. according to the semiconductor device of claim 4, it is characterized in that,

The part of described metallic film is projected into the outside in described first district of described first substrate.

8. according to the semiconductor device of claim 4, it is characterized in that,

Described metallic film via described second salient point to described electronic unit feed.

9. according to the semiconductor device of claim 1, it is characterized in that,

Described first communication unit is an antenna.

10. semiconductor device comprises:

A plurality of substrates, comprise first to fourth substrate, in described first to fourth substrate each comprises the platysome with the first surface that is used to install electronic unit and second surface parallel with described first surface, and described first and second surfaces are set to be parallel to each other along the thickness direction of described substrate; It is characterized in that,

First electronic unit is installed in described first substrate,

Second electronic unit is installed in described second substrate, described second substrate is set makes that the described first surface of the described first surface of described first substrate and described second substrate is relative,

The 3rd electronic unit is installed in described the 3rd substrate,

Quadrielectron parts are installed in described the 4th substrate, described the 4th substrate are set make that the described first surface of the described first surface of described the 3rd substrate and described the 4th substrate is relative, and

On position with respect to the mutual correspondence of described second substrate and described the 3rd substrate, in described second substrate and with described the 3rd substrate of the adjacent setting of described second substrate on be formed for the antenna of received signal.

11. the semiconductor device according to claim 10 is characterized in that,

On each described platysome of described substrate, form described antenna in the mode of trooping.

12. the semiconductor device according to claim 10 also comprises:

Connect commutation circuit, be used to switch being connected between the predetermined terminal of the second suprabasil antenna and described second electronic unit, and switch being connected between the predetermined terminal of the 3rd suprabasil antenna and described the 3rd electronic unit.

13. the semiconductor device according to claim 10 also comprises:

Planar metal film, each of this planar metal film all are set to parallel with the described platysome of described substrate, and described metallic film is to being arranged on described suprabasil described electronic unit feed.

14. the semiconductor device according to claim 13 is characterized in that,

Described metallic film comprises:

First metallic film is set to parallel with the described platysome of described first and second substrates and separates, and via salient point be connected with described first and second substrates and

Second metallic film is set to parallel with the described platysome of described third and fourth substrate and separates, and is connected with described third and fourth substrate via salient point, and

Described first metallic film and described second metallic film interconnect.

15. the semiconductor device according to claim 13 is characterized in that,

Described metallic film comprises:

First metallic film is set to parallel with the described platysome of described first substrate and separates, and is connected with described first substrate via closing line,

Second metallic film is set to parallel with the described platysome of described second substrate and separates, and is connected with described second substrate via closing line,

The 3rd metallic film is set to parallel with the described platysome of described the 3rd substrate and separates, and is connected with described the 3rd substrate via closing line, and

The 4th metallic film is set to parallel with the described platysome of described the 4th substrate and separates, and is connected with described the 4th substrate via closing line,

It is characterized in that described first to fourth metallic film interconnects.

16. the semiconductor device according to claim 15 is characterized in that,

Described first substrate comprises the 5th substrate, and the 5th substrate has a plurality of via holes and is connected with described first substrate via salient point,

Described second substrate comprises the 6th substrate, the 6th substrate has a plurality of via holes, connects with described second substrate and be connected via the described via hole of salient point with described the 5th substrate that is provided with on the position corresponding with the described via hole of described second substrate via salient point

Described the 3rd substrate comprises the 7th substrate, and the 7th substrate has a plurality of via holes and is connected with described the 3rd substrate via salient point, and

Described the 4th substrate comprises the 8th substrate, and the 8th substrate has a plurality of via holes, connects with described the 4th substrate and be connected via the described via hole of salient point with described the 7th substrate that is provided with on the position corresponding with the described via hole of described the 4th substrate via salient point.

17. the semiconductor device according to claim 15 is characterized in that,

Described first substrate comprises first dividing plate, and this first dividing plate has the first end that engages with described first substrate,

Described second substrate comprises second partition, and this second partition has first end that engages with described second substrate and the second end that engages with described first dividing plate with salient point, and described salient point is inserted between described first dividing plate and the described second partition,

Described the 3rd substrate comprises the 3rd dividing plate, and the 3rd dividing plate has the first end that engages with described the 3rd substrate, and

Described the 4th substrate comprises the 4th dividing plate, and the 4th dividing plate has first end that engages with described the 4th substrate and the second end that engages with described the 3rd dividing plate with salient point, and described salient point is inserted between described the 3rd dividing plate and described the 4th dividing plate.

18. substrate, comprise platysome, this platysome has and is used to install the first surface of electronic unit and the second surface parallel with described first surface, and described first and second surfaces are set to be parallel to each other along the thickness direction of described substrate, and described substrate comprises:

First district is positioned on the described platysome, is used to install described electronic unit;

Second district is positioned on the described platysome, comprise be used for to/from a plurality of first communication units of the second substrate transmission/received signal, described a plurality of first communication units are provided with in the mode of trooping;

Imput output circuit, be set in described first district or described second district, described imput output circuit is corresponding with described first communication unit, and each of described imput output circuit comprises: the input unit that is used for the output circuit and being used to that signal outputs to the second communication unit of described second substrate corresponding with described first communication unit is received the signal that sends from described corresponding second communication unit; With

Control circuit is used to control the input and output of described imput output circuit, and described control circuit is set in described first district or described second district of described first substrate.

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