CN100480717C

CN100480717C - Apparatus for measuring clock signal generation

Info

Publication number: CN100480717C
Application number: CNB200410064419XA
Authority: CN
Inventors: 叶大嘉; 林建光; 吴奇峰
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2004-08-24
Filing date: 2004-08-24
Publication date: 2009-04-22
Anticipated expiration: 2024-08-24
Also published as: CN1740802A

Abstract

The test clock signal generator device includes a homogeneous clock signal generator for receiving a reference clock signal and a scanning chain energization signal and outputting a homogeneous clock signal, in which the frequency of said homogeneous clock signal is identical to that of said reference clock signal, and a multiplexer for receiving said homogeneous clock signal and a scanning chain clock signal, and outputting a test clock signal according to said scanning chain energization signal, in which the frequency of said reference clock signal is higher than that of said scanning chain clock signal.

Description

Apparatus for measuring clock signal generation

Technical field

The present invention is about having a test clock signals generation circuit in the integrated circuit, particularly integrated circuit.

Background technology

When the manufacturing DLC (digital logic circuit) is followed in design, must carry out circuit error detection and test by proper device.General DLC (digital logic circuit), as shown in Figure 1, it comprises combinational logic circuit (combinationalcircuits) and circuit (sequential circuits) in proper order.Combinational logic circuit 10-16 produces output signal according to present input signal; Circuit (as: trigger D1-D6) has memory function in proper order, can produce output signal according to previous input signal.Wherein, sclk is a test clock signals.

Conventional DLC (digital logic circuit) test mode is one scan chain (scanchain) with a plurality of trigger serial connections, so, scans in the chain via specific logical value is written in regular turn, and with this DLC (digital logic circuit) of error detection, this practice is called sweep test.Wherein, (Scan Enable SE), operates under scan chain pattern (shift mode) and normal mode (normal mode) to select circuit by a plurality of multiplexers (mux1-mux6) and scan chain enable signal.When the scan chain pattern (SE=1), by test board test pattern (test pattern) is moved into (Scan-In, SI) and be stored in the trigger (D1-D6).Then, when (SE=0) enters normal mode when (claiming capture mode again), make to be stored in being worth of trigger D1-D6,, and deposit calculated result in each trigger D1-D6 with the logical operation under the simulation normal operating conditions to send into those combinational logic circuits 10-16.At last, enter scan chain pattern (SE=1) again, test result can via the serial connection the trigger scan chain shift out in regular turn (Scan-Out, SO), to detect this chip whether can operate as normal.

But, the work clock of chip significantly promoted in recent years, had been risen to the spectrum of hundreds of MHz by tens of MHz, and the scan clock that being subject to test board can provide still fails to promote synchronously, made that chip can't be to test with speed (at speed).Even if there is minority that the test board of high-frequency clock can be provided, the unit price of present stage is also too expensive, does not meet cost benefit.Inequality when the frequency of operation of the internal circuit of this chip and I/O (I/O) circuit, make chip be difficult for to test with speed (at speed).In view of this, the invention provides a kind of test clock signals generation circuit, make each circuit of chip internal to be tested be able to corresponding work clock and carry out with the speed test.

Summary of the invention

Purpose of the present invention is for providing a kind of test clock signals generation circuit.

Another object of the present invention is applied in the testing scanning chain for providing a kind of, and the clock generating circuit of performance test chip internal produces the test pulse signal with speed.

The invention provides a kind of apparatus for measuring clock signal generation, this apparatus for measuring clock signal generation comprises: together fast clock-signal generator, receive a reference clock signal and one scan chain enable signal, export together fast clock signal, wherein, this frequency with fast clock signal is identical with the frequency of this reference clock signal; And a multiplexer, receiving should be with fast clock signal and one scan chain clock signal signal, and exports a test clock signals according to this scan chain enable signal; Wherein, the frequency of this reference clock signal is higher than the frequency of this scan chain clock signal signal.

Description of drawings

Fig. 1 is the partial schematic diagram of specific function circuit;

Fig. 2 is the circuit box synoptic diagram of the embodiment of the invention;

Fig. 3 is the circuit block diagram of the same fast clock-signal generator of the embodiment of the invention;

Fig. 4 is the sequential chart according to Fig. 3 circuit;

Fig. 5 is the built-up circuit synoptic diagram of the embodiment of the invention about comparer; And

Fig. 6 is that another embodiment of the present invention is about the circuit box synoptic diagram with fast clock-signal generator.

The figure number table of comparisons:

10,12,14,16: combinational logic circuit 22: low frequency test clock signals generator

20: test clock signals generation circuit 26: multiplexer

24,28: with fast clock-signal generator 28: clock-signal generator

240: synchronizer 241: impulse controller

242: counter 244,246,248: comparer

Embodiment

As shown in Figure 2, be the circuit box synoptic diagram of the apparatus for measuring clock signal generation of preferred embodiment of the present invention.Test clock signals generation circuit 20 of the present invention comprises: a low frequency test clock signals generator 22, together a fast clock-signal generator 24 and a multiplexer 26.(SE=1) entered the scan chain pattern when this test clock signals generation circuit 20 was high state (high) at scan chain enable signal (SE), made the test signal (tclk) of output with the scan chain clock signal signal sclk of low frequency; And (SE=0) enters normal mode when SE is low state (low), is test signal (tclk) to carry out the identical same fast clock signal of frequency with chip to be measured.

Low frequency test clock signals generator 22 is in order to provide one scan chain clock signal (sclk), and this scan chain clock signal is provided by test board (tester) usually, also can be produced voluntarily by chip certainly.Comprise together fast clock (clk_in) input end, one scan chain enable signal (SE) input end and one (clk_out) output terminal with fast clock-signal generator 24, wherein can be provided by the clock-signal generator 28 of chip internal with fast clock (reference clock signal) clk_in.Usually, this clock-signal generator 28 be a phase-locked loop (Phase Locked Loop, PLL).

Please refer to Fig. 3, it is about the block schematic diagram with fast clock-signal generator according to the embodiment of the invention.As shown in the figure, be made up of an at least one synchronizer 240 and an impulse controller 241 with fast clock-signal generator 24, this impulse controller 241 comprises a counter 242 and a comparer 244 compositions.In the present embodiment, synchronizer 240, counter 242 are all operated with identical clock signal (clk_in).At another embodiment, synchronizer 240 is composed in series by two triggers (D7 and D8).When test clock signals generation circuit becomes normal mode in the scan chain pattern, by this synchronizer 240 with counter reset 242.In addition, in embodiments of the present invention, counter 242 is selected binary counter (binarycounter) for use, other as gray code counter (Gray code counter) also applicable to counter device of the present invention.

For example, when counter 242 enabling countings,, and be 1 and 2 o'clock in count value via the effect of comparer 244, export together fast clock enable signal (clk_out_en).With fast clock enable signal again with fast clock (clk_in) through one with the logical operation of door AND1 after, to produce together fast clock test dipulse signal.Please refer to the sequential chart of Fig. 4, in the present embodiment, the frequency of sclk and clk_in is 10MHz and 200MHz respectively.Another embodiment, the figure place of this counter gets final product with enough count pulse numbers.Another embodiment when the count value of this counter is upward will not continue to go up number, does not do the operation of making zero, in order to avoid counter is in non-predetermined count value generation maloperation in limited time yet.

In addition, the internal circuit calcspar about comparer 244 please refer to Fig. 5, in the present invention, and when comparer 244 is received from 5 bit (Q ₀-Q ₄) counter 242 transmit count value the time, by XOR gate (XOR1-XOR10), rejection gate (NOR1, NOR2) and one or the effect of door (OR), in counter=1,2 o'clock, with the same fast clock enable signal clk_out_en of an exportable high state (high).Above-mentioned counter=1,2 o'clock together fast clock enable signal clk_out_en of output, only be an embodiment, according to method of the present invention, when also can being set in counter=5, or other preset values at 6 o'clock, just exports by comparer 244 with fast clock enable signal clk_out_en.Certainly, according to method of the present invention, counter can also export with fast clock enable signal clk_out_en at=1,2,3 o'clock, and after the logical operation of feasible and AND1, produced together fast clock test three pulse signals.In other words, can be via the setting of counter in order to control this umber of pulse with fast clock signal.

As shown in Figure 4, when SE becomes 0 by 1, representative will become normal mode by the scan chain pattern, and the output signal of test clock signals generation circuit 20 also will become clk_out by sclk.At this moment, the output signal SE_12 of synchronizer 240 (synchronizing clock signals) also becomes 0 by 1 after postponing a bit of time, and (set) counter 242 of also resetting simultaneously makes it begin to go up number by 0 according to the frequency with fast clock clk_in.When count value (counter) is 1 and 2, effect by comparer 244, with the together fast clock enable signal clk_out_en of output, again with fast clock clk_in through one with the logical operation of door AND1 after, to produce together fast clock test dipulse (comprising pulse 1 and pulse 2) signal clk_out.At last, SE becomes at 1 o'clock by 0, gets back to the result that the scan chain modal representation prepares to read testing authentication, whether meets the logic operation result of expection with the result of compare test.

Therefore, utilize of the present invention with in the test process of fast clock test dipulse signal as test signal, as shown in Figure 1, when the scan chain pattern (SE=1), with scan chain clock signal sclk test pattern is moved into (SI) and be stored in the trigger (D1-D6) by test board.Then, when SE=0 enters normal mode, at this moment, the triggering of pulse 1 signal by clk_out, make and be stored in the worth of trigger D1-D6 to send into (launch) first combinational logic circuit 10 to the 4th combinational logic circuits 16 respectively, with the logical operation of simulation under the normal operating conditions, and with calculated result each trigger D1-D6 that restores.

As shown in Figure 6, circuit of the present invention does not limit and produces one group same speed test dipulse signal.For example the setting of the comparer (first comparer 246 and second comparer 248) by two groups (or more than) can provide the same speed test dipulse signal of two groups (or more than).As shown in Figure 6, first comparer 246 is being 1 and 2 o'clock with fast clock specific pulse generator 28 in count value, and output is with fast clock test pulse signal clk_out1; 246 of second comparers are being 3 and 4 o'clock with fast clock specific pulse generator 28 in count value, and output is with fast clock test pulse signal clk_out2).

Design with fast clock test signal generating circuit of the present invention has considerable advantage, and for instance: use original low-frequency clock test board, same fast clock signal that promptly can high frequency is tested chip to be measured, realizes synchronism detection purpose at a high speed.Though the present invention illustrates as above with preferred embodiments, so it is not only to terminate in the foregoing description in order to limit the present invention's spirit with the invention entity.So the modification of being done in not breaking away from spirit of the present invention and scope all should be included in the claim scope.

Claims

1. apparatus for measuring clock signal generation that is positioned at a chip, this device comprises:

Together fast clock-signal generator receives a reference clock signal and one scan chain enable signal, exports together fast clock signal, and wherein, this frequency with fast clock signal is identical with the frequency of this reference clock signal; And

One multiplexer receives and is somebody's turn to do with fast clock signal and one scan chain clock signal, and exports a test clock signals according to this scan chain enable signal;

Wherein, the frequency of this reference clock signal is higher than the frequency of this scan chain clock signal.

2. apparatus for measuring clock signal generation as claimed in claim 1, wherein this reference clock signal is an operation clock signal of this chip.

3. apparatus for measuring clock signal generation as claimed in claim 2, wherein this reference clock signal is produced by a phase-locked loop of this chip, and wherein this scan chain clock signal is produced by an external testing platform.

4. apparatus for measuring clock signal generation as claimed in claim 1 wherein should also comprise with fast clock-signal generator:

At least one trigger receives this reference clock signal and this scan chain enable signal, exports one first clock signal; And

One impulse controller, in order to control the umber of pulse of this first clock signal, output should be with fast clock signal.

5. apparatus for measuring clock signal generation as claimed in claim 4, wherein this impulse controller comprises a counter, this counter is in order to count this umber of pulse with fast clock signal.

6. apparatus for measuring clock signal generation as claimed in claim 1, wherein this test clock signals comprises the composition of this reference clock signal and this scan chain clock signal.

7. apparatus for measuring clock signal generation as claimed in claim 1, wherein this scan chain enable signal comprises an one scan chain pattern and a normal mode, wherein when this scan chain enable signal is this scan chain pattern, this test clock signals is same as this scan chain clock signal, wherein when this scan chain enable signal is this normal mode, this test clock signals comprises at least one pulse signal, and the frequency of this pulse signal is same as the frequency of this reference clock signal.

One kind the test one chip the test clock signals production method, this method comprises:

Produce a reference clock signal;

Receive one scan chain enable signal and one scan chain clock signal; And

According to this scan chain enable signal, export a test clock signals, wherein this test clock signals comprises the composition of this reference clock signal and this scan chain clock signal.

9. method as claimed in claim 8, wherein the frequency of this reference clock signal is higher than the frequency of this test clock signals.

10. method as claimed in claim 8, wherein this reference clock signal is identical with an operation clock signal of this chip.