CN100477304C

CN100477304C - Semiconductor light-emitting device, and a method of manufacture of a semiconductor device

Info

Publication number: CN100477304C
Application number: CNB2006100776893A
Authority: CN
Inventors: S·E·霍珀; V·鲍斯奎特; J·赫弗尔南
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2005-04-28
Filing date: 2006-04-28
Publication date: 2009-04-08
Anticipated expiration: 2026-04-28
Also published as: CN1855565A; GB2425652A; GB0508556D0

Abstract

The invention discloses a preparing method of nitride semiconductor part, which comprises the following steps: growing InxGa1-xN (0<=x<=1) layer; growing nitride semiconductor layer with aluminum on the InxGa1-xN (0<=x<=1) layer; forming electronic gas area at interface position of InxGa1-xN(0<=x<=1) layer and nitride semiconductor layer; annealing the nitride semiconductor layer at 800 deg.c.

Description

The manufacture method of light emitting semiconductor device and semiconductor device

Technical field

The present invention relates to light emitting semiconductor device, relate in particular to the light emitting semiconductor device of making in the nitride material system such as (Al, Ga, In) N material system.The invention still further relates to the manufacture method of semiconductor device, relate in particular to manufacturing such as semi-conducting material in the nitride material system of (Al, Ga, In) N material system.The present invention for example can be applicable to light-emitting diode (LED) or laser diode (LD), perhaps is applied to the manufacturing such as the optical semiconductor device of light-emitting diode (LED) or laser diode (LD).The present invention also can be applicable to the manufacturing such as the electronic semiconductor components of hetero-structure field effect transistor (HFET) or High Electron Mobility Transistor (HEMT).

Background of invention

(Al, Ga, In) N material system comprises having general formula Al _xGa _yIn _1-x-yThe material of N (wherein 0≤x≤1 and 0≤y≤1).In this is used, the a kind of of (Al, Ga, In) N material system of the molar fraction non-zero of aluminium, gallium and indium will be called AlGaInN, al mole fraction is zero but a kind of InGaN that is called of the molar fraction non-zero of gallium and indium, and indium mole fraction is zero but a kind of AlGaN or the like that is called of the molar fraction non-zero of gallium and aluminium.Light emitting semiconductor device in current suitable concern manufacturing (Al, Ga, In) the N material system is because the device of making in this system can send the light of the blue wavelength region of spectrum.For example, the light emitting semiconductor device of making in (Al, Ga, In) N material system has been described among the US-A-5777350.In (Al, Ga, In) N material system, make such as the transistorized electronic device of high-performance also be pay close attention to.

Fig. 1 is the typical semiconductor Laser Devices made in (Al, Ga, In) N material system (or laser diode-" LD ") 10 schematic diagram.This device can send the light in the blue wavelength region.

The Laser Devices 10 of Fig. 1 grow on the substrate 1.In the laser diode 10 of Fig. 1, substrate 1 is a sapphire substrate.Resilient coating 2, first coating layer 3 and the first optical guidance layer 4 grow on the substrate 1 in this order.In the embodiment in figure 1, resilient coating 2 is n type GaN layers, and first coating layer 3 is n type AlGaN layers, and the first optical guidance layer 4 is n type GaN layers.

Active region 5 grows on the first optical guidance layer 4.

The second optical guidance layer 7, second coating layer 8 and cap rock 9 grow on the active region 5 in this order.The conductivity type opposite of the second optical guidance layer 7 and second coating layer 8 and the first optical guidance layer 4 and first coating layer 3; In the Laser Devices 10 of Fig. 1, the first optical guidance layer 4 and first coating layer 3 are n types, so the second optical guidance layer 7 and second coating layer 8 are p type layers.In the Laser Devices of Fig. 1, the second optical guidance layer 7 is p type GaN layers, and second coating layer 8 is p type AlGaN layers, and cap rock 9 is p type GaN layers.

Be not shown specifically the structure of the active region 5 of Laser Devices 10 among Fig. 1.But general, active region 5 is to be provided with single quantum well (SQW) active region of a quantum well layer between first and second barrier layers or to have two or more quantum well layers and each quantum well layer all is arranged at two Multiple Quantum Well (MQW) active regions between the barrier layer.For example, quantum well layer can be the layer of InGaN, AlGaN or AlGaInN.

High-quality hetero-structure field effect transistor (HFET) and High Electron Mobility Transistor (HEMT) need in the channel region combination of big electronics sheet concentration and high electron mobility usually.A kind of method that obtains necessary electronic sheet concentration and electron mobility is that the electronics gas area is incorporated into device.Because with the less interaction (or scattering) of matrix or foreign atom, the electronics in the electron gas can have than mobility higher in the block semiconductor crystal.

Also expect the electronics gas area is incorporated into the nitride semiconductor light electronic device, as described below.

Known, the electronics gas area for example can be made of the potential well that electronics wherein can gather to form electron gas.According to the shape and the thickness of potential well, the electronics in the electron gas can be restricted to the direction vertical with the potential well plane and only can with the parallel plane two dimension of potential well in move freely; In this case, electron gas is called " two-dimensional electron gas " (2DEG).Perhaps, the electronics of electron gas can move freely in three-dimensional, and electron gas is known as " three-dimensional electronic gas " (3DEG) in this situation.Because less with the interaction (or scattering) of matrix or foreign atom, the mobility of the electronics in the electron gas is far above the electron mobility in the block semiconductor crystal.

People such as Jeganathan have reported in J.Appln.Phys.94 (2003) p3260: the AlGaN/GaN heterostructure can be used for realizing that the sheet carrier concentration reaches 5 * 10 ¹³Cm ^-22DEG and do not have the intentional doping of heterostructure.This has surpassed well such as attainable carrier concentration in other III-V system of AlGaAs/GaAs system, and this mainly is owing to compare five times of big piezoelectric polarizations of the AlGaN layer that is subjected to stress with AlGaAs and compare spontaneous polarization very big in the buergerite III-nitride (polarization under the zero stress) with other III-V material.But people's such as Jeganathan method need be used the AlGaN layer with very high al mole fraction, even may use the AlN layer, to obtain 5 * 10 ¹³Cm ^-2The 2DEG of sheet carrier concentration.Usually do not expect that the AlN or the AlGaN layer that will have high al mole fraction are incorporated into device,, form dislocation because this can cause too much stress in the device, and unwanted impurity combination.

The U.S. Patent application No.10/974348 that awaits the reply jointly (the UK Patent Application No.0325100.6 that awaits the reply jointly) discloses and has a kind ofly made in nitride material system and the active region is arranged at on-chip light emitting semiconductor device.The active region comprise the lowermost layer that forms the active region first aluminous layer (for example, AlGaN layer), form the active region the superiors second aluminous layer and be arranged at first aluminous layer and second aluminous layer between at least one InGaN quantum well layer.

People such as Jena have reported in Appl.Phys.Lett.81 (23) 2002p4395 and have used the AlGaN layer of the molar fraction with classification to form 3-D electron gas or sheet.This method produces has 9 * 10 ¹²Cm ^-2The electron gas of the most large stretch of electron concentration (sheet electron concentration).

People such as Ibbetson have discussed the AlGaN/GaN electron source in the electron gas at the interface in Appl.Phys.Lett.77 (2) 2000p250.They surface state is defined as the main source of electronics and predict AlGaN/GaN at the interface electron gas 4.8 * 10 ¹³Cm ^-2The most large stretch of electron concentration.

People such as Mkhovan have described in J.Appl.Phys.95 (4) 2004, p1843 has about 5 * 10 in the AlGaN/GaN material system ¹³Cm ^-2The formation of accurate 2DEG of electronics sheet concentration.Their statement sheet electron concentrations are by the control of polarization induced charge and influenced by interfacial diffusion.They have provided how 2DEG forms or as the less details of the electron source of 2DEG.

People such as Jeganathan (more than) in J.Appl.Phys.94 (2003) p3260, report: the AlGaN/GaN heterostructure can be used for realizing that the sheet carrier concentration reaches 5 * 10 ¹³Cm ^-22DEG and do not have the intentional doping of heterostructure.But, do not instruct the AlGaN/GaN heterostructure is incorporated into opto-electronic device the electronics gas area to be provided and to improve the optical efficiency of device.

U.S. Patent No. 6515313 discloses a kind of luminescent device, and wherein bipolar minimizing method (mixing such as interface classification or interface) is used to reduce the field that any polarization on the active region of device is inducted, thereby improves optical efficiency.But among the present invention, introduce bipolar and polarization field especially to form electron gas.

U.S. Patent No. 6541797 discloses the luminescent device of making in the nitride material system, and it has the 2DEG that forms in the active region on its p type side and (has less than 5 * 10 ¹³Cm ^-2The sheet carrier concentration).This 2DEG district is as the collecting region of effective electron-hole-recombination.On the contrary, among the present invention, the electron gas district is positioned at outside the active region, and on the n of active region type side.

U.S. Patent No. 6614060 has been described a kind of luminescent device, and it comprises the wide InGaN layer that is positioned under the active region, is used for electron capture and the electron resonance tunnelling is gone into the active region.Do not indicate the electron gas of formation Anywhere in device.

People such as Kim are at Phys.Stat.Sol. (a) 201, and (2004) have reported the use of electron tunneling barrier layer in the nitride LED, to improve optical property among the p2663.Electron barrier layer by the active region that is arranged in LED or just the thick AlGaN of 2nm below this district provide.The AlGaN layer is reported as and reduces the hot electron overflow of flowing out the active region.People such as Kim do not report or advise the electron gas of formation at the interface between AlGaN tunneling barrier layer and the following GaN.In addition, described in J.App.Phys.86 (1999) p4520, this thin AlGaN layer will not cause the formation of 2DEG according to people such as Smorchova.

People such as Luo in J.Elec.Matl.30 (5) 2001, p459, reported from the improvement of InAs quantum dot (QD) the luminescence generated by light radiation intensity of 2DEG coupling.By with the overlapping 2DEGE of QD in the wave function of electronics, 2DEG is considered to the electronics container as QD.But in the present invention, electron gas is outside the active region, so the wave function of the electronics in the electron gas is not coupled to the active region.

Summary of the invention

One aspect of the present invention provides a kind of method of making nitride compound semiconductor device, and this method may further comprise the steps: growth In _xGa _1-xN (0≤x≤1) layer; Under at least 500 ℃ growth temperature at described In _xGa _1-xGrowth contains the nitride semiconductor layer of aluminium on the N layer, and the described thickness that contains the nitride semiconductor layer of aluminium makes the electronics gas area be formed at described In thus _xGa _1-xBetween N layer and the nitride semiconductor layer at the interface; And under at least 800 ℃ temperature, described nitride semiconductor layer is annealed.

The zone of term used herein " electronics gas area " expression wherein can formation electron gas.Because with the less interaction (or scattering) of matrix or atoms of dopant, the electronics in the electron gas can have higher mobility than the electronics in the block semiconductor crystallization.

Term used herein " nitride compound semiconductor device " expression wherein each semiconductor layer all is the semiconductor device of nitride material system part.An example of nitride material system is (Al, Ga, In) N material system.

Can be at the described nitride semiconductor layer that contains aluminium of growth under 750 ℃ or the following growth temperature.

Find, use relatively low growth temperature to cause the formation of electron gas in the electronics gas area succeeded by annealing steps to the nitride semiconductor layer that contains aluminium, its sheet electron concentration is apparently higher than the sheet electron concentration of the electron gas that method obtained by prior art.The present invention can obtain to have 6 * 10 when 300K ¹³Cm ^-2Or the electron gas of above sheet electron concentration.(all sheet electron concentrations of quoting in the description of the invention are all under the situation that applies zero electric field or magnetic field.) in addition, have the nitride semiconductor layer of relatively low aluminum concentration, the electron gas that can obtain to have this high sheet electron concentration, and the In that need not deliberately mix by use _xGa _1-xN layer or nitride semiconductor layer.The present invention does not need to use AlN with high al mole fraction or the layer of AlGaN.Therefore, the present invention causes producing the photoelectricity made in the III-nitride-based semiconductor and the improvement efficient and the performance of electronic device.The sheet carrier concentration that realizes by the present invention is higher than can be for modulation doping HFET (for example according to Appl.Phys, the growth of the people's such as Maeda that provide among Lett.79 (2001) p1634 the method) realization of routine growth with 2D electron gas.

Nitride semiconductor layer can be Al _yGa _zIn _1-y-zN (0＜y≤1,0≤z≤1) layer.

Al _yGa _zIn _1-y-zThe N layer can have 0＜y＜0.3.Use has this low al mole fraction, and (In) the N layer will still allow to produce and have 6 * 10 for Al, Ga ¹³Cm ^-2Or the electron gas of above sheet carrier concentration, but will avoid and use AlN layer with high al mole fraction or (Al, Ga, the In) shortcoming that is associated of N layer, thus still can obtain the second best in quality device.

Nitride semiconductor layer can be Al _yGa _1-yThe N layer.

Nitride semiconductor layer has the thickness of 5nm at least, and it can have the thickness less than 50nm.The thickness of nitride semiconductor layer is a factor that determines whether to form electron gas, and makes the thickness of nitride semiconductor layer will allow to form the electron gas with high sheet electron concentration in these restrictions.If the thickness of nitride semiconductor layer is significantly less than 5nm or obviously greater than 50nm, then electron gas can not form.

In _xGa _1-xThe N layer is the layer of GaN.

In _xGa _1-xThe N layer has the thickness of 20nm at least, and it can have the thickness less than 3 μ m.

If In _xGa _1-xThe thickness of N layer is starkly lower than 20nm, then can not be included in the electron gas that gathers in the electronics gas area.

In _xGa _1-xThe N layer can deliberately not mixed, and nitride semiconductor layer can deliberately not mixed.Method of the present invention does not rely on the electron gas that these layers that mix have high sheet electron concentration with acquisition.This provides the advantage that is higher than art methods, wherein art methods depends on and uses heavily doped layer so that the electron gas with high sheet electron concentration to be provided, because because diffusion of impurities is gone into other layer of device, the performance that highly doped layer may the deterioration device is provided in device architecture, perhaps causes performance to change in time.

Perhaps, In _xGa _1-xThe N layer can be doped the n type.This formation for electron gas in the electronics gas area is unnecessary, but it can reduce In _xGa _1-xThe resistance of N layer, and therefore allow thicker In _xGa _1-xThe N layer is incorporated into device architecture, and does not make the resistance of device too high.Perhaps, nitride semiconductor layer can be doped the n type, although this nitride semiconductor layer that mixes is more unessential, even because nitride semiconductor layer thin layer and therefore also have lower resistance when deliberately not mixed normally.An example of suitable n type alloy is a silicon.

This method can comprise directly at In _xGa _1-xGrowing nitride semiconductor layer on the N layer.

The present invention can be included in the described In of growth in the growth chamber _xGa _1-xN layer and described nitride semiconductor layer, and can be included in and described nitride semiconductor layer is annealed in the described growth chamber.This is known as " scene " annealing, and has avoided removing nitride semiconductor layer to implement the needs of annealing from growth chamber.During the other layer of growth, this is particularly advantageous on being desirably in nitride semiconductor layer.Nitride semiconductor layer preferred and then it grown after and before any other layer of growth, be annealed.

Perhaps, layer structure can remove from growth chamber, makes nitride semiconductor layer be annealed (this is called " outside " annealing) outside growth chamber.After the preferred and then growing nitride semiconductor layer and before any other layer of growth, from growth chamber, shift out a layer structure and anneal.

This method can be included in one or more other (Al, Ga, In) N layers of growth on the nitride semiconductor layer.In addition, this one or more other (In) the N layer can be at growth In for Al, Ga _xGa _1-xGrow before the N layer.This allow with the electronics gas area be incorporated into such as LED, LD, HEMT or HFET (Al, Ga is In) in the structure of the electronics of N or photoelectric device.

When the temperature of 300K, can in the electronics gas area, form and have 6 * 10 ¹³Cm ^-2Or above sheet carrier concentration or have 1 * 10 ¹⁴Cm ^-2Or the electron gas of above sheet carrier concentration.

The step of annealing nitride semiconductor layer can have 10 minutes or the following duration.

A second aspect of the present invention provides a kind of light emitting semiconductor device of making in nitride material system, it comprises: be used for photoemissive active region and be arranged at electronics gas area on the n type side of described active region; In wherein using, the electronics gas area has at least 6 * 10 when comprising 300K ¹³Cm ^-2The electron gas of sheet electron density.

In the operation of device, electronics accumulates in the electronics gas area and forms electron gas.Electron gas provides outside the active region but has been in or near the zone of the high concentration electron charge of the n lateral boundaries of active region, and as the electronics container so that charge carrier to be provided in the active region.Therefore, being provided with of electronics gas area improved the electronics injection that enters the device active region in the device, thereby improved the optical efficiency (optical efficiency is defined as the optical output power of device and the ratio of the electric energy that device consumes) of luminescent device.

The electronics gas area for example can be made of potential well, and electronics can gather to form electron gas in this potential well.According to the shape and the thickness of potential well, the electronics in the electron gas can be constrained on the direction vertical with the plane of quantum well and only with the parallel plane two dimension of this quantum well in free movement; In this case, electron gas is known as " two-dimensional electron gas " (2DEG).Perhaps, the electronics of electron gas can be in free movement in whole three-dimensionals, and this electron gas is known as three-dimensional electronic gas (3DEG) in this case.

Device can comprise the ground floor on the n type side that is arranged at the active region and form the part of device active region and be adjacent to the second layer that this ground floor is provided with, the composition of the second layer is different from ground floor, make the electron gas area definition between the ground floor and the second layer at the interface.Ground floor does not constitute the part of active region, and electronics gas area (on the n of active region side) outside the active region

Ground floor can be in close proximity to second layer setting.This with the electronics gas area place as close as possible active region, thereby the improvement of the maximum possible that the electronics that enters the active region injects is provided, and therefore provide the improvement of the maximum possible of device optical efficiency.

In the use, the electronics gas area can comprise two-dimensional electron gas or three-dimensional electronic gas.

Ground floor can be the GaN layer, and perhaps it can be the InGaN layer.The second layer can be the AlGaN layer.

Can deliberately do not mixed in the electronics gas area.Comprise under the above-mentioned first and second layers situation that in the electronics gas area this requires the ground floor and the second layer deliberately not to be mixed.

Perhaps, the electronics gas area can be doped the n type.Comprise under the above-mentioned first and second layers situation that in the electronics gas area this requires in the ground floor and the second layer at least one to be doped the n type.Silicon is an example of suitable alloy.

Device can be a light-emitting diode, and perhaps it can be a semiconductor laser device.

Description of drawings

By illustrated examples preferred feature of the present invention is described referring now to accompanying drawing, wherein:

Fig. 1 is (Al, Ga, In) schematic cross sectional views of the known semiconductor Laser Devices of making in the N system.

Fig. 2 is the schematic conduction band diagrammatic sketch according to device of the present invention.

Fig. 3 is the schematic cross sectional views according to the semiconductor laser device of the embodiment of the invention.

Fig. 4 is the schematic cross sectional views according to the light-emitting diode of the embodiment of the invention.

Fig. 5 shows the Output optical power of light-emitting diode of the present invention.

Fig. 6 is the schematic cross sectional views of the semiconductor layer structure of the method according to this invention growth.

Fig. 7 shows the optical output power as the LED with general structure shown in Figure 4 of the function of the growth temperature of low AlGaN barrier layer.

Fig. 8 shows the optical output power as the LED of having of the function of annealing temperature general structure shown in Figure 4.

Embodiment

Fig. 2 is the schematic representation of the conduction band of luminescent device according to an embodiment of the invention.This device has and is used for photoemissive active region.The active region comprises quantum well layer 11, between per two adjacent quantum well layers 11 barrier layer 12 is set.Fig. 2 illustrates the active region with three quantum well layers 11 and two barrier layers 12, but the invention is not restricted to the active region of this special construction.

The active region further comprises and and then is arranged at first barrier layer 15 under the minimum quantum well layer 11 and and then is arranged at second barrier layer of going up most on the quantum well layer 11 16.In the example of Fig. 2, first and second barrier layers are respectively the AlGaN layers.、

The device portions that is positioned at 10 left sides, active region among Fig. 2 is the n type side of device, and the device portions that is positioned at the right of active region 10 among Fig. 2 is the p type side of device.N type contact (not shown) is arranged in the n type side of device and p type contact (also not shown) is arranged in the p type side of device.

According to the present invention, electronics gas area 13 is arranged in the device, on the n type side of active region 10, and outside the active region.When device is in the work, have at least 6 * 10 ¹³Cm ^-2The electron gas of sheet electron density be formed in the electronics gas area 13.

In the embodiment of Fig. 2, device comprises the ground floor 14 on the n type side that is arranged at active region 10.Ground floor 14 preferably directly is adjacent to first barrier layer 15.The composition of ground floor 14 is different with first barrier layer 15.Because the difference of forming, the conduction band level of first barrier layer 15 is not equal to the conduction band level of ground floor 14, thereby as is known, potential well is formed between the ground floor 14 and first barrier layer 15 at the interface.Potential well forms electronics gas area 13-when device is in the work, gathers in the potential well at the interface of electronics between the ground floor 14 and first barrier layer 15, thereby forms electron gas at the interface at this.The electron confinement of the electron gas on the direction vertical with the potential well plane (that is, from left to right direction among Fig. 2) determined by the potential well width, and if this potential well enough narrow, then the electron gas in the potential well will be two-dimensional electron gas (2DEG).

First barrier layer 15 is preferably thinner relatively.This has guaranteed to make separately as far as possible little (equaling the thickness of the second layer 15) between the quantum well of electron gas and active region, and therefore provides the more effective electronics of the quantum well from the electron gas to the active region to inject, thus the optical efficiency of boost device as much as possible.

The device of Fig. 2 is made in nitride material system.As an example, device can be in that (Al, Ga In) make in the N system, and quantum well layer 11 can be that InGaN layer and barrier layer 12 can be the GaN layers in this situation.The ground floor and

first barrier layer

14,15 that limit electronics gas area 13 can be respectively GaN layer and AlGaN layer, and as shown in Figure 2, perhaps they can be respectively InGaN layer and AlGaN layer.If ground floor 14 is InGaN layer, then In _xGa _1-xThe OK range of the indium mole fraction among the N is 0≤x≤0.1.

Second barrier layer 16 for example can be made of the AlGaN that the p type mixes.

The aluminum concentration of first barrier layer 15 be preferably 0.3 or below; That is, first barrier layer 15 has composition Al _xGa _1-xN, wherein 0＜x≤0.3.Use has the layer of this relatively low aluminum concentration will be avoided and the shortcoming of using AlN layer with high al mole fraction or AlGaN layer to be associated, thereby still can obtain the second best in quality device.Especially, al mole fraction reaches 0.3 AlGaN layer can not caused generating obvious stress in the device, forms the dislocation of significant amounts, can not cause significantly in conjunction with unwanted impurity yet.Second barrier layer 16 preferably also has composition Al _xGa _1-xN, wherein 0＜x≤0.3.

Select the thickness of first barrier layer 15, so that the electronics gas area is formed between first barrier layer 15 and the ground floor 14 at the interface.For realizing this point, the thickness of first barrier layer 15 is preferably at least between the 5nm, and preferably less than 50nm.This thickness range provides the maximum optical output power of device.Thickness greater than the 20nm operative constraint of electronics in the electronics gas area (thereby provide) preferably is provided ground floor 14, less than 3 μ m (although the thickness of ground floor 14 do not have the thickness of first barrier layer 15 important like that).These thickness ranges that are suitable for obtaining having the electron gas of high sheet electron concentration have been found.Especially, if the thickness of first barrier layer 15 is significantly less than 5nm or obviously greater than 50nm, then can not electron gain gas.

The electron gas that forms in the electronics gas area 13 is that two-dimensional electron gas or three-dimensional electronic gas mainly are to be determined by the thickness of first barrier layer 15.If the thickness of first barrier layer 15 is less than about 20nm, then 2-DEG may be formed in the electronics gas area, and if the thickness of first barrier layer 15 greater than about 20nm, then 3-DEG may be formed in the electronics gas area 13.

The ground floor 14 of the device architecture of Fig. 2 and first barrier layer 15 can deliberately not mixed.If device is made according to method described below, then can obtain to have the electron gas of high sheet electron concentration, even nominally the ground floor 14 of the device of Fig. 2 and first barrier layer 15 all do not mix.This is a shortcoming, so because provide heavily doped layer can make the device performance deterioration in device architecture because alloy can diffuse into other layer of device with not needing.

Perhaps, as needs, in the ground floor 14 of Fig. 2 device architecture and first barrier layer 15 one or both can be by intentional Doped n-type.For example, if ground floor 14 is thick-layers, the ground floor that then mixes is desirable to reduce its resistance.The formation of electron gas is influenced by the doped level of ground floor 14 not obviously in the electronics gas area 13.

Fig. 3 is the schematic cross sectional views in conjunction with semiconductor laser diode of the present invention.Laser diode 17 has substrate 18 and grows in this on-chip resilient coating 19.In the example of Fig. 3, substrate 18 is GaN substrates, and resilient coating 19 is n type GaN layers, and its thickness is 250nm.Silicon is suitable alloy.

The n type coats district 20 and is arranged on the resilient coating 19.In the example of Fig. 3, the n type coats that district 20 has superlattice structure and the floor of the AlGaN with 0.12 al mole fraction that interlocked by the floor with GaN constitutes.There is the thickness of 900nm in the coating district of Fig. 3.But Laser Devices are not limited to special shape or the thickness that n type shown in Figure 3 coats the district.

Ground floor 14 grows on the n type coating layer 20.In the embodiments of figure 3, ground floor 14 is GaN layers that the n type mixes, and thickness is 100nm.Silicon is used as alloy.

Active region 10 grows on the ground floor 14.In the example of Fig. 3, first barrier layer 15 is the thick Al of 15nm _0.1Ga _0.9N layer, each quantum well layer 11 all are the thick In of 2nm _0.1Ga _0.9The N layer, barrier layer 12 all is the layer of the thick GaN of 15nm in the middle of each, and second barrier layer 16 is the thick Al of 5nm _0.15Ga _0.85The layer of N.In the embodiments of figure 3, each layer of active region 10 is not deliberately mixed.

Optical guidance district 21 grows on the active region.In the embodiments of figure 3, optical guidance district 21 is GaN floor, and it is doped p type and the thickness with 100nm.Magnesium is suitable p type alloy.

The p type coats district 22 and is arranged in the optical guidance district 21.In the example of Fig. 3, the p type coats that district 22 has superlattice structure and the floor of the AlGaN with 0.12 al mole fraction that interlocked by the floor with GaN constitutes.The p type of Fig. 3 coats the thick 500nm in district.But Laser Devices are not limited to special shape or the thickness that p type shown in Figure 3 coats the district.

P type cap rock 23 is arranged at the p type and coats in the district 22.In the embodiments of figure 3, cap rock 23 is thick layers of 20nm of the GaN of doped p type.Magnesium suitable alloy.

Hard contact (not shown among Fig. 3) is arranged on the n side and p side of active region 10.The contact can be arranged on the upper surface of following and cap rock 23 of substrate 18 easily.

Fig. 4 shows in conjunction with LED24 of the present invention.LED24 has substrate 18.In the embodiment of Fig. 4, substrate is the superincumbent sapphire substrate of its (0001) face.

Resilient coating 19 grows on the substrate 18.In the embodiment of Fig. 4, resilient coating 19 is GaN layers that the n type mixes, thick 4 μ m.Silicon is suitable alloy.

Active region 10 grows on the resilient coating 19.The active region of the LED of Fig. 4 is equal to the active region of the laser diode of Fig. 3, and no longer repeats its description.

The LED24 of Fig. 4 further comprises the cap rock 25 that grows on the active region 10.Among Fig. 4, cap rock 25 is GaN layers that the p type mixes, thick 300nm.Magnesium is suitable alloy.

Hard contact (not shown among Fig. 4) is arranged on the n side and p side of active region 10.The contact can be arranged on the upper surface of following and cap rock 25 of substrate 18 easily.

How the optical output power that Fig. 5 shows the LED that combines electronics of the present invention gas area depends on the sheet carrier density (during 300K) of electron gas in the electronics gas area.The value of power output shown in Figure 5 is from having general structure shown in Figure 4 but comprises the LED of electron gas of different sheet electron concentrations and obtain.The value of sheet electron concentration is to utilize structure shown in Figure 6 29 to measure by Hall effect on the equivalent electrons gas to obtain Al in structure 29 _yGa _1-yN layer 26 is arranged at In _xGa _1-xMake electronics gas area 28 be formed at them at the interface on the N layer 27.GaN and the

AlGaN layer

26,27 of Fig. 6 structure 29 that is used for obtaining the sheet electron concentration of specific electron gas has composition and the thickness identical with first barrier layer 15 with the ground floor 14 of measuring the LED that the power output that LED produced with specific electron gas uses.Therefore, two structures of separating are used for obtaining each data point of Fig. 5.

As shown in Figure 5, the optical output power of LED increases with the increase of the sheet carrier concentration of electron gas.There is not the conventional equipment of electronics gas area to have the power output of about 50 μ W (0.05mW) expectation.Along with the increase of the light output of the sheet concentration of electron gas is initially relatively low, but the curve of Fig. 5 for (when the 300K) from about 4.5 * 10 ¹³Cm ^-2To about 6 * 10 ¹³Cm ^-2Scope in the sheet electron concentration have " elbow ".For when the 300K greater than 6 * 10 ¹³Cm ^-2The sheet electron concentration, the output of the light of LED increases fast along with the increase of the sheet electron concentration of electron gas.Therefore, preferably, the electron gas in the electronics gas area 13 has at least 6 * 10 when 300K ¹³Cm ^-2The sheet electron concentration.

Can believe: for luminescent device of the present invention, the relation between the sheet electron concentration of optical output power and electron gas will always have general type shown in Figure 5.Particularly, the relation between optical output power and the sheet electron concentration is supposed to have one " elbow ", and the output of the light of device increases fast along with the increase of the sheet electron concentration of electron gas more than it.Therefore, in the use when being included in 300K at least 6 * 10 ¹³Cm ^-2The electronics gas area of electron gas of sheet electron density should form device with high luminous power output.

A kind of method of the device architecture of shop drawings 2 is described now.For the semiconductor layer structure of the Fig. 2 that grows,, subsequently it is introduced in the growth chamber of grower by prepared by any suitable process and the suitable substrate (not shown among Fig. 2) of cleaning.A kind of suitable substrate is the model substrate that is made of the GaN layer that the n type of growing on the process for sapphire-based substrate mixes, but the invention is not restricted to any special substrate.The present invention also is not limited to any special grower, and device can be made by any conventional semiconductor growth techniques, such as MBE (molecular beam epitaxy) or MOVPE (metal organic vapor).

The one or more layers of growth on substrate are such as resilient coating, n type coating layer and n type light guide layer in the situation of laser diode.The growth of these layers does not constitute a part of the present invention and does not further describe.

Subsequently, growth regulation one deck 14 (In _xGa _1-xThe N layer).In _xGa _1-xN layer 14 is grown under at least 500 ℃ growth temperature.(general, in growth course, substrate is heated, and " growth temperature " is defined as the temperature of substrate.)

Subsequently, AlGaN layer 15 is directly grown in In _xGa _1-xOn the N layer 14.AlGaN layer 15 is grown with at least 500 ℃ growth temperature.The growth temperature of AlGaN layer 15 in principle can with In _xGa _1-xThe growth temperature difference of N layer 14.The growth temperature of AlGaN layer 15 is preferably less than 750 ℃, because the electron gas that has high sheet electron concentration succeeded by one of annealing relatively low growth temperature formation as described below; Can obtain to have the electron gas of high sheet electron concentration (during 300K) in this way, for example be higher than 6 * 10 ¹³Cm ^-2And even reach 1 * 10 ¹⁴Cm ^-2Or more than.The growing method of describing with reference to the example 1 of following table 1 is greater than 1 * 10 in the time of can obtaining 300K ¹⁴Cm ^-2The example of growing method of electron gas of sheet electron concentration.

Make 15 annealing of AlGaN layer with at least 800 ℃ and the temperature bigger at least 50 ℃ subsequently than its growth temperature.This annealing is carried out (this is known as on-the-spot annealing) by the process of stopping growing and with the preferred temperature that the temperature in the growth chamber is brought up to annealing AlGaN layer in the growth chamber of grower.Perhaps, substrate can be shifted out from growth chamber to allow outside growth chamber, anneal (this is known as outside annealing).As mentioned above, the electronics gas area is arranged at AlGaN layer 15 and In _xGa _1-xAt the interface, and the effect of annealing steps is the sheet electron concentration that increases the electron gas that forms in the electronics gas area between the N layer 14.Below provide the further details of annealing steps.

If annealing steps is outside annealing steps, then after finishing annealing steps, substrate is turned back in the growth chamber.

Subsequently, grown quantum trap layer 11 and barrier layer 12 are to form active region 10.P type layer 16 grows on the active region 10 subsequently.

Subsequently, other layer of growth on p type layer 16 is such as cap rock and/or p type contact layer, to finish this device.The growth of these succeeding layers does not constitute a part of the present invention and does not further describe.

At last, substrate is cut into individual devices, and contact (step of cut crystal and formation contact does not constitute a part of the present invention and do not further describe) is set.

In the example of above-mentioned Fig. 2, first barrier layer 15 is AlGaN layers.Yet, the invention is not restricted to the AlGaN layer as first barrier layer, and first barrier layer can be the semi-conductive layer of any suitable aluminiferous nitride that for example comprises AlGaInN in principle.

In the above-described embodiments, ground floor 14 is adjacent to first barrier layer 15.Though this is desirable, according to the present invention, even thin intermediate layer grows between the ground floor 14 and first barrier layer 15 electron gas that also can obtain to have high sheet carrier concentration.For example, the InGaN quantum well layer can grow between the ground floor 14 and first barrier layer 15, and this layer can have the typical thickness of about 10nm.As another example, silicon layer (being called the Δ layer) can grow between the ground floor 14 and first barrier layer 15, and silicon Δ layer will have the typical thickness of about 0.5nm.

Provide the more details of annealing steps referring now to Fig. 6.As previously mentioned, the semiconductor layer structure 29 of Fig. 6 comprises and grows in In _xGa _1-xAl on N (0≤x≤1) layer 27 _yGa _1-yN (0＜x≤1) layer 26.Electronics gas area 28 is formed at Al _yGa _1-yN layer 26 and In _xGa _1-xBetween the N layer 27 at the interface.Among Fig. 6, In _xGa _1-xN layer 27 is illustrated as the GaN layer, but layer 27 can have the indium mole fraction of non-zero alternatively.Indium mole fraction is preferably in the scope of 0≤x≤0.05.

For the semiconductor layer structure 29 of the Fig. 6 that grows, by prepared by any suitable process and clean suitable substrate (not shown among Fig. 6), subsequently its is introduced the growth chamber of grower.A kind of suitable substrate is the model substrate that is made of the GaN layer that the n type of growing on the process for sapphire-based substrate mixes, but the invention is not restricted to any special substrate.The present invention also is not limited to any special grower, and the present invention can be by any conventional semiconductor growth techniques realization, such as MBE (molecular beam epitaxy) or MOVPE (metal organic vapor).

In _xGa _1-xN layer 27 grows on the substrate subsequently.In _xGa _1-xN layer 27 is with the growth of at least 500 ℃ growth temperature, and preferably with at least 600 ℃ growth temperature.(general, at growth course heating substrate, and " growth temperature " is defined as the temperature of substrate.)

Layer structure 29 at Fig. 6 is incorporated under the situation of device architecture, and one or more layers can be at growth In _xGa _1-xGrow on the substrate before the N layer 27.The growth of any this insert layer does not constitute the part of growing method of the present invention and does not further describe.

In the present embodiment, the nitride semiconductor layer 26 (Al that contain aluminium _yGa _1-yThe N layer) grows in In subsequently _xGa _1-xOn the N layer 27.Al _yGa _1-yN layer 26 is with the growth of at least 500 ℃ growth temperature, and preferably with at least 600 ℃ growth temperature.Al _yGa _1-yThe growth temperature of N layer 26 can be different from In in principle _xGa _1-xThe growth temperature of N layer 27.In one embodiment, Al _yGa _1-yN layer 26 can have the thickness of 20nm and 0.1 Al molar fraction, but the invention is not restricted to Al _yGa _1-yThis special thickness of N layer 26 or Al molar fraction.

In addition, for the reason of following explanation, the growth temperature of nitride semiconductor layer 26 is preferably 750 ℃ or following.

Nitride semiconductor layer preferably is directly grown in In _xGa _1-xOn the N layer 27, make nitride semiconductor layer and In _xGa _1-xThere is not insert layer between the N layer 27.But, even thin intermediate layer (such as above-mentioned thin InGaN quantum well layer or silicon Δ layer) grows in nitride semiconductor layer and In _xGa _1-xBetween the N layer, also can obtain electron gas by method of the present invention with high sheet carrier concentration.

According to the present invention, the nitride semiconductor layer 26 (Al in the present embodiment _yGa _1-yThe N layer) anneals with at least 800 ℃ and the temperature that is higher than its growth temperature subsequently.The temperature of annealing nitride semiconductor layer 26 is preferably high at least 50 ℃ than the growth temperature of nitride semiconductor layer 26.As mentioned above, the electronics gas area is arranged at nitride semiconductor layer 26 and In _xGa _1-xAt the interface, and the effect of annealing steps of the present invention will increase the sheet electron concentration of the electron gas that forms in the electronics gas area between the N layer 27.

The typical duration of annealing steps is one minute.It should be noted that substrate temperature to be increased to the speed of annealing temperature of expectation and the speed that substrate temperature reduces should keep enough low behind annealing steps, with the tangible thermal stress of bringing out in the layer of avoiding causing in the substrate or growing on the substrate; This is applied to on-the-spot annealing and both are annealed in the outside.The temperature ramp speed of having found to be no more than 40-50 ℃/minute is suitable for on-the-spot annealing, can be used for outside annealing and reach 100 ℃/minute temperature ramp speed.As employed term here, the duration of annealing steps is the time under the annealing temperature, and does not comprise and make temperature ramp upwards reach annealing temperature and follow-uply make temperature ramp required time downwards.Therefore, although the duration of annealing steps is generally one minute or a few minutes, but for example to spend about 6-10 minute so that substrate temperature is risen to 800 ℃ annealing temperature from 500 ℃ growth temperature in the situation of annealing at the scene, and behind annealing steps other about 6-10 minute of cost substrate temperature is reduced to the suitable temperature of the next one layer of being used to grow.

To be incorporated in the layer structure 29 of Fig. 6 under the situation of device architecture, one or more layers can grow in Al _yGa _1-yOn the N layer 26, and/or one or more layer can be grown before growing GaN layer 27.For example, the active region can grow on layer structure 29.Perhaps, layer in addition can grow on layer structure 29 being provided for photoemissive active region, and it combines nitride semiconductor layer 26 (but non-GaN layer 27) to obtain the device of the above general type of describing with reference to figure 2.The growth of any this further layer does not constitute the part of growing method of the present invention, and further is not described.

Annealing steps can be " scene " annealing steps of implementing in the growth chamber of grower, and perhaps it can be that annealing steps is shifting out this layer structure " outside " annealing steps that implement the back from growth chamber.In both of these case, the annealing steps Al that can and then grow _yGa _1-yImplement after the N layer 26, perhaps it can with one or more other layer growths in Al _yGa _1-yImplement after on the N layer 26.Be incorporated under the situation of device architecture in the layer structure with Fig. 6, Al and then grows _yGa _1-yCarry out the advantage that annealing steps has possibility, i.e. Al after the N layer 26 _yGa _1-yAny layer of growth will not be annealed on the N layer 26, and mean that each layer with to device anneals having grown to anneal behind the entire infrastructure.But, being incorporated in the situation of device architecture in layer structure Fig. 6, Al and then grows _yGa _1-yThe shortcoming of carrying out annealing steps after the N layer 26 is: the process that must stop growing is to allow to carry out annealing steps.For example in the large-scale production of device annealing many batches of wafers situation in, outside annealing steps is preferred.

Result of the present invention is shown in the table 1.

Table 1

The AlGaN growth temperature (℃)	The AlGaN annealing temperature (℃)	300K sheet electron concentration (cm ^-2)	300K electron mobility (cm ²V ^-1s ^-1)	300K sheet resistor ()
The AlGaN growth temperature (℃)	The AlGaN annealing temperature (℃)	300K sheet electron concentration (cm ^-2)	300K electron mobility (cm ²V ^-1s ^-1)	300K sheet resistor ()	630	880	1×10 ¹⁴	200	330
630	There is not annealing	1×10 ¹³	830	770	630	880	1×10 ¹⁴	200	330
630	There is not annealing	1×10 ¹³	830	770	900	There is not annealing	2×10 ¹³	600	600

First clauses and subclauses of table 1 relate to the semiconductor layer structure by method growth of the present invention, wherein Al _yGa _1-yN layer 26 is in growth under 630 ℃ the growth temperature and on-the-spot annealing under 880 ℃ growth temperature.In table 1 second and the 3rd clauses and subclauses relate to comparative example-Al in second entry _yGa _1-yThe N layer is grown under 630 ℃ growth temperature but is not annealed, Al in the 3rd clauses and subclauses _yGa _1-yThe N layer is grown under 900 ℃ higher growth temperature but is not annealed.

The first entry 1 of table 1 uses the semiconductor layer structure manufacturing with unadulterated GaN template substrate.In the MBE chamber under the ammonia steam, nominally the thick unadulterated GaN layer of 1 μ m grows on the substrate under 900 ℃ growth temperature.Subsequently, once more in the MBE chamber under the ammonia steam, growth temperature is reduced to 630 ℃, nominally and under 630 ℃ growth temperature growth 20nm thick unadulterated Al _0.1Ga _0.9The N layer.In 10 minutes time cycle, located to keep one minute, after this in 15 minutes time cycle, sample is cooled to temperature less than 200 ℃ with the temperature increase to 880 of sample ℃ and at 880 ℃.

As shown in table 1, method of the present invention provides the electron gas that has obviously greater than the sheet electron concentration of the sheet electron concentration of the electron gas that obtains with growing method relatively.Growth that provides in the first entry of use table 1 and annealing temperature, the sheet electron concentration of the electron gas that obtains by method of the present invention is 1 * 10 ¹⁴Cm ^-2When temperature (300K measure).Comparison growing method shown in the second and the 3rd clauses and subclauses of table 1 has produced has 1 * 10 respectively ¹³Cm ^-2Or 2 * 10 ¹³Cm ^-2The electron gas (under 300K, measuring once more) of sheet electron concentration.Be used for by the possible mechanism that provided by the invention electron concentration increases be: during annealing steps at Al _yGa _1-yIn the N layer 26 and/or its surface forms the nitrogen room.Therefore the room causes higher carrier concentration of electron gas to the extra electronics of electron gas contribution.

Can see: the electron mobility of the electron gas that obtains by the inventive method is lower than the electron mobility of the electron gas that the comparative approach that provides in the second and the 3rd clauses and subclauses by table 1 obtains slightly.But the factor that reduces electron mobility obviously is less than the factor that increases the sheet electron concentration.

The result of table 1 is to use layer structure shown in Figure 6 to obtain.The nitride layer 26 that contains aluminium is AlGaN layers, its al mole fraction be 0.1 and thickness be 20nm, and and then grow and be annealed after the AlGaN layer.The GaN layer is grown when 900 ℃ temperature and is had the thickness of 1 μ m, although the growth temperature of GaN layer and its thickness can obviously not influence the electron concentration of the electron gas that is obtained.

As shown, the result in first of table 1 row is to use 880 ℃ annealing temperature to obtain.For on-the-spot annealing steps, annealing temperature is preferably in 800 ℃ to 1000 ℃ temperature range (although higher annealing temperature can be used for outside annealing steps).At the scene in the situation of annealing steps, found that about 880 ℃ annealing temperature forms the highest electron concentration of electron gas, and use apparently higher than or be lower than 880 ℃ annealing temperature and form lower sheet carrier concentration.Under the situation of using on-the-spot annealing, therefore annealing temperature is preferably about 880 ℃ especially.

The result of first row of table 1 is to use the annealing steps with 1 minute duration to obtain.Annealing steps is not limited to this duration, and the duration of annealing steps can be shorter than or be longer than 1 minute.Generally, annealing temperature is high more, required annealing time short more (being for on-the-spot and outside annealing both).

Find: the causing and the reducing of sheet carrier concentration of annealing steps than long duration, and this may be the reason owing to surperficial roughening.Therefore, for on-the-spot and outside annealing, the duration of annealing steps is preferably less than 1 hour.In many cases, can consider to be shorter than 1 hour annealing time.For many annealing temperatures, 10 minutes or following annealing time perhaps even 2 minutes or following, will provide higher sheet carrier concentration.

Table 2 shows further result of the present invention, and the situation that contains the nitride layer 26 of aluminium for outside annealing (in this example, is Al once more _yGa _1-yThe N layer).

Table 2

Outside annealing temperature (℃)	300K sheet carrier concentration (cm ^-2)	300K electron mobility (cm ²V ^-1s ^-1)
Outside annealing temperature (℃)	300K sheet carrier concentration (cm ^-2)	300K electron mobility (cm ²V ^-1s ^-1)	There is not annealing	2.4×10 ¹³	598
1000	3.0×10 ¹³	451	There is not annealing	2.4×10 ¹³	598
1000	3.0×10 ¹³	451	1050	4.7×10 ¹³	263

1100

6.0×10 ¹³

186

First entry in the table 2 relates to a comparative example, wherein Al _yGa _1-yN layer 26 is not annealed, and second, third and the 4th clauses and subclauses show the effect of outside annealing steps under the temperature of 1000 ℃, 1050 ℃ and 1100 ℃ respectively.Can see that the effect of annealing steps has been to increase the sheet electron concentration (comparing with the sheet electron concentration that obtains under the situation that does not have annealing steps) of the electron gas that is obtained.The temperature of annealing steps is big more, and the sheet electron concentration of the electron gas that is obtained is big more, and the generation of 1100 ℃ annealing temperature has 6.0 * 10 ¹³Cm ^-2The sheet electron concentration.The increase of sheet electron concentration may be because Al _yGa _1-yThe nitrogen room that the surface of N layer 26 produces produces.

The result of table 2 is to use the layer structure identical with the layer structure of table 1 to obtain, wherein the thick Al of 20nm _0.1Ga _0.9N is as aluminous layer 26.Each the comfortable 900 ℃ of growth down of GaN layer and AlGaN layer.In carrying out each situation of annealing steps, all has 1 minute duration.

In more detail, the 4th of table 2 the clauses and subclauses are to use the semiconductor structure with unadulterated GaN template substrate to obtain.In the MBE chamber under the ammonia steam, nominally the thick unadulterated GaN layer of 1mm under 900 ℃, grow on the substrate, and subsequently in the MBE chamber under the ammonia steam, equally with 900 ℃ of thick unadulterated Al of growth 20nm _0.1Ga _0.9The N layer.Then, in 15 minutes time cycle, sample is cooled to 200 ℃ or following temperature, subsequently it is shifted out and insert the rapid thermal annealing device from the MBE chamber.In the rapid thermal annealing device, this sample was heated to 1100 ℃ temperature in 1 minute under blanket of nitrogen, be annealed 1 minute with 1100 ℃ under blanket of nitrogen, and was cooled to 300 ℃ or following temperature subsequently under blanket of nitrogen in 1 minute.

Can see that the sheet carrier concentration of table 2 is lower than those of table 1.This is owing to the growth temperature of comparing AlGaN layer in the table 2 (900 ℃) with table 1 (630 ℃) is higher.As mentioned above, the growth temperature of nitride semiconductor layer is preferably 750 ℃ or following, and is preferably 700 ℃ or following especially.Find: under the situation that all other factorses maintenances are constant, the growth temperature of the 500-750 ℃ of interior nitride semiconductor layer of scope forms the highest electron concentration of institute's electron gain gas.If (but it should be noted that and make annealing temperature enough higher that any growth temperature for greater than 500 ℃ nitride semiconductor layer has 6 * 10 in the time of can obtaining 300K ¹³Cm ^-2The electron gas of sheet carrier concentration, although electron mobility can be lower for the growth temperature of 500 ℃-750 ℃ of scopes.) as mentioned above, can believe: the high sheet electron concentration that the present invention obtained is owing in the nitride semiconductor layer 26 during the annealing steps and/or the nitrogen room of its surface--and can further believe: scope forms higher nitrogen vacancy concentration in the growth temperature of 500-750 ℃ nitride semiconductor layer.

In addition, expectation reduces the nitrogen pressure that is used for outside annealing and will form higher sheet carrier concentration for given outside annealing temperature.Can believe: need in the AlGaN layer, form the electron gas that the nitrogen room has high sheet electron density with formation, and the nitrogen pressure that minimizing is used for annealing the outside can form more rooms.Expectation also can obtain to have 6 * 10 for the outside annealing temperature below 1100 ℃ ¹³Cm ^-2Or the electron gas of above sheet electron density, reduce the nitrogen pressure that is used for outside annealing.

In the method for the invention, nitride semiconductor layer (that is Al among Fig. 6 embodiment, _yGa _1-yN layer 26) preferably has greater than 5nm and less than the thickness of 50nm.In _xGa _1-xN layer 27 preferably has greater than 20nm but less than the thickness of 3 μ m.Found that these thickness ranges are suitable for obtaining to have the electron gas of high sheet electron concentration.If the thickness of nitride semiconductor layer obviously at 5nm outside the scope of 50nm then can not electron gain gas, and if thickness is significantly less than 20nm then InGaN layer 27 can not retrain electron gas effectively.The thickness of nitride semiconductor layer has determined that electron gas is that two dimension or three-dimensional electronic gas-as the thickness of enough nitride semiconductor layers then more may be three-dimensional electronic gas greater than about 20nm, if the thickness of nitride semiconductor layer is less than about 20nm then more may be two-dimensional electron gas.

In the method for the invention, Al _yGa _1-yN layer 26 preferably has 0.3 or following Al molar fraction y.The method according to this invention is used the AlGaN layer with this low al mole fraction still to allow to generate and is had 6 * 10 ¹³Cm ^-2Or the electron gas of above sheet carrier concentration, but will avoid and the shortcoming of using AlN layer with high al mole fraction or AlGaN layer to be associated, thereby still can obtain the second best in quality device.Particularly, al mole fraction reaches 0.3 AlGaN layer can not caused obviously generating stress in the device, obviously forms many dislocation, and obviously in conjunction with unwanted impurity.

The In of layer structure of Fig. 6 can deliberately not mix _xGa _1-xN layer 27 and Al _yGa _1-yN layer 26.Method of the present invention does not rely on these layers that mix, and if the In of the layer structure of Fig. 6 _xGa _1-xN layer 27 and Al _yGa _1-yNominally N layer 26 does not all mix, method of the present invention can obtain to have the electron gas of high sheet electron concentration.Especially, when the layer structure with Fig. 6 was incorporated in electronics or the optoelectronic device structure, this was favourable, because because alloy does not diffuse into other layer of device with not needing, provide the performance of heavily doped layer meeting deterioration device in device architecture.

Yet, as needs, the In of the layer structure of the Fig. 6 that can intentionally mix _xGa _1-xN layer 27 and Al _yGa _1-yIn the N layer 26 one or both.If expectation is with In _xGa _1-xN layer 27 and Al _yGa _1-yIn the N layer 26 one or both are doped to the n type, and then a kind of suitable alloy is a silicon.For example, if thick GaN layer not doping can have high resistance, not Doped GaN layer that then will be thicker is incorporated into device architecture and will forms and have high-resistance device.Therefore, preferred Doped GaN layer is to reduce its resistance.

In the example of Fig. 6, the nitride semiconductor layer that contains aluminium is the AlGaN layer.The invention is not restricted to this, and the nitride semiconductor layer that contains aluminium for example can be Al _yGa _zIn _1-y-zN layer (0＜y≤1,0≤z≤1).Al mole fraction y is preferably less than 0.3.

As mentioned above, InGaN layer 27 is preferably at least 500 ℃ with the growth temperature that contains the nitride semiconductor layer 26 of aluminium.500 ℃ growth temperature is the lowest temperature that is used for such as the MBE growth of the material of InGaN and AlGaN, and can not have good quality of materials with the layer that is lower than 500 ℃ growth temperature growth.

1050 ℃ temperature is the approximate temperature upper limit that is used for the MOCVD growth of AlGaN.Therefore, the

layer

26 and 27 in the layer structure of Fig. 6 used from approximate 500 ℃ of growth temperatures in approximate 1050 ℃ of scopes can provide good quality of materials, and no matter employed growing technology.Its exception is that 850 ℃ temperature is the approximate temperature upper limit that is used for such as the growth that contains phosphide material of InGaN or AlGaInN, and this is owing to be difficult to indium is incorporated into described material under obviously greater than 850 ℃ temperature.For the growth that contains the indium layer, for example, if layer 27 is if that InGaN layer or the nitride layer 26 that contains aluminium are AlGaInN layers, then the scope of application can provide good quality of materials from the growth temperature in approximate 500 ℃ to approximate 850 ℃, and no matter employed growing technology.

In addition, being used in preferred 550 ° of-700 ℃ of scopes contains the growth temperature of the nitride layer of aluminium.Found that this temperature range forms the electron gas with the highest carrier concentration.Proposed this be because under this temperature-the inherent growing period of this temperature range formed the nitrogen room, ammonia convert to Nitrogen Atom a little less than, therefore the Nitrogen Atom that can be used for growing is less.

Fig. 7 shows the optical output power as the LED with general structure shown in Figure 4 of the function of the growth temperature of low AlGaN barrier layer 15.Can see that all three growth temperatures (600 ℃, 630 ℃ and 650 ℃) that are used for low AlGaN barrier layer 15 provide higher optical output power, wherein 630 ℃ growth temperature provides the highest optical output power to LED.This shows that all three growth temperatures have all formed the electron gas with high sheet carrier concentration, and wherein 630 ℃ the growth temperature that is used for low AlGaN barrier layer 15 is that electron gas has provided the highest sheet carrier concentration.

Found to provide the annealing temperature of the highest carrier concentration to depend on the thickness of the nitride layer that contains aluminium.Propose, this is owing to the layer combination of the formation in crystallization and surface nitrogen room again occurred.For the described typical thickness of application of the nitride layer that is used to contain aluminium, found that 850 ℃ to 950 ℃ annealing region provides the highest sheet carrier concentration.

Fig. 8 shows the optical output power as the LED of having of annealing temperature function general structure shown in Figure 4.Can see that 825 to 925 ℃ of annealing temperatures in the scope provide higher optical output power, have wherein obtained the highest optical output power under 870 to 900 ℃ annealing temperature.This shows under all annealing temperatures of Fig. 8 and has formed the electron gas with high sheet carrier concentration, and the annealing temperature in 870 to 900 ℃ of scopes is that electron gas has provided the highest sheet carrier concentration.

Fig. 7 and 8 result utilize above described structure of first clauses and subclauses and growth conditions for table 1 to obtain, and wherein the growth temperature of AlGaN layer or annealing temperature change as shown in figure.

Therefore, described the present invention, obviously, the present invention can change by many methods.This modification is not considered to depart from the spirit and scope of the invention, and all obvious this modifications of those skilled in the art all are considered within the scope of following claims.

Claims

1. method of making nitride compound semiconductor device, this method may further comprise the steps:

Growth In _xGa _1-xThe N layer, 0≤x≤1 wherein, wherein said In _xGa _1-xThe N layer has the thickness of 20nm at least;

In the growth temperature below at least 500 ℃ and 750 ℃, at described In _xGa _1-xGrowth contains the nitride semiconductor layer of aluminium on the N layer, and the described thickness that contains the nitride semiconductor layer of aluminium makes the electronics gas area be formed at described In thus _xGa _1-xAt the interface, wherein said nitride semiconductor layer has 5nm at least and less than the thickness of 50nm between N layer and the nitride semiconductor layer; And

At least 800 ℃ temperature, described nitride semiconductor layer is annealed.

2. the method for claim 1 is characterized in that, described nitride semiconductor layer is Al _yGa _zIn _1-y-zN layer, wherein 0＜y≤1,0≤z≤1.

3. method as claimed in claim 2 is characterized in that, described Al _yGa _zIn _1-y-zThe N layer has 0＜y＜0.3.

4. the method for claim 1 is characterized in that, described nitride semiconductor layer is Al _yGa _1-yThe N layer.

5. the method for claim 1 is characterized in that, described In _xGa _1-xThe N layer is the GaN layer.

6. the method for claim 1 is characterized in that, described In _xGa _1-xThe N layer has the thickness less than 3 μ m.

7. the method for claim 1 is characterized in that, described In _xGa _1-xThe N layer is not deliberately mixed.

8. the method for claim 1 is characterized in that, described In _xGa _1-xThe N layer mixes with the n type.

9. the method for claim 1 is characterized in that, described nitride semiconductor layer is not deliberately mixed.

10. the method for claim 1 is characterized in that, described nitride semiconductor layer mixes with the n type.

11. the method for claim 1 is characterized in that, also comprises directly at described In _xGa _1-xGrowing nitride semiconductor layer on the N layer.

12. the method for claim 1 is characterized in that, also is included in the described In of growth in the growth chamber _xGa _1-xN layer and described nitride semiconductor layer, wherein said method are included in the described growth chamber described nitride semiconductor layer are annealed.

13. the method for claim 1 is characterized in that, also is included in one or more other (Al, Ga, In) N layers of growth on the described nitride semiconductor layer.

14. the method for claim 1 is characterized in that, in the use, in the 300K temperature, formation has 6 * 10 in the electronics gas area ¹³Cm ^-2The electron gas of above sheet carrier concentration.

15. method as claimed in claim 14 is characterized in that, in the use, and the temperature more than 300K, formation has 1 * 10 in the electronics gas area ¹⁴Cm ^-2The electron gas of sheet carrier concentration.

16. the method for claim 1 is characterized in that, described step with nitride semiconductor layer annealing has the duration below 10 minutes.

17. the method for claim 1 is characterized in that, described device is a luminescent device.

18. method as claimed in claim 17 is characterized in that, described device is a light-emitting diode.

19. method as claimed in claim 17 is characterized in that, described device is a semiconductor laser device.

20. the method for claim 1 is characterized in that, after the described nitride semiconductor layer of and then growing described nitride semiconductor layer is annealed.

21. nitride semiconductor photogenerator, it comprises: be used for photoemissive active region, be arranged at the electronics gas area on the n type side of described active region, be arranged on the n type side of described active region and have the ground floor of 20nm thickness at least and constitute the part of described active region and have 5nm at least and less than the second layer of the thickness of 50nm, the described second layer has the composition different with ground floor and passes through in the growth temperature below at least 500 ℃ and 750 ℃, and then the described second layer of growth and at least 800 ℃ temperature on described ground floor is annealed to the described second layer after the growth the described second layer is set; Thereby, described electronics gas area be defined between the described ground floor and the described second layer at the interface and comprise and have at least 6 * 10 ¹³Cm ^-2The electron gas of sheet electron density.

22. device as claimed in claim 21 is characterized in that, described ground floor is arranged at the described second layer of next-door neighbour.

23. device as claimed in claim 21 is characterized in that, in the use, described electronics gas area comprises two-dimensional electron gas.

24. device as claimed in claim 21 is characterized in that, in the use, described electronics gas area comprises three-dimensional electronic gas.

25. device as claimed in claim 21 is characterized in that, described ground floor is the GaN layer.

26. device as claimed in claim 21 is characterized in that, described ground floor is the InGaN layer.

27. device as claimed in claim 21 is characterized in that, the described second layer is the nitride layer that contains aluminium.

28. device as claimed in claim 27 is characterized in that, the described second layer is the AlGaN layer.

29. device as claimed in claim 21 is characterized in that, described ground floor is not deliberately mixed.

30. device as claimed in claim 21 is characterized in that, described ground floor mixes with the n type.

31. device as claimed in claim 21 is characterized in that, the described second layer is not deliberately mixed.

32. device as claimed in claim 21 is characterized in that, the described second layer mixes with the n type.

33. device as claimed in claim 21 is characterized in that, described device is a light-emitting diode.

34. device as claimed in claim 21 is characterized in that, described device is a semiconductor laser device.