CN100474589C - Semiconductor anti-static protection structure - Google Patents

Semiconductor anti-static protection structure Download PDF

Info

Publication number
CN100474589C
CN100474589C CNB200610118439XA CN200610118439A CN100474589C CN 100474589 C CN100474589 C CN 100474589C CN B200610118439X A CNB200610118439X A CN B200610118439XA CN 200610118439 A CN200610118439 A CN 200610118439A CN 100474589 C CN100474589 C CN 100474589C
Authority
CN
China
Prior art keywords
injection region
type
region
trap
type injection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB200610118439XA
Other languages
Chinese (zh)
Other versions
CN101188237A (en
Inventor
苏庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CNB200610118439XA priority Critical patent/CN100474589C/en
Publication of CN101188237A publication Critical patent/CN101188237A/en
Application granted granted Critical
Publication of CN100474589C publication Critical patent/CN100474589C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Thyristors (AREA)

Abstract

本发明公开了一种半导体防静电保护结构,包括P型衬底,在所述P型衬底上包括有N阱注入区和P阱注入区;在所述N阱注入区和所述P阱注入区内各包括有一个P型注入区和一个N型注入区,所述P型注入区和N型注入区之间被一个氧化层隔离区隔开;所述N阱注入区内的P型注入区与所述P阱注入区的N型注入区被又一个氧化层隔离区隔开,在所述N阱注入区内的P型注入区与所述P阱注入区的N型注入区之间的氧化层隔离区的上面设置有一个多晶硅。本发明有效的降低了可控硅的开启电压,既保证不增加新的工艺条件,又使得用于ESD放电的寄生NPN管与PNP管更容易开启,可以充分发挥其ESD能力。

Figure 200610118439

The invention discloses a semiconductor antistatic protection structure, which comprises a P-type substrate, on which an N-well injection region and a P-well injection region are included; in the N-well injection region and the P-well Each of the implanted regions includes a P-type implanted region and an N-type implanted region, and the P-type implanted region and the N-type implanted region are separated by an oxide layer isolation region; the P-type implanted region in the N-well implanted region The implanted region is separated from the N-type implanted region of the P-well implanted region by another oxide layer isolation region, between the P-type implanted region in the N-well implanted region and the N-type implanted region of the P-well implanted region A polysilicon is disposed above the isolation region of the oxide layer. The invention effectively reduces the turn-on voltage of the thyristor, not only ensures that no new process conditions are added, but also makes it easier to turn on the parasitic NPN and PNP transistors used for ESD discharge, and can fully exert their ESD capabilities.

Figure 200610118439

Description

Semiconductor anti-static protection structure
Technical field
The present invention relates to a kind of semiconductor device structure, especially a kind of semiconductor anti-static protection structure.
Background technology
Current popular technology uses SCR (SCR structure) as ESD (static discharge) protection device, as shown in Figure 1, comprises P type substrate 1, includes N trap injection region 2 and P trap injection region 11 on described P type substrate 1; In described N trap injection region 2, include a P type injection region 3 and a N type injection region 4, separated by an oxide layer isolated area 5 between P type injection region 3 in the described N trap injection region 2 and the N type injection region 4; Also include a P type injection region 6 and a N type injection region 7 in described P trap injection region 11, separated by another oxide layer 8 isolated areas between the P type injection region 6 of described P trap injection region 11 and the N type injection region 7; P type injection region 3 in the described N trap injection region 2 is separated by another oxide layer isolated area 9 with the N type injection region 7 of described P trap injection region 11.ESD electric charge injection end is connected with N type injection region with the P type injection region of described N trap injection region.P type injection region in the P trap injection region, the N trap injection region in the P trap injection region, P-N-P-N four-level semiconductor structure has been formed in the N type injection region in P type injection region in the N trap injection region and the N trap injection region.This also is the structure that causes metal oxide layer transistor latch-up problem.On the protective capacities of ESD, this structure can provide the highest ESD protective capacities under the layout area of minimum.Its cut-in voltage is equivalent to the junction breakdown voltage of N trap injection region and P trap injection region.Because the N trap injects and to have lower doping content, so its puncture voltage has so high puncture voltage up to 30-50V, makes its internal circuit that will protect just to be broken by the ESD electrostatic charge early than its unlatching.
The equivalent electric circuit of this electrostatic-proof protection device can be referring to Fig. 2; include a PNP pipe and a NPN pipe; the emitter of described PNP pipe is received the base stage of this PNP pipe by a resistance; the collector electrode of described PNP pipe is connected to the base stage of described NPN pipe; the base stage of described PNP pipe is also connected to the collector electrode of described NPN pipe; the emitter of described NPN pipe is connected to the base stage of this NPN pipe by another resistance, the grounded emitter of described NPN pipe, and the emitter of described PNP pipe is as the Anode anode.When ESD took place, the electrostatic charge of releasing can cause two parasitic triodes of protection device, i.e. pipe of PNP among Fig. 2 and the conducting of NPN pipe, and as shown in Figure 3, device can produce the phenomenon of Snapback (step recovery).But because the unlatching of these two parasitic triodes needs the reverse PN junction of N trap to puncture, its puncture voltage has so high puncture voltage up to 30-50V, makes its internal circuit that will protect just to be broken by the ESD electrostatic charge early than its unlatching.
Summary of the invention
Technical problem to be solved by this invention provides a kind of semiconductor anti-static protection structure, can when static discharge take place, and parasitic NPN pipe and PNP pipe can in time be opened, and fully device are protected.
For solving the problems of the technologies described above, the technical scheme of semiconductor anti-static protection structure of the present invention is, comprises P type substrate, includes N trap injection region and P trap injection region on described P type substrate; In described N trap injection region, include a P type injection region and a N type injection region, separated by an oxide layer isolated area between P type injection region in the described N trap injection region and the N type injection region; Also include a P type injection region and a N type injection region in described P trap injection region, separated by another oxide layer isolated area between the P type injection region of described P trap injection region and the N type injection region; The N type injection region of P type injection region in the described N trap injection region and described P trap injection region is separated by another oxide layer isolated area, is provided with a polysilicon above the oxide layer isolated area between the N type injection region of P type injection region in described N trap injection region and described P trap injection region.
The present invention isolates the triggering structure of forming by increased polysilicon and oxide layer on the basis of traditional SCR structure, has effectively reduced the silicon controlled cut-in voltage, and has not influenced its protective capability.Both guarantee not increase new process conditions, and made the parasitic NPN pipe and the PNP that are used for esd discharge manage easier unlatching again, can give full play to its ESD ability.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is the structural representation of conventional semiconductor electrostatic-proof protection device;
Fig. 2 is the equivalent circuit diagram of conventional semiconductor anti-electrostatic protecting structure;
Fig. 3 recovers the electric current-voltage curve of phenomenon for producing step;
Fig. 4 is the structural representation of semiconductor anti-static protection structure of the present invention;
Fig. 5 is the equivalent circuit diagram of semiconductor anti-static protection structure of the present invention.
Reference numeral is among the figure, 1.P type substrate; 2.N trap injection region; 3.P type injection region; 4.N type injection region; 5. oxide layer isolated area; 6.P type injection region; 7.N type injection region; 8. oxide layer isolated area; 9. oxide layer isolated area; 10. polysilicon; 11.P trap injection region; 12. earth terminal; 13.ESD electric charge injection end; 14. electric capacity; 15. resistance.
Embodiment
Semiconductor anti-static protection structure of the present invention can comprise P type substrate 1 referring to shown in Figure 4, includes N trap injection region 2 and P trap injection region 11 on described P type substrate 1; In described N trap injection region 2, include a P type injection region 3 and a N type injection region 4, separated by an oxide layer isolated area 5 between P type injection region 3 in the described N trap injection region 2 and the N type injection region 4; Also include a P type injection region 6 and a N type injection region 7 in described P trap injection region 11, separated by another oxide layer 8 isolated areas between the P type injection region 6 of described P trap injection region 11 and the N type injection region 7; P type injection region 3 in the described N trap injection region 2 is separated by another oxide layer isolated area 9 with the N type injection region 7 of described P trap injection region 11, is provided with a polysilicon 10 above the oxide layer isolated area 9 between the N type injection region 7 of P type injection region 3 in described N trap injection region 2 and described P trap injection region 11.
Described polysilicon is connected with circuits for triggering.Described circuits for triggering comprise a resistance 15 and an electric capacity 14, one end of described resistance 15 is connected with described polysilicon 10, one end of described electric capacity 14 also is connected with described polysilicon 10, the other end of described resistance 15 connects earth terminal 12, and the other end of described electric capacity 14 is connected to ESD electric charge injection end 13.
The equivalent electric circuit of semiconductor anti-static protection structure of the present invention as shown in Figure 5; include a PNP pipe and a NPN pipe; the emitter of described PNP pipe is received the base stage of this PNP pipe by a resistance; the collector electrode of described PNP pipe is connected to the base stage of described NPN pipe; the base stage of described PNP pipe is also connected to the collector electrode of described NPN pipe; the emitter of described NPN pipe is connected to the base stage of this NPN pipe by another resistance; the grounded emitter of described NPN pipe, the emitter of described PNP pipe is as ESD electric charge injection end.One end of electric capacity 14 is connected to ESD electric charge injection end, and the other end connects and is connected with an end of resistance 15, the other end ground connection of resistance 15, and the end that electric capacity 14 is connected with resistance 15 produces triggering signal, control NPN pipe.
Add polysilicon on this silicon controlled rectifier and trigger structure, when ESD takes place, having a positive voltage is added on the polysilicon 10, below polysilicon 10 and oxide layer isolated area 9, P type area between N type injection region 7 and N trap injection region, have the induction electron production, the ion that these inductions generate has been expanded the depletion layer area of N trap injection region 2, reduce distance with N type injection region 7, at this moment since the ESD accumulation in N trap injection region 2, improved the voltage of N trap injection region 2, punchthrough effect (punch through) has just taken place further to horizontal expansion in the depletion region that causes N trap injection region 2 when contacting with N type injection region 7, electric current sharply rises, cause parasitic NPN pipe and the conducting of PNP pipe to enter the electric current amplification region, bleed off the ESD electric charge.And under non-ESD generation state, polysilicon is by big resistance 15 ground connection, and N trap injection region 2 punchthrough effect can not take place with N type injection region 7.

Claims (3)

1. a semiconductor anti-static protection structure comprises P type substrate, includes N trap injection region and P trap injection region on described P type substrate; In described N trap injection region, include a P type injection region and a N type injection region, separated by an oxide layer isolated area between P type injection region in the described N trap injection region and the N type injection region; Also include a P type injection region and a N type injection region in described P trap injection region, separated by another oxide layer isolated area between the P type injection region of described P trap injection region and the N type injection region; The N type injection region of P type injection region in the described N trap injection region and described P trap injection region is separated by another oxide layer isolated area, it is characterized in that, be provided with a polysilicon above the oxide layer isolated area between the N type injection region of P type injection region in described N trap injection region and described P trap injection region.
2. semiconductor anti-static protection structure according to claim 1 is characterized in that, described polysilicon is connected with circuits for triggering.
3. semiconductor anti-static protection structure according to claim 2; it is characterized in that; described circuits for triggering comprise a resistance and an electric capacity; one end of described resistance is connected with described polysilicon; one end of described electric capacity also is connected with described polysilicon; the other end ground connection of described resistance, the other end of described electric capacity are connected to the electric charge injection end of static discharge.
CNB200610118439XA 2006-11-17 2006-11-17 Semiconductor anti-static protection structure Active CN100474589C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB200610118439XA CN100474589C (en) 2006-11-17 2006-11-17 Semiconductor anti-static protection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB200610118439XA CN100474589C (en) 2006-11-17 2006-11-17 Semiconductor anti-static protection structure

Publications (2)

Publication Number Publication Date
CN101188237A CN101188237A (en) 2008-05-28
CN100474589C true CN100474589C (en) 2009-04-01

Family

ID=39480526

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB200610118439XA Active CN100474589C (en) 2006-11-17 2006-11-17 Semiconductor anti-static protection structure

Country Status (1)

Country Link
CN (1) CN100474589C (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102315212B (en) * 2010-06-29 2015-10-21 上海华虹宏力半导体制造有限公司 Grid drive thyristor circuit and electrostatic discharge protective circuit
CN102148241B (en) * 2010-12-30 2012-10-24 浙江大学 Coupling-capacitor triggered silicon controlled device
CN108346652B (en) * 2017-01-22 2021-02-09 中芯国际集成电路制造(上海)有限公司 Electrostatic discharge protection device

Also Published As

Publication number Publication date
CN101188237A (en) 2008-05-28

Similar Documents

Publication Publication Date Title
US8455315B2 (en) Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch
CN101506974B (en) Latch-up free vertical TVS diode array structure using trench isolation
US8981426B2 (en) Electrostatic discharge protection device
US8044466B2 (en) ESD protection device in high voltage and manufacturing method for the same
CN102468299A (en) Area-efficient high voltage bipolar-based ESD protection targeting narrow design windows
CN102544115B (en) ESD (Electro-Static discharge) protection device with low trigger voltage and high balllast resistance for SCR (Silicon Controlled Rectifier)
US8703547B2 (en) Thyristor comprising a special doped region characterized by an LDD region and a halo implant
CN101283452A (en) Electrostatic Discharge Protection Devices
CN106229314A (en) Electrostatic discharge protector and manufacture method thereof
CN110649016A (en) Silicon controlled rectifier type ESD (electro-static discharge) protection structure without hysteresis effect and implementation method thereof
US8598625B2 (en) ESD protection device with tunable design windows
CN101202281A (en) SCR electrostatic protection device and method of manufacture
US8859361B1 (en) Symmetric blocking transient voltage suppressor (TVS) using bipolar NPN and PNP transistor base snatch
CN100524758C (en) SCR antistatic protection structure
KR20090098237A (en) Electrostatic Discharge Protection Device with Stacked Silicon Controlled Rectifier with High Holding Voltage
CN100474589C (en) Semiconductor anti-static protection structure
CN100525000C (en) Static discharge protection circuit and structure for part charging mode
JP2010050328A (en) Electrostatic protective element
CN109742070B (en) A FDSOI thyristor electrostatic protection device
US20120248574A1 (en) Semiconductor Structure and Manufacturing Method and Operating Method for the Same
US6690069B1 (en) Low voltage complement ESD protection structures
KR100750588B1 (en) Electrostatic Discharge Protection Circuit
CN101202280A (en) A kind of SCR electrostatic protection device and its manufacturing method
US11222886B2 (en) ESD protection device with low trigger voltage
CN111739887B (en) Electrostatic Protection Unit Based on Thyristor and Its Parallel Structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER NAME: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

CP03 Change of name, title or address

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Patentee before: Shanghai Huahong NEC Electronics Co., Ltd.