CN100472964C - Current steering switch circuit for high speed, high resolution digital-to-analog conversion - Google Patents
Current steering switch circuit for high speed, high resolution digital-to-analog conversion Download PDFInfo
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- CN100472964C CN100472964C CNB2005101189558A CN200510118955A CN100472964C CN 100472964 C CN100472964 C CN 100472964C CN B2005101189558 A CNB2005101189558 A CN B2005101189558A CN 200510118955 A CN200510118955 A CN 200510118955A CN 100472964 C CN100472964 C CN 100472964C
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Abstract
Provided are a method and system for reducing glitch in a switch circuit. A system includes a current-steering switch circuit including a main differential pair switch coupled to a first tail current having a first current value. Also included is an auxiliary differential pair switch connected to the main differential pair switch. The auxiliary differential pair switch is coupled to a second tail current and configured to substantially reduce a feed-through current associated with the main differential pair switch.
Description
Technical field
The present invention relates to D/A converting circuit, more particularly, relate to a kind of current steering switch circuit that is used for high speed, high-resolution digital-to-analogue conversion.
Background technology
Current steering switch circuit is widely used in high speed Nyquist (Nyquist) digital to analog converter (DAC).In the switch motion process in the switching circuit output noise and glitch can appear.The partly cause that noise and glitch occur is because will be by the parasitic capacitance between the input and output node when output is arrived in switch input signal feedthrough (feed-through).Another reason that noise and glitch occur is the current imbalance that is injected into differential output nodes from vibration (bouncing) the common emitter node of switch differential pair.
Industry is called I type switching noise with the former, and the latter is called II type switching noise.If DAC is full segmented, the DAC output noise that is caused by switch motion then is linear, the DAC output signal level is proportional in this case: its unidirectional tail current is switched to the total quantity of differential pair of the positive side of DAC difference output, deduct the quantity that switches to minus side.
Yet, for 10 or high-resolution more, adopt the DAC structure of segmented to reduce complexity usually, this segmented DAC structure comprises an exchange unidirectional current source array and an exchange bidirectional weighting current source array.Consequently, its tail current being switched to the DAC difference, to export the net quantity of the differential pair of positive side be not the linear function of signal level; Therefore switching noise produces nonlinearity erron at the output of DAC, even if for each switch motion, it equates on amplitude.
Along with the raising of switching rate, become the essential part of considering in each change-over period switching time, therefore switching noise becomes the nonlinear main cause of output, thereby has limited the switching rate of high-resolution DAC.
For example, in the front end applications of cable modem, wish to make one 12 (or more high-resolution) DAC arrays to operate on the sample rate of about 2.5GS/s, in each DAC, to send multi-channel signal.This change-over period is 400 psecs (ps), and in present bipolar complementary metal oxide semiconductor (BiCOMS) technology, and differential pair is approximately 40ps switching time.Like this, switching noise accounts for the DAC output waveform 1/10th more than.That is to say that switching noise has been limited in the Spurious-Free Dynamic Range (SFDR) of DAC output below the 60dB.
Therefore, need a kind ofly to be used for switch noise inhibiting and SFDR is brought up to technology more than the 60dB.
Summary of the invention
According to the description of the embodiment in principle of the present invention and the present specification, the present invention includes the current steering circuit that is used to make up high speed, high-resolution digital to analog converter.Described current steering circuit comprises the main differential pair switch that is connected to first tail current with first current value, also comprises the auxilliary differential pair switch that is cross connected on the described main differential pair switch.Described auxilliary differential pair switch is connected to second tail current, is used for fully reducing and the relevant feedthrough current of described main differential pair switch.
According to an aspect of the present invention, provide a kind of current steering switch circuit, comprising:
Main differential pair switch, described main differential pair switch comprises that the first transistor is right, described the first transistor is to having first and second Control Node, first and second output nodes and tail current node;
Auxilliary differential pair switch, described auxilliary differential pair switch comprises that transistor seconds is right, described transistor seconds is to having first and second Control Node, first and second output nodes and tail current node;
Wherein, first and second Control Node of described main differential pair switch are connected respectively to first and second Control Node of described auxilliary differential pair switch; First and second output nodes of described main differential pair switch are cross connected to first and second output nodes of described auxilliary differential pair switch respectively; Form first connected node by first output node of described main differential pair switch and second output node of described auxilliary differential pair switch; Form second connected node by second output node of described main differential pair switch and first output node of described auxilliary differential pair switch;
First tail current source, described first tail current source has first current value, is connected to the tail current node of described main differential pair switch;
Second tail current source, described second tail current source has second current value less than described first current value, is connected to the tail current node of described auxilliary differential pair switch;
First pair of serial transistor (cascode transistor) is connected respectively to described first and second connected nodes, and described first pair of serial transistor regulated the voltage at the described first and second connected node places respectively.
Preferably, in the current steering switch circuit of the present invention, also comprise second pair of serial transistor; In described second pair of serial transistor, a transistor is connected between described main differential pair switch tail current node and described first tail current source, and the another transistor is connected between described auxilliary differential pair switch tail current node and described second tail current source.
Preferably, in the current steering switch circuit of the present invention, also comprise:
Differential amplifier circuit, first and second Control Node with described main differential pair switch and described auxilliary differential pair switch are connected respectively, and described differential amplifier circuit comprises the input that is used to receive differential input signal;
Biasing circuit, described biasing circuit provides bias voltage for described main differential pair switch, auxilliary differential pair switch, first and second pairs of serial transistors.
Preferably, in the current steering switch circuit of the present invention, described biasing circuit comprises:
The first transistor is complementary with described first pair of serial transistor;
Transistor seconds links to each other with the first transistor of described biasing circuit, and is complementary with described main differential pair switch;
The 3rd transistor links to each other with the transistor seconds of described biasing circuit, and is complementary with described second pair of serial transistor.
Preferably, in the current steering switch circuit of the present invention, described biasing circuit also comprises:
First resistance, be connected between the first transistor and described supply voltage of described biasing circuit, and and the load resistance that is connected between described first pair of serial transistor and the described supply voltage is complementary, and wherein, described first resistance is controlled the voltage swing on the described load resistance;
Second resistance is connected between the 3rd transistor AND gate second source of described biasing circuit, and for described first and second tail current sources provide voltage headroom, the second resistance scalable of wherein said biasing circuit is to adapt to different current sources.
Preferably, in the current steering switch circuit of the present invention, described biasing circuit also comprises the 3rd resistance, is connected between the first transistor of first resistance of described biasing circuit and described biasing circuit, for described main differential pair switch provides the work tolerance limit.
Preferably, in the current steering switch circuit of the present invention, described differential amplifier circuit comprises the driving transistors differential pair, each driving transistors in the described driving transistors differential pair have respectively control end as input, by current source separately be connected to supply voltage second end, be connected to the 3rd end of the 3rd current source, second end of wherein said each driving transistors interconnects by the resistance of a string definition common-mode voltage node, and wherein said common-mode voltage node provides bias voltage by described biasing circuit.
Preferably, in the current steering switch circuit of the present invention, described main differential pair switch and described auxilliary differential pair switch constitute balance cock.
Preferably, in the current steering switch circuit of the present invention, described auxilliary differential pair switch is identical with described main differential pair switch.
Preferably, in the current steering switch circuit of the present invention, described transistor is realized by bipolar device.
Preferably, in the current steering switch circuit of the present invention, described transistor is made by the complementary metal oxide semiconductors (CMOS) material.
According to a further aspect in the invention, provide a kind of digital to analog converter, comprise
N type Z/kZ hierarchic structure (ladder);
P type Z/kZ hierarchic structure;
The differential switch array is connected between described n type Z/kZ hierarchic structure and the described p type Z/kZ hierarchic structure, and wherein at least one described differential switch comprises:
Main differential pair switch, described main differential pair switch comprises that the first transistor is right, described the first transistor is to having first and second Control Node, first and second output nodes and tail current node separately;
Auxilliary differential pair switch, described auxilliary differential pair switch comprises that transistor seconds is right, described transistor seconds is to having first and second Control Node, first and second output nodes and tail current node separately;
Wherein, first and second Control Node of described main differential pair switch are connected respectively to first and second Control Node of described auxilliary differential pair switch;
Wherein, first and second output nodes of described main differential pair switch are cross connected to first and second output nodes of described auxilliary differential pair switch respectively;
Form first connected node by first output node of described main differential pair switch and second output node of described auxilliary differential pair switch;
Form second connected node by second output node of described main differential pair switch and first output node of described auxilliary differential pair switch;
First tail current source, described first tail current source has first current value, is connected to the tail current node of described main differential pair switch;
Second tail current source, described second tail current source has second current value less than described first current value, is connected to the tail current node of described auxilliary differential pair switch;
The pair of series transistor is connected respectively to described first and second connected nodes, and described serial transistor is to regulating the voltage at described connected node place.
Preferably, in the digital to analog converter of the present invention, also comprise second pair of serial transistor; In described second pair of serial transistor, a transistor is connected between described main differential pair switch tail current node and described first tail current source, and the another transistor is connected between described auxilliary differential pair switch tail current node and described second tail current source.
Preferably, in the digital to analog converter of the present invention, also comprise:
Differential amplifier circuit is connected to the Control Node of described main differential pair switch and described auxilliary differential pair switch, and described differential amplifier circuit comprises the input that is used to receive differential input signal;
Biasing circuit, described biasing circuit are as supply voltage, for described main differential pair switch, auxilliary differential pair switch, first and second pairs of serial transistors provide bias voltage.
Preferably, in the digital to analog converter of the present invention, described biasing circuit comprises a string voltage divider that is connected between described supply voltage and the reference edge.
Preferably, in the digital to analog converter of the present invention, described differential amplifier circuit comprises the driving transistors differential pair, described driving transistors includes the control end as input respectively, each driving transistors includes second end that is connected to described supply voltage by current source separately, wherein said first end interconnects by the resistance of a string definition common-mode voltage node, each driving transistors includes the 3rd end that is connected to the 3rd current source, and wherein said common-mode voltage node provides bias voltage by described biasing circuit.
Preferably, in the digital to analog converter of the present invention, described main differential pair switch and described auxilliary differential pair switch constitute balance cock.
Preferably, in the digital to analog converter of the present invention, described auxilliary differential pair switch is identical with described main differential pair switch in fact.
Preferably, in the digital to analog converter of the present invention, described at least one differential switch is realized by bipolar device.
Preferably, in the digital to analog converter of the present invention, described at least one differential switch is made by the complementary metal oxide semiconductors (CMOS) material.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the schematic diagram of I type and II type switching noise electric current in the differential switch circuit;
Fig. 2 is the schematic diagram of the balance cock behind the elimination I type noise current;
Fig. 3 has cascode device with the schematic diagram of improvement to the balance cock of the elimination of I type noise;
Fig. 4 has the schematic diagram that the tail current serial transistor is used to suppress the balance cock of II type noise current;
Fig. 5 is the schematic diagram that is used for the differential amplifier circuit 500 of driven equilibrium switch input;
Fig. 6 is the schematic diagram that the bleeder circuit of bias voltage is provided for the balance cock circuit;
Fig. 7 is the schematic diagram that disposes the balance cock circuit of driving stage and biasing circuit;
Fig. 8 is the block diagram of the digital to analog converter (DAC) 800 that includes Z/2Z hierarchic structure;
Fig. 9 includes switch S
0To S
5The schematic diagram of DAC 900.
Embodiment
It below is the detailed description of also in conjunction with the accompanying drawings the present invention being carried out according to embodiments of the invention.In connotation of the present invention and scope, may also have other embodiment, and also can the embodiment in the present specification be made amendment.Therefore, the following description is not meaned limitation of the present invention.Or rather, scope of the present invention should be determined by claim of the present invention.
Shown in Figure 1 is the schematic diagram of a part 100 that includes the differential amplifier circuit of current steering switch 101.Switching circuit 101 comprises first and second bipolar transistors 102 and 104 differential pairs of forming (diffpair), and this first and second bipolar transistor 102 and 104 has difference negative output node (on) and difference positive output node (op) separately. Bipolar transistor 102 and 104 is connected with (parasitism) junction capacitor 106 and 108 respectively between its base stage and collector electrode.Junction capacitor 106 and the whole input-output Miller capacitances of 108 representatives.The parasitic capacitance that also comprises current source 110 in the main switch 101 and link with it (by capacitor 112 expressions). Difference transistor 102 and 104 and current source 110 constitute main switches 101.As example, establish the electric current that current source 110 produces 1.5I.
When difference input node dp and dn switched between constant high voltage and constant low-voltage, discharge and charging took place in junction capacitor 106 and 108.This change action produces I type switching noise, shows as feedthrough current 114 and 116 respectively.When the voltage of input node dp and dn switches when making the voltage fluctuation at cascode node ce place, can produce II type switching noise, pass capacitor 112, show as electric current 118.As mentioned above, I type and II type switching noise will make DAC output very significantly nonlinear characteristic occur.
For example, Fig. 9 includes switch S
0To S
5The schematic diagram of DAC 900.Switch S
0To S
5In one or more switches can adopt switch 101 (as shown in Figure 1) to realize.In the example of Fig. 9, switch S
0To S
3Carry out meticulous digital-to-analogue conversion.Switch S
4To S
5Carry out rough digital-to-analogue conversion.The operation principle of DAC 900 has been that March 16, application number in 2005 are 11/080 in the applying date, 808, the name U.S. Patent application that is called " the delay compensation Z/2Z hierarchic structure (Delay Equalized Z/2Z Ladder forDigital to Analog Conversion) that is used for digital-to-analogue conversion " is introduced, and the application is incorporated among the application with reference to its whole subject contents and with it.Switch S
0To S
5Needn't possess equal weight.Thereby, can make the nonlinearity of DAC output more serious from the I type of different switches and II type switching noise.
Fig. 2 is the exemplary plot of balance cock 200, and it has fully reduced I type and II type noise.
The spike tail current at the differential output nodes op of main switch 101 and on place (II type noise) is partial offset also.Because do not match between the parasitic capacitance that two cascode node ce and ce ' locate, this counteracting is not a fully differential.Because the tail current source unequal (1.5I for example shown in Figure 2 and 0.5I) in the main and auxiliary switch has caused parasitic capacitance not match.
Tail current in auxiliary switch 201 has the less biasing, and main switch 101 is actually identical with auxiliary switch 201.That is to say that because auxiliary switch 201 and main switch 101 interconnections, the noise of auxiliary switch 201 is just in time opposite to its effect with main switch 101 to the effect of difference output.Because bias current is little to input-output effect of parasitic capacitance, especially when differential pair is metal oxide semiconductor field-effect device (MOSFET), the degree of I type feedthrough noise cancellation is bigger than signal cancellation degree, thereby has improved signal to noise ratio (snr) and Spurious-Free Dynamic Range (SFDR).
With regard to balance cock 200, device occupies main power consumption and area when input data serializer in the high-speed DAC before the current steering switch array and restatement.Though balance cock is approximately Duoed one times (1.5I+0.5I=2I, that traditional is 1I) than the conventional switch consumed current, with respect to total power consumption, this a little power consumption that balance cock increases is inappreciable.In fact, this technology of analogue test proof balance cock can be exported SFDR with DAC and improve 10dB, and has only increased by about 10% total power consumption.
Fig. 3 is the schematic diagram that comprises a pair of 302 output serial transistors 304 and 306 balance cock 300, and this serial transistor is connected with balance cock 200 shown in Figure 2 302.In Fig. 3, output serial transistor 304 and 306 is by the output node op of adjustment switch 200 and the voltage on the on, reduced Miller effect (promptly, because the anti-phase interior output of input signal changes, thereby effectively increased the input to output capacitance of seeing from input), and further reduce unbalanced feedthrough.
To be applied to by the constant voltage that external power source produces on the short circuit base terminal bco of serial transistor 304 and 306.In this way, serial transistor 304 and 306 can be used as shielding device to reduce the output voltage swing of balance cock 206, is reduced to less voltage swing 308 from the relatively large amplitude of oscillation 204 (as shown in Figure 2).As a result, during switch motion, the variation of the parasitic junction capacitance between the input and output node is less.Like this, because feedthrough noise current I
Bcp, I
Bcn, I '
BcpAnd I '
BcnAmplitude close, thereby can realize improvement to the neutralization effect between these electric currents.As a result, analogue test proves: compare with independent use output cascode device or balance cock 200, the serial transistor shown in Figure 3 and the combination of balance cock make SFDR improve 20dB.
Fig. 4 is the schematic diagram of balance cock 400, and it comprises balance cock 300 and serial transistor 402 and 404, is used to suppress II type noise.In this circuit layout, serial transistor 402 and 404 is arranged near near the differential pair in the balance cock 200 separately, the relatively large parasitic capacitance 410 and 412 of coming self noise cascode node ce and ce ' in order to shielding.Because noise node ce is relative now littler with 408 with the parasitic capacitance 406 that ce ' locates, thereby II type peak current significantly reduces.
Fig. 5 is the circuit diagram of an embodiment of differential amplifier circuit 500, and the input difference of switching circuit that is used for driving Fig. 2 to 4 is right.Among Fig. 5, the common mode of driving amplifier output 502 is connected to reference voltage Vcm, and to improve power supply attenuation rate (PSRR), wherein voltage Vcm is an AC reference voltage over the ground.Amplifier circuit 500 comprises first and second current sources 504 and 506, first and second transistors 508 and 510, first and second resistance 514 and the 516 and the 3rd current source 512.
Fig. 6 is the schematic diagram that is connected to the biasing circuit 600 of balance cock 400.For for simplicity, in example shown in Figure 6, only show the part of balance cock 400.As shown in Figure 6, serial transistor 304,306 and switch input difference provide biasing to 102,104 by voltage divider.Described voltage divider comprises 602,604,606 and three resistance 666,614,622 of three diode-connected transistors that are connected between power Vcc and the ground.The reference voltage that is produced by voltage divider cushions from the noise switch by the RC circuit filtering and by emitter follower (transistor 624 and 626).
In voltage divider, be connected resistance 616 on the Vcc and aspect voltage drop, be complementary with load resistance 618 and 610 that switch 400 drives.Resistance 616 is adjustable resistances, is used to regulate output voltage swing.
The first transistor 602 is connected between Vcc and the ground, is complementary with switch output serial transistor 304 and 306.Transistor seconds 604 is complementary to 102 and 104 with the input difference transistor.The 3rd transistor 606 is complementary with tail current serial transistor 402.The resistance 622 of ground connection is identical on type with resistance 616, and the tail current source 110 and 202 that its voltage is reduced in the balance cock provides voltage headroom.Resistance 622 is adjustable resistances, is used to adapt to different current source 110 and 202.Because the coupling between reference voltage generator and the biased witch, follow the tracks of mutually the working point, thereby this circuit can be tolerated bigger variation on technology, supply voltage and the temperature.
In Fig. 6, a less relatively resistance 614 can be inserted voltage dividers, so that provide some voltage headroom (be Vcb〉0) to 102 and 104 for input difference.Because the peak value enough and to spare of DAC output voltage swing and tail current source is depended in the pressure drop of resistance 616 and resistance 622 respectively, thereby the resistance value ratio of these two resistance can carry out programming Control according to output voltage swing and/or required current source peak value enough and to spare.
Each feature described herein can be implemented separately and/or implement with various compound modes each other.Such as but not limited to, Figure 7 shows that the schematic diagram of the balance cock 700 that comprises characteristics combination described herein.Certainly, the invention is not restricted to example shown in Figure 7.In example shown in Figure 7, balance cock 700 comprises balance cock 400 (as shown in Figure 4), differential amplifier circuit 500 (as shown in Figure 5) and switching circuit biasing circuit 600 (as shown in Figure 6).In one embodiment, transistor Q1, Q2, Q1 ' and Q2 ' are measure-alike in fact, and Q3 and Q4 are measure-alike, and Q5 and Q6 are measure-alike.
Balance cock disclosed herein can be realized in the stepped network of DAC R/2R, the stepped network of Z/2Z and/or the stepped network of Z/kZ, the content of this respect has been 11/080 at application number, open in 808 the U.S. Patent application file, in above discussion with reference to and combine this application.Such as but not limited to, Fig. 8 is the block diagram that comprises the DAC800 of P type hierarchic structure 802 and N type hierarchic structure 804.Under the control of respective differences divided data control line 812 and 814, differential switch 806 is connected with 810 node 808 separately with current source (not shown among Fig. 8).Differential switch 806 realizes by mode as herein described.
More than invention has been described by means of functional module, these functional modules have embodied the performance of correlation between specific function and the function.For ease of describing, the boundary of these functional modules has been done autocratic definition herein.As long as correlation can suitably realize between wherein specific function and the function, also can make other boundary definition.
The front has disclosed the general characteristic of invention fully to the description of the embodiment of the invention, other people are by the knowledge (comprising with reference to quoting this paper content) of application this area, under the situation that does not break away from total design of the present invention, need not more experiments, just can make amendment to these specific embodiments at an easy rate and/or make it be suitable for different application.Therefore, according to the instruction that this paper introduces content, can determine that this adaptive change is to be equal to mutually with the scope of embodiment disclosed herein with revising.Should be appreciated that word used herein or term, its objective is in order clearly to describe the present invention, rather than limit, thereby those skilled in the art in conjunction with those of ordinary skill in the art's knowledge, can carry out note according to the instruction of this paper to word in the specification or term.
It is that October 29, application number in 2004 are 60/622 that the application requires the applying date, 936, name is called the priority of the U.S. Provisional Patent Application of " method and system that is used for the glitch-free difference current guiding switching circuit of high speed, high-resolution digital-to-analogue conversion ", and the application is incorporated among the application with reference to its full content and with it.
Claims (9)
1, a kind of current steering switch circuit is characterized in that, comprising:
Main differential pair switch, described main differential pair switch comprises that the first transistor is right, described the first transistor is to having first and second Control Node, first and second output nodes and tail current node;
Auxilliary differential pair switch, described auxilliary differential pair switch comprises that transistor seconds is right, described transistor seconds is to having first and second Control Node, first and second output nodes and tail current node;
Wherein, first and second Control Node of described main differential pair switch are connected respectively to first and second Control Node of described auxilliary differential pair switch; First and second output nodes of described main differential pair switch are cross connected to first and second output nodes of described auxilliary differential pair switch respectively; Form first connected node by first output node of described main differential pair switch and second output node of described auxilliary differential pair switch;
Form second connected node by second output node of described main differential pair switch and first output node of described auxilliary differential pair switch;
First tail current source, described first tail current source has first current value, is connected to the tail current node of described main differential pair switch;
Second tail current source, described second tail current source has second current value less than described first current value, is connected to the tail current node of described auxilliary differential pair switch;
First pair of serial transistor is connected respectively to described first and second connected nodes, and described first pair of serial transistor regulated the voltage at the described first and second connected node places respectively.
2, current steering switch circuit according to claim 1 is characterized in that, also comprises second pair of serial transistor; In described second pair of serial transistor, a transistor is connected between described main differential pair switch tail current node and described first tail current source, and the another transistor is connected between described auxilliary differential pair switch tail current node and described second tail current source.
3, current steering switch circuit according to claim 2 is characterized in that, also comprises:
Differential amplifier circuit, first and second Control Node with described main differential pair switch and described auxilliary differential pair switch are connected respectively, and described differential amplifier circuit comprises the input that is used to receive differential input signal;
Biasing circuit, described biasing circuit provides bias voltage for described main differential pair switch, auxilliary differential pair switch, first and second pairs of serial transistors.
4, current steering switch circuit according to claim 3 is characterized in that, described biasing circuit comprises:
The first transistor is complementary with described first pair of serial transistor;
Transistor seconds links to each other with the first transistor of described biasing circuit, and is complementary with described main differential pair switch;
The 3rd transistor links to each other with the transistor seconds of described biasing circuit, and is complementary with described second pair of serial transistor.
5, current steering switch circuit according to claim 4 is characterized in that, described biasing circuit also comprises:
First resistance, be connected between the first transistor and supply voltage of described biasing circuit, and and the load resistance that is connected between described first pair of serial transistor and the described supply voltage is complementary, and wherein, described first resistance is controlled the voltage swing on the described load resistance;
Second resistance is connected between the 3rd transistor AND gate second source of described biasing circuit, and for described first and second tail current sources provide voltage headroom, the second resistance scalable of wherein said biasing circuit is to adapt to different current sources.
6, current steering switch circuit according to claim 5, it is characterized in that, described biasing circuit also comprises the 3rd resistance, is connected between the first transistor of first resistance of described biasing circuit and described biasing circuit, for described main differential pair switch provides the work tolerance limit.
7, current steering switch circuit according to claim 3, it is characterized in that, described differential amplifier circuit comprises the driving transistors differential pair, each driving transistors in the described driving transistors differential pair have respectively control end as input, by current source separately be connected to supply voltage second end, be connected to the 3rd end of the 3rd current source, second end of wherein said each driving transistors interconnects by the resistance of a string definition common-mode voltage node, and wherein said common-mode voltage node provides bias voltage by described biasing circuit.
8, current steering switch circuit according to claim 1 is characterized in that, described main differential pair switch and described auxilliary differential pair switch constitute balance cock.
9, current steering switch circuit according to claim 1 is characterized in that, described auxilliary differential pair switch is identical with described main differential pair switch.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US62293604P | 2004-10-29 | 2004-10-29 | |
| US60/622,936 | 2004-10-29 | ||
| US11/169,665 | 2005-06-30 |
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| Publication Number | Publication Date |
|---|---|
| CN1767387A CN1767387A (en) | 2006-05-03 |
| CN100472964C true CN100472964C (en) | 2009-03-25 |
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| CNB2005101189558A Expired - Fee Related CN100472964C (en) | 2004-10-29 | 2005-10-27 | Current steering switch circuit for high speed, high resolution digital-to-analog conversion |
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