CN100466479C - Block interleaving for turbo coding. - Google Patents
Block interleaving for turbo coding. Download PDFInfo
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- CN100466479C CN100466479C CNB200610055037XA CN200610055037A CN100466479C CN 100466479 C CN100466479 C CN 100466479C CN B200610055037X A CNB200610055037X A CN B200610055037XA CN 200610055037 A CN200610055037 A CN 200610055037A CN 100466479 C CN100466479 C CN 100466479C
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Abstract
An interleaver receives incoming data frames of size N. The interleaver indexes the elements of the frame with an N1 x N2 index array. The interleaver then effectively rearranges (permutes) the data by permuting the rows of the index array. The interleaver employs the equation I(j,k) = I(j,( alpha jk + beta j)modP) to permute the columns (indexed by k) of each row (indexed by j.) P is at least equal to N2, beta j is a constant which may be different for each row, and each alpha j is a relative prime number relative to P. After permuting, the interleaver outputs the data in a different order than received (e.g., receives sequentially row by row, outputs sequentially each column by column).
Description
The application be the applicant on January 11st, 2000 submit to, application number for " 00804027.3 ", denomination of invention divides an application for the application for a patent for invention of " block interleaving that is used for turbo coding ".
Technical field
The present invention relates generally to communication system, be specifically related to carry out code modulated interleaver.
Background technology
Have been found that coding techniques (being called coded modulation) to communication channel can improve the bit error rate such as electronic communication systems such as modulator-demodulator, wireless communication systems.Turbine (Turbo) coded modulation proved a kind of to additive white Gaussian (AWGN) or decline be feature the practicality of " makeing mistakes at random " channel, the modulator approach high efficiently with channel efficiency.For example, can in code division multiple access (CDMA) environment, find these channels of makeing mistakes at random.The ability of CDMA environment depends on working signal/noise ratio, thereby improves performance and just improve ability.
An aspect of engine encoder (Turbo coder) is a kind of interleaver so efficiently, it to primary reception to or the Frame that sends before entering into the 2nd encoder, replace.According to one or more randomized algorithms by displacement is finished in incomplete randomization.With Frame after the displacement and initial data frame combination, show the low BERs that can obtain in AWGN and the fading channel.Interleaving treatment has increased the diversity in the data, thereby during distortion, can use error correction algorithm to recover in decoder in transmission when modulated symbol.
Frame is gathered and compiled to traditional interleaver to the signaling point that will send in the array, in fact array delegation connect delegation ground and filled.After the signaling point of scheduled volume is compiled frame, send by the row of reading this array in fact and make interleaver be dummy status.As a result, the signaling point that is close to mutually in original signal point stream in the same delegation of array is separated by the signaling point that quantity equals line number amount in the array.Ideally, choosing of the quantity of row and row should make complementary signaling point separate longlyer than the channel pulse train of makeing mistakes of expectation after transmission.
Non-homogeneous " extreme spread " and " maximum unordered " of output sequence that interweaves and to obtain data.Therefore, the redundancy of two convolution coder introducings is scattered more impartial in the output sequence of Turbo encoder.Minimum range is increased to than the bigger value that evenly interweaves.The non-homogeneous intrinsic problem that interweaves be how actual implement to interweave obtain enough " heterogeneity " simultaneously and minimum latency compensates, this delay compensation has limited the application of real-time requirement.
Seeking effective interleaver is popular theme in the 3rd generation CDMA standard actions.Determined and be generally acknowledged, when the frame scale when infinite, the most effective interleaver is a random interleaver.Yet for limited frame scale, the most effective interleaver determines still under discussion.
Therefore, need a kind of system and method that improves heteropical interlaced code of limited frame scale.
The system and method that also needs a kind of quite simple interlaced code of implementing.
So, the object of the present invention is to provide the system and method for the heteropical interlaced code that improves limited frame scale.
Another object of the present invention is to provide the system and method for the quite simple interlaced code of implementing.
Those of skill in the art will be appreciated that above-mentioned and other purpose from the following description.
Summary of the invention
The present invention can finish above-mentioned and other purpose, wherein, Frame is interweaved, and Frame is formed by pre-determined size and by several portions.One embodiment of the invention comprise store frames of data and utilize N
1* N
2Index array I is the method for this Frame indexation, wherein, and N
1And N
2The long-pending N that equals at least.Element in the index array shows positions of elements in the Frame.The Frame element can any traditional approach be stored and be need not to be organized into array.This method further comprise according to I (j, k)=I (j, (α
jK+ β
j) modP) the index array is replaced, wherein, I is the index array, as mentioned above, j and k are respectively the indexes of row and column in the index array, the constant group that α and β select according to current line, and P and each α
jIt is relative prime number.Frame is replaced after the index array I indexation by displacement effectively.
An embodiment more of the present invention comprises interleaver, and this interleaver comprises store frames of data and storage N
1* N
2The storage device that index array I uses, wherein, N
1And N
2The long-pending N that equals at least.Element in the index array shows positions of elements in the Frame.The Frame element can any traditional approach be stored and be need not to be organized into array.This interleaver further comprise according to I (j, k)=I (j, (o
jK+ β
j) modP) to the device that the index array is replaced, wherein, I is the index array, as mentioned above, j and k are respectively the indexes of row and column in the index array, the constant group that α and β select according to current line, and P and each α
jIt is relative prime number.Frame is replaced after the index array I indexation by displacement effectively.
The further embodiment of the present invention provides a kind of interleaver of interleaving data frame element, and this interleaver comprises: storage comprises the input store as the Frame of a plurality of elements of array D, and this array D has as 0,1 ... N
1-1 N
1OK; With as 0,1 ... N
2-1 N
2Row, wherein, N
1And N
2It is positive integer greater than 1; Be coupled with described input store and array D be replaced as array D according to equation
1Processor D
1(j, k)=D (j, (α
jK+ β
j) modP), wherein, j is by array D and D
1The index of row; K is by array D and D
1The index of row; α
jAnd β
jBe to be the predetermined integer of each row j; P equals N at least
2Integer; With each α
jBe to be coupled and to be configured to store described replacement array D with respect to the relative prime number of P with described processor
1Working storage.
The further again embodiment of the present invention provides the interleaver of element in a kind of interleaving data frame, and described interleaver comprises: the memory of storage index array I, and this array I has as 0,1 ... N
1-1 N
1OK; With as 0,1 ... N
2-1 N
2Row, wherein, N
1And N
2It is each unit that is stored in a plurality of memory cell greater than the Frame element that 1 positive integer and described memory also are used for receiving; Be coupled the processor of value that is used for showing the respective memory unit of frame element with described memory in the sequential positions storage that array I meets delegation with delegation; Also the I array is replaced as I with described processor according to following equation
1Array: I (j, k)=I (j, (α
jK+ β
j) modP) wherein, j is by array I and I
1The index of row; K is by array I and I
1The index of row; α
jAnd β
jIt is the predetermined integer of each row j; P equals N at least
2Integer; With each α
jBe relative prime number with respect to P, thus, according to array I
1The Frame of indexation can be replaced effectively.
Below in conjunction with some embodiment of diagram and actual description the present invention.Obviously, those of skill in the art are not breaking away from spirit of the present invention or the claim scope can be done various modifications, increases and delete.
Description of drawings
By below in conjunction with accompanying drawing to the detailed description that embodiment did, can be expressly understood the present invention, wherein:
Fig. 1 illustrates the key diagram of traditional Turbo encoder;
Fig. 2 illustrates the block diagram of interleaver shown in Fig. 1;
Fig. 3 illustrates the array that comprises Frame and to the displacement of this array;
Fig. 4 illustrates the Frame that is stored in the continuous memory cell;
Fig. 5 illustrates with the index array of the indexation of Frame shown in Fig. 4 with to the displacement of index array.
Embodiment
Fig. 1 illustrates traditional Turbo encoder.As shown in the figure, traditional Turbo encoder comprises two encoders 20 and an interleaver 100.Interleaver 100 of the present invention receives the Frame of introducing 110, and the scale of this frame 110 (size) is N, and wherein, N is the some parts that bit number, byte number or other frame can be separated into, and they are called the frame element.Interleaver 100 with N frame element be divided into as the row data set.Interleaver is rearranged data in each group with pseudo-random fashion then.Interleaver 100 can adopt distinct methods to rearrange not on the same group data set.Yet the technical staff in this field will be appreciated that one or more methods can be reused for one or more data sets and do not depart from the scope of the present invention.After the data, interleaver is to be different from the order dateout of reception in each group of displacement.
Interleaver 100 can be at N
1* N
2Store frames of data in the array of scale makes N
1* N
2=N.Example shown in Figure 3 shows to have 3 row (N
1=3) 6 row (N
2=6) array 350 is used for storing the Frame 110 with 18 elements, and these 18 element representations are that frame element 00 (FE00) is to FE17 (N=18).Though this is a preferred approach, array also can be designed to N
1* N
2Be the part of N, make one or more littler arrays, and the result of each less array is made up in the back according to work of the present invention.
According to the displacement of the present invention to array 350, in the array 350 each the row j carry out respectively, according to equation replace each the row in row k.
D(j，k)＝D(j，(α
jk+β
j)modP)
Wherein:
J and k are respectively the indexes of row and column in the array 350;
P is more than or equal to N
2Number;
α
jWith P is relative prime number (1 or both may be non-prime numbers, but their common divisor has only 1);
β
jBe constant, with 1 value and each line correlation.
In case the data of all row are replaced, new array is read with regard to row with connecing row.Equally, in case row is replaced, just can before dateout, replace data by column split.Under the situation that both are replaced at row and column, row, column or both can replace according to the present invention.For example, also can come row in the transposition array with the bit of binary representation row index j by transposition.(for example, in 4 row arrays, the 2nd and the 3rd is about to carry out transposition according to this scheme.) also can replace row or column according to different method of replacing, but be not both.Those of skill in the art know, system can be rearranged to row and connect a column storage, respectively organize data and delegation by column permutation and meet delegation and read the result, and these do not depart from the scope of the present invention.
These deinterleaving methods are based upon on the number theory basis, and available software and/or hardware are implemented (that is, the integrated circuit of application-specific (ASIC), programmable logic array (PLA), or any other suitable logical device).And, single pseudo-random sequence generator (that is, m-sequence, M-sequence, Gold sequence, Kasami sequence ... etc.) can be used as interleaver.
In example shown in Figure 3, the choosing value of P is 6, and the α value is 5 to all 3 provisional capitals, and the β value is respectively 1,2 and 3 to 3 row.(these only are for example.Select other number can obtain different displacement results.) value of α (5), respectively be with respect to the as above relative prime number of the P (6) of regulation.
Equation with the value computational rules of stipulating is replaced as array D with row 0 among the array D350
1The process of row 0 is as follows in 360:
D
1(0，0)＝D(0，(5*0+1)mod6)＝D(0，(1)mod6)＝D(0，1)＝FE01
D
1(0，1)＝D(0，(5*1+1)mod6)＝D(0，(6)mod6)＝D(0，0)＝FE00
D
1(0，2)＝D(0，(5*2+1)mod6)＝D(0，(11)mod6)＝D(0，5)＝FE05
D
1(0，3)＝D(0，(5*3+1)mod6)＝D(0，(16)mod6)＝D(0，4)＝FE
D
1(0，4)＝D(0，(5*4+1)mod6)＝D(0，(21)mod6)＝D(0，3)＝FE03
D
1(0，5)＝D(0，(5*5+1)mod6)＝D(0，(26)mod6)＝D(0，2)＝FE02
So row 0 becomes: FE01 FE00 FE05 FE04 FE03 FE02
For row 1, equation becomes:
D
1(1，0)＝D(1，(5*0+2)mod6)＝D(1，(2)mod6)＝D(1，2)＝FE08
D
1(1，1)＝D(1，(5*1+2)mod6)＝D(1，(7)mod6)＝D(1，1)＝FE07
D
1(1，2)＝D(1，(5*2+2)mod6)＝D(1，(12)mod6)＝D(1，0)＝FE06
D
1(1，3)＝D(1，(5*3+2)mod6)＝D(1，(17)mod6)＝D(1，5)＝FE11
D
1(1，4)＝D(1，(5*4+2)mod6)＝D(1，(22)mod6)＝D(1，4)＝FE10
D
1(1，5)＝D(1，(5*5+2)mod6)＝D(1，(27)mod6)＝D(0，3)＝FE09
So row 1 becomes: FE08 FE06 FE11 FE10 FE09
For row 2, equation becomes:
D
1(2，0)＝D(2，(5*0+3)mod6)＝D(2，(3)mod6)＝D(2，3)＝FE15
D
1(2，1)＝D(2，(5*1+3)mod6)＝D(2，(8)mod6)＝D(2，2)＝FE14
D
1(2，2)＝D(2，(5*2+3)mod6)＝D(2，(13)mod6)＝D(2，1)＝FE13
D
1(2，3)＝D(2，(5*3+3)mod6)＝D(2，(18)mod6)＝D(2，0)＝FE12
D
1(2，4)＝D(2，(5*4+3)mod6)＝D(2，(23)mod6)＝D(2，5)＝FE17
D
1(2，5)＝D(2，(5*5+3)mod6)＝D(2，(28)mod6)＝D(0，4)＝FE16
So row 2 becomes: FE15 FE14 FE13 FE12 FE17 FE16
And the Frame after the displacement is included in array D shown in Figure 3
1360.One row connect a row output array will be according to following order output frame element:
1，8，15，0，7，14，5，6，13，4，11，12，3，10，17，2，9，16。
Change in the enforcement of the present invention one, Frame 110 is not according to array or matrix but be stored in the continuous memory cell, and store an index array that separates and be used for element indexization Frame, according to equation of the present invention the index array is replaced, by output data frame after the index array indexation after the displacement.
The block diagram of Fig. 4 explanation 32 elements of storage (thereby have side-play amount 0 to 31 from initial memory cell) on length.Frame 110 is taken as 22 length of elements thereby containing element FE00 to FE21 in this example, occupy offset storage unit 00 to 21 in frame 400.Offset storage unit 22 to 31 comprises unknown content in the frame 400.The frame length of 22 elements is an example, also can select other length.The storage frame element is an example in continuous memory cell, also can adopt discontinuous memory cell.
The index array I550 that memory block 400 indexation are used in Fig. 5 explanation.Each forms 4 row (N with 8 row
1=4, N
2=8, N=N
1* N
2=32).Then as shown in Figure 5, original contents is inserted array I550.This initialization meets delegation according to delegation and reads in the identical effect of Frame 110 generations.
The index array is replaced according to following equation:
I
1(j，k)＝I(j，(α
jk+β
j)modP)
Wherein, α=1,3,5,7
β＝0，0，0，0
P＝8
These numbers are examples, also can select other number, as long as satisfy regulation: P equals N at least
2And each value of α is the relative prime number with respect to selected P value.
For example, if equation is applied to the row of row 2, then produce:
I
1(2，0)＝I(2，(5*0)mod8)＝I(2，(0)mod8)＝I(2，0)＝16
I
1(2，1)＝I(2，(5*1)mod8)＝I(2，(5)mod8)＝I(2，5)＝21
I
1(2，2)＝I(2，(5*2)mod8)＝I(2，(10)mod8)＝I(2，2)＝18
I
1(2，3)＝I(2，(5*3)mod8)＝I(2，(15)mod8)＝I(2，7)＝23
I
1(2，4)＝I(2，(5*4)mod8)＝I(2，(20)mod8)＝I(2，4)＝20
I
1(2，5)＝I(2，(5*5)mod8)＝I(2，(25)mod8)＝I(2，1)＝17
I
1(2，6)＝I(2，(5*6)mod8)＝I(2，(30)mod8)＝I(2，6)＝22
I
1(2，7)＝I(2，(5*7)mod8)＝I(2，(35)mod8)＝I(2，3)＝19
Equation is applied to row 0,1 and 3 equally, produces the index array I after the displacement shown in Figure 5
1560.
0，8，16，24，1，11，21，31，2，14，18，30，3，9，23，29，4，12，20，28，5，15，17，27，6，10，22，26，7，13，19，25。
But this example supposition frame length is offset storage unit 22-31 in 22 element frames 400, is not the Frame part.Therefore, when output data frame, it is retracted or wipes out length 22; That is, ignore greater than 21 offset storage unit.So Frame surface element order output down:
0，8，16，1，11，21，2，14，18，3，9，4，12，20，5，15，17，6，10，7，13，19。
One aspect of the present invention, for example, by with the bit inversion of binary representation row index j and before output the row to array carry out transposition.
Available some different modes are implemented interleaver 100 of the present invention.Fig. 2 illustrates one embodiment of the invention, and wherein, interleaver 100 comprises the input store 300 of reception and store frames of data 110.This memory 300 can comprise shift register, RAM etc.Interleaver 100 also can comprise working storage 310, and memory 310 also can comprise RAM, shift register etc.Interleaver comprise processor 320 (as, microprocessor, ASIC etc.), be configured to according to above-mentioned equation handle in real time I (j, k) or visit comprise I (J, K) result's the table that pre-deposits wherein.Those of skill in the art it will be appreciated that memory 300 and 310 can be a memory same or that separate.
For determine in real time I (j, k), the 1st row and will be in the displacement index array corresponding to the bytes store of displacement index in working storage.Replace next line and storage then, or the like, replaced and stored up to all row.This line replacement can order or parallel carrying out.
No matter be in real time or table look-up and determine I after the displacement (j, k), data can be stored in the workpiece memory by some different modes.Can by with displacement back index array (that is, with permutation function with input store indexation) in I (j, k) identical order is selected data and can be stored with storing them into working storage in proper order with memory cell from input store.Also can be by being stored in input store (promptly with them, FIF0) order in is selected byte and they is directly stored in the working storage by displacement back I (j, k) store in (that is, with permutation function with working storage indexation) definite memory cell.In case finish above-mentioned storage, just can connect a row ground from the working storage sense data according to one row of the index array after the displacement.As mentioned above, data based row rather than the row deposit working storage in after, data can be carried out another and be taken turns displacement, to obtain different results.
If system is enough fast, then can saves a memory, and can in real time or table look-up to deposit it in working storage when receiving data element with the displacement order that afterwards the index array is corresponding.
The interleaver that is disclosed can with existing Turbo code structure compatible.These interleavers present superior performance and do not increase the complexity of system.
In addition, those skilled in the art can see that deinterleaver can be used to the frame after interweaving is decoded.The structure that is used to separate the deinterleaver of Turbo code belongs to prior art.Here no longer discuss equally.But the deinterleaver of corresponding embodiment can constitute with the sequence after the above-mentioned displacement.
Though the foregoing description be a kind of in cdma system appreciable Turbo encoder, those of skill in the art should see that enforcement of the present invention is not limited to this, all can implement for the interleaving and de-interleaving of any kind in any communication system.
Therefore, the present invention can realize above-mentioned purpose effectively, comprises according to the apparent variation of doing of top description.In fact, the invention provides the apparatus and method that the improved finite length sign indicating number that interweaves makes the complexity minimum of enforcement simultaneously.
Should see, can do various variations to said structure with to the order of work of front, but not depart from the scope of the present invention.Therefore, describe above and accompanying drawing shown in all situations that comprises all be illustrative and do not limit.
Should see that also following claims are used for containing the present invention general and all specific features and whole statements that the scope of the invention is done described herein, we can say all as language expression to fall into wherein.
Claims (8)
1. the method for element in the interleaved signal data communication channel frame is characterized in that, comprises the following step:
Storage comprises the signal data frame as a plurality of elements of array D, and this array D has
Be designated as 0,1 ... N
1-1 N
1OK; With
Be designated as 0,1 ... N
2-1 N
2Row,
Wherein, N
1And N
2It is positive integer greater than 1; With
According to equation array D is replaced as array D
1
D
1(j，k)＝D(j，(α
jk+β
j)modP)
Wherein, j is array D and D
1Row number;
K is array D and D
1Row number;
α
jAnd β
jBe to be the predetermined integer of each row j;
P is more than or equal to N
2Integer; With
Each α
jBe the relative prime number with respect to P, wherein prime number is represented one group of number that does not have other common divisor except 1 relatively.
2. the method for claim 1 is characterized in that, wherein, the described element of array D is stored according to first order, and array D
1Described element export according to second order.
3. method as claimed in claim 2 is characterized in that, wherein, the element delegation of array D connects delegation's storage, and array D
1Element one row connect a row output.
4. the method for claim 1 further comprises output array D
1Step, wherein, N
1And N
2Long-pending greater than number of elements in the frame, frame is truncated to the number of element in the frame between period of output.
5. the interleaver of element in the interleaving data frame is characterized in that, comprises:
Storage comprises the storage device as the Frame of a plurality of elements of array D, and this array D has
Be designated as 0,1 ... N
1-1 N
1OK; With
Be designated as 0,1 ... N
2-1 N
2Row,
Wherein, N
1And N
2It is positive integer greater than 1; With
According to equation array D is replaced as array D
1Displacement apparatus
D
1(j，k)＝D(j，(α
jk+β
j)modP)
Wherein, j is array D and D
1Row number;
K is array D and D
1Row number;
α
jAnd β
jBe to be the predetermined integer of each row j;
P is more than or equal to N
2Integer; With
Each α
jBe the relative prime number with respect to P, wherein prime number is represented one group of number that does not have other common divisor except 1 relatively.
6. interleaver as claimed in claim 5 is characterized in that, also comprises according to the device of the described element of the first order storage array D with according to the second order output array D
1The device of described element.
7. interleaver as claimed in claim 6 is characterized in that, wherein, the device delegation of the described element of described storage array D meets delegation and stores, described output array D
1Device one row of element connect row and export.
8. interleaver as claimed in claim 5 is characterized in that, further comprises the described array D of output
1With work as N
1And N
2Long-pending greater than in the frame during number of elements with described array D
1Be truncated to number of elements destination device in the frame.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11539499P | 1999-01-11 | 1999-01-11 | |
| US60/115,394 | 1999-01-11 | ||
| US09/263,431 | 1999-03-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB008040273A Division CN1252936C (en) | 1999-01-11 | 2000-01-11 | Block interleaving for turbo coding |
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|---|---|
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| CN100466479C true CN100466479C (en) | 2009-03-04 |
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ID=37195635
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|---|---|---|---|---|
| US4394642A (en) * | 1981-09-21 | 1983-07-19 | Sperry Corporation | Apparatus for interleaving and de-interleaving data |
| CN1147883A (en) * | 1995-02-01 | 1997-04-16 | 菲利浦电子有限公司 | Method of error protected transmission, method of error protected reception of data and transmission system for transmission of data |
| US5742612A (en) * | 1993-06-02 | 1998-04-21 | Alcatel Radiotelephone | Method and device for interleaving a sequence of data elements |
-
2000
- 2000-01-11 CN CNB200610055037XA patent/CN100466479C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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