CN100461148C - Data chain connecting layer of chip group and method used in processing pack - Google Patents
Data chain connecting layer of chip group and method used in processing pack Download PDFInfo
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- CN100461148C CN100461148C CNB2007101437010A CN200710143701A CN100461148C CN 100461148 C CN100461148 C CN 100461148C CN B2007101437010 A CNB2007101437010 A CN B2007101437010A CN 200710143701 A CN200710143701 A CN 200710143701A CN 100461148 C CN100461148 C CN 100461148C
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Abstract
The invention discloses a data chained layer of chip and pack processing method, which comprises the following steps: storing the kind of pack into a kind queue if the data chained layer receives the pack from the chip group; calculating the first number of kinds of pack in the kind queue if the connecting line of chip group and processor is broken; reconstructing the connecting line of chip group and processor; comparing the second affirming order number from the processor after reconstructing the chip group with the first affirming order number to the processor before the connecting line is broken; calculating the second number in kinds of pack without resending according to the second affirming order number if the second affirming order number is different from the first affirming order number; transmitting pack to the processor according to the first and second numbers. The invention can increase the performance of entire system.
Description
Technical field
The present invention is particularly transmitted relevant for the bag between chipset and processor relevant for chipset.
Background technology
Chipset (Chipset) is one group of chip that is positioned on the motherboard, is the indispensable element of motherboard.The function of chipset mainly is the bridge of linking up as processor and other peripheries, spare part.Processor is responsible for computing and deal with data, and required data of processor or the data of finishing dealing with, and all is responsible for conversion by chipset or transmits.Each processor all needs a cover chipset collocation, could finish the work smoothly.
Fig. 1 is the block diagram of a known computer system 100.Computer system 100 comprises chipset 102, processor 104, storer 106 and a plurality of peripherals 112～116.Processor 104 is responsible for handling the data of whole computer system.When the computing of processor 104 needs storage data, just be stored in the storer 106.A plurality of peripherals 112～116 can be hard disk, CD, mouse or the like.When processor 104 is desired access peripherals 112～116, must be through chipset 102 to carry out access; And peripherals 112～116 tendencies to develop also must see through chipset 102 to transmit when sending data to processor 104.Therefore the efficient of data transfer is very big for the usefulness influence of processor between chipset and processor.
Fig. 2 carries out the synoptic diagram that data transmit for the chipset 210 and 240 of the processors of computer system 200.The data that chipset 210 and processor are 240 transmit all, and the division of labor wherein is respectively physical layer (physical layer) 212 and 242, Data Link Layer (dara link layer) 214 and 244, transport layer (transactionlayer) 216 and 246 by bottom to high level for a plurality of stratum.When transport layer was delivered to Data Link Layer with the packet data delivery of desire transmission, Data Link Layer can be disassembled the packet of transport layer again became transmissible least unit on physical network, down sends to physical layer and does substantial transmission.
Yet the line of chipset 210 and 240 physical layers of processor may interrupt sometimes.This moment, the transport layer 216 of chipset 210 just can't cause the decline of system effectiveness to Data Link Layer 214 transfer data packets.If when the line of chipset 210 and 240 physical layers of processor interrupts, make the transport layer 216 of chipset 210 sustainable, just can promote the usefulness of computer system integral body to Data Link Layer 214 transfer data packets.Therefore, when needing a kind of line between chipset and processor to interrupt, still can allow transport layer continue chipset to the Data Link Layer transfer data packets.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of method that is used for Data Link Layer (the data link layer) pack processing of chipset (chipset), to solve the problem that known technology exists.If this Data Link Layer is received bag from a transport layer of this chipset, just the kind with bag deposits bag kind of a Class Queue in, and deposits the data of bag in a bag data queue.When if the line of this chipset and a processor interrupts, calculate first number of bag various types of in this bag kind of Class Queue respectively.Then, after the line of this chipset and this processor is rebuild, first acknowledged sequence number of this chipset bag that this chipset is received from this processor at last before second acknowledged sequence number (ACK serial number) of the bag that this processor is at first received interrupts with line after relatively line is rebuild.If this second acknowledged sequence number is different with this first acknowledged sequence number, calculate various types of second number that need not retransmit the bag that send in this bag kind of Class Queue respectively according to this second acknowledged sequence number.At last, send bag according to described first number and described second number to this processor.
The invention provides the Data Link Layer (data linklayer) of a kind of chipset (chipset).This Data Link Layer comprises bag kind of a Class Queue and a control circuit.If when this Data Link Layer was received bag from a transport layer of this chipset, just the kind with bag deposited in wherein.This control circuit, calculate first number of bag various types of this bag kind of Class Queue when interrupting respectively in order to line from this chipset and a processor, first acknowledged sequence number of this chipset bag that this chipset is received from this processor at last before second acknowledged sequence number (ACK serial number) of the bag that this processor is at first received and line interruption after the line of this chipset and this processor is rebuild the back relatively line is rebuild, if this second acknowledged sequence number and this first acknowledged sequence number do not calculate various types of second number that need not retransmit the bag that send in this bag kind of Class Queue respectively according to this second acknowledged sequence number simultaneously, and send bag to this processor according to described first number and described second number.
The Data Link Layer of chipset of the present invention and be used for the method for its pack processing, when the line between chipset and processor interrupted, therefore the transport layer of chipset still can promote performance of entire system to the Data Link Layer transmission package.
Description of drawings
Fig. 1 is the block diagram of a known computer system;
Fig. 2 is for carrying out the synoptic diagram that data transmit between the chipset of computer system and processor;
Fig. 3 is the block diagram according to chipset of the present invention;
Fig. 4 shows the synoptic diagram according to bag kind Class Queue of the present invention;
Fig. 5 is the process flow diagram according to Data Link Layer method of pack processing when line interrupts of chipset of the present invention.
Embodiment
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, several preferred embodiments cited below particularly, and cooperate appended diagram, be described in detail below.
Fig. 3 is the block diagram according to chipset 300 of the present invention.Chipset 300 comprises physical layer (physicallayer) module 312, Data Link Layer (data link laycr) module 314 and transport layer (transaction layer) 316.When chipset 300 is desired when processor transmits data, at first by chipset 300 transport layer module 316 to Data Link Layer module 314 transfer data packets.Data Link Layer module 314 with digital coding, add frame, debug, and it is synchronous etc. to carry out flow process control, mistake control, link sequential control and sign indicating number frame.Then transmit data to processor by physical layer module 312 by the entity line again.
Data Link Layer module 314 comprises control circuit 322, bag kind of Class Queue 324, bag data queue 326.The transmission flow process of the bag of control circuit 322 control datas link layer 314.Bag kind of Class Queue 324 stores the bag kind that transmitting layer 3 16 is sent to Data Link Layer 314, and bag data queue 326 stores the bag data that transmitting layer 3 16 is sent to Data Link Layer 314.Data Link Layer module 314 still comprises a plurality of first bag kind counters and a plurality of second bag kind counter (not shown), calculates the number of various types of bag respectively in order to the bag kind that stores according to bag kind of Class Queue 324.
In an embodiment, stored bag kind can be divided into 4 kinds in bag kind of the Class Queue 324, is respectively reading order (read command), write command (writecommand), reads and respond order (read response command), response order (response command).For instance, desire to read the data of storer 106, just send reading order to processor 104 when the chipset 102 of Fig. 1; When chipset 102 desires of Fig. 1 with writing data into memory 106, just send write command to processor 104.When processor 104 desires to read the data of peripherals 112～116, and chipset 102 desires are back to processor with the data of peripherals 112～116, just send to read to processor 104 and respond order.In addition, peripherals 112～116 is desired when processor 104 sends some information, and chipset 102 just sends to processor 104 and responds order.For example, during write command configuration successful that 112～116 pairs of processors 104 of peripherals send, chipset 102 just sends to processor 104 and responds order.In in the case, the first bag kind counter and the second bag kind counter just comprise reading order counter, write command counter separately, read and respond command counter, respond command counter, to calculate the number of various types of bag respectively.
Fig. 4 shows the synoptic diagram according to bag kind Class Queue 400 of the present invention.Bag kind of a Class Queue 400 comprises and deposits formation index 402 in, takes out formation index 404, first index 406, and 4 indexs such as second index, 408 grades.Whenever control circuit 312 deposits (push) bag kind in to bag kind of Class Queue 400, deposit formation index 402 in and just progressively increase one, to point to a bag kind that deposits at last.Whenever control circuit 312 receives processor when responding a corresponding acknowledged sequence number, take out formation index 404 and just equal this corresponding acknowledged sequence number, wrap kind to point to the first pen that is not identified taking-ups (pop) as yet.Therefore, the dequeue of asking for index 404 is started to depositing formation index 402 bag kind between the two in, is all stored in bag kind of the Class Queue 400 bag kinds, shown in Fig. 4 bend part.
Fig. 5 is the process flow diagram according to the method 500 of Data Link Layer pack processing when line interrupts of chipset of the present invention.To describe with the chipset 300 of Fig. 3 herein.At first in step 502, whenever Data Link Layer 314 is received a bag from transport layer 316, control circuit 312 just will wrap data storing in bag data queue 326, and control circuit 312 also will wrap kind and be stored in the bag kind Class Queue 324 simultaneously.No matter whether the line between chipset 300 and processor interrupts, and the present invention does not stop transmitting layer 3 16 to continue toward Data Link Layer 314 transport data packets.
If in step 504, when being notified line between chipset 300 and processor to interrupt by physical layer 312, then, control circuit 322 just can calculate the number of stored various bags according to the bag kind that stores in bag kind of the Class Queue 324 in step 506.Control circuit 322 at first points to the position of taking out formation index 404 with first index 406, and this promptly wraps the first stroke bag kind that stores in kind of the Class Queue 400.Then, one by one first index 406 is incremented to the position that deposits formation index 402 in, this promptly wraps the finishing touch bag kind that stores in kind of the Class Queue 400.Whenever first index 406 increases for the moment, the value in the pairing first bag kind counter of the bag kind that control circuit 322 just points to first index 406 adds up one, to add up the number of various types of bag respectively.For instance, if the bag kind that first index 406 points to is a reading order, then the value of the first reading order counter just increases by one; If the bag kind that first index 406 points to is write command, then the value of the first write command counter just increases by one.
After the number accumulative total of various bags finishes, in between the preparatory stage that the line of chipset 300 and processor is set up, control circuit 322 must prevent in step 508 temporarily that transmitting layer 3 16 from continuing to Data Link Layer 314 transmission package, in case terminate between the preparatory stage of line foundation, bag number accumulative total of each first bag kind counter makes a mistake.Furthermore, between the preparatory stage that the line of chipset 300 and processor is set up, control circuit 322 prevents that transmitting layer 3 16 from continuing to need to pass the elm bag needed time of transmission greater than transmitting layer 3 16 to Data Link Layer 314 to the time of Data Link Layer 314 transmission package, and the bag number accumulative total that can take precautions against each first bag kind counter makes a mistake.
Then, after the line of chipset 300 and processor rebulid, chipset 300 just can begin mutual transmission package with processor.The bag that transmits between chipset 300 and processor can have an acknowledged sequence number (ACK serial number).This moment, control circuit 322 just can write down second acknowledged sequence number that line is rebuild the bag that the back self processor receives in step 510, and first acknowledged sequence number that the line of second acknowledged sequence number and step 504 interrupts the bag that preceding chipset 300 self processors receive is compared.If second acknowledged sequence number is identical with first acknowledged sequence number, the expression line is had no progeny in step 504, the acknowledged sequence numbers of sending out of processor not more.Therefore control circuit 322 can be in step 516 directly needs the various types of bag number that sends to processor with the stored value of each first bag kind counter as Data Link Layer, and sends the bag that is stored in the bag data queue 326 to processor in view of the above.
Otherwise if second acknowledged sequence number is different with first acknowledged sequence number, the expression line is had no progeny in step 504, and physical layer 312 is not received the affirmation sequence number that processor sends.That is to say that the bag that physical layer 312 sends is correctly received by processor before line interrupts, but line interrupts subsequently, the affirmation sequence number that causes processor to send is not received by physical layer 312.Therefore control circuit 322 must be rejected the bags that transmit from wrapping earlier more in the data queue 326, just can send bag to processor again.This moment, control circuit 322 can point to the position of taking out formation index 404 with second index 408 earlier in step 512, and this promptly wraps the first stroke bag kind that stores in kind of the Class Queue 400.Then, one by one second index 408 is incremented to the position of the bag correspondence of second acknowledged sequence number, the finishing touch bag kind that this promptly should reject in bag kind of Class Queue 400.Whenever second index 408 increases for the moment, value in the pairing second bag kind counter of the bag kind that control circuit 322 just points to second index 408 adds up one, the number of the various types of bag that need not resend to add up respectively to transmit before line interrupts.
Store the total number of various types of bag in bag kind of the Class Queue 324 this moment in each first package counting facility respectively, and stored the number of the various types of bag that should in bag kind of Class Queue 324, reject in each second package counting facility respectively.Therefore, control circuit 322 can deduct stored value in the pairing second bag kind counter with stored value in each first bag kind counter in step 514, as the various types of bag number of Data Link Layer 314 need, and send the bag that is stored in the bag data queue 326 to processor in view of the above to the processor transmission.
The invention provides a kind of chipset, even when the line between chipset and processor interrupts, its transport layer still can be to the Data Link Layer transmission package.By increase in Data Link Layer bag kind of Class Queue with the kind of storage bag and a plurality of bag kind counter to calculate the number of various types of bag, can after line is rebuild, calculate the number of the various types of bag that should resend, with foundation as the bag transmission.Because when the line between chipset and processor interrupted, therefore the transport layer of chipset still can promote performance of entire system to the Data Link Layer transmission package.
Bright via above embodiment, for those skilled in the art, can use circuit design software and prior art, method of the present invention is embodied in control circuit.In view of the above; the above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100: computer system
102: chipset
104: processor
106: memory
112-116: ancillary equipment
210: chipset
240: processor
212,242: physical layer
214,244: Data Link Layer
216,246: transport layer
300: chipset
312: physical layer
314: Data Link Layer
316: transport layer
322: control circuit
324: bag kind of Class Queue
326: bag data queue
400: bag kind of Class Queue
402: deposit the formation index in
404: take out the formation index
406: the first indexs
408: the second indexs
Claims (11)
1. a method that is used for the Data Link Layer pack processing of chipset is characterized in that, comprises the following steps:
If this Data Link Layer is received bag from a transport layer of this chipset, just the kind with bag deposits bag kind of a Class Queue in, and deposits the data of bag in a bag data queue;
When if the line of this chipset and a processor interrupts, calculate first number of bag various types of in this bag kind of Class Queue respectively;
After the line of this chipset and this processor is rebuild, first acknowledged sequence number of this chipset bag that this chipset is received from this processor at last before second acknowledged sequence number of the bag that this processor is at first received and line interruption after relatively line is rebuild;
If this second acknowledged sequence number is different with this first acknowledged sequence number, calculate various types of second number that need not retransmit the bag that send in this bag kind of Class Queue respectively according to this second acknowledged sequence number; And
Send bag according to described first number and described second number to this processor.
2. the method that is used for the Data Link Layer pack processing of chipset according to claim 1 is characterized in that this method more comprises the following steps:
When the line of this chipset and a processor interrupted, this Data Link Layer continued to receive bag from this transport layer, and deposits the data of bag in this bag data queue; And
After the line of this chipset and this processor is rebuild, should bag data queue take out bag certainly to send to this processor.
3. the method that is used for the Data Link Layer pack processing of chipset according to claim 1 is characterized in that this method more comprises the following steps:
If this second acknowledged sequence number is identical with this first acknowledged sequence number, send the various types of described first number destination packet respectively to this processor;
If this second acknowledged sequence number is different with this first acknowledged sequence number, sends respectively to this processor and various types of to deduct described second corresponding several destination packets by described first number.
4. the method that is used for the Data Link Layer pack processing of chipset according to claim 1, it is characterized in that, this bag kind of Class Queue comprises that one deposits a formation index and a taking-up formation index in, this deposits the formation index in and points to last bag kind that deposits in this bag kind of Class Queue, and this taking-up formation index is pointed in this bag kind Class Queue bag kind that deposits in and do not confirmed by processor at first.
5. the method that is used for the Data Link Layer pack processing of chipset according to claim 4 is characterized in that the calculating of described first number comprises the following steps:
The bag kind of pointing to from this taking-up formation index with one first index is incremented to the bag kind that this deposits the sensing of formation index in one by one; And
Whenever this first index is changed bag kind time-like pointed, respectively wrap kind with a plurality of first bag kind counter accumulative totals respectively according to the bag kind that this first index is pointed to, and obtain described first number.
6. the method that is used for the Data Link Layer pack processing of chipset according to claim 4 is characterized in that the calculating of described second number comprises the following steps:
Be incremented to the bag kind of the bag of this second acknowledged sequence number correspondence one by one from the bag kind of this taking-up formation index sensing with one second index; And
Whenever this second index is changed bag kind time-like pointed, respectively wrap kind with a plurality of second bag kind counter accumulative totals respectively according to the bag kind that this second index is pointed to, and obtain described second number.
7. the method that is used for the Data Link Layer pack processing of chipset according to claim 1 is characterized in that, this method more was included between the preparatory stage that the line of this chipset and this processor sets up, and prevented that this transport layer is to this Data Link Layer transmission package.
8. the Data Link Layer of a chipset is characterized in that, comprising:
One bag kind of Class Queue is if this Data Link Layer just deposits the kind of wrapping wherein in when a transport layer of this chipset is received bag;
One bag data queue is if this Data Link Layer just deposits the data of wrapping wherein in when a transport layer of this chipset is received bag;
One control circuit, calculate first number of bag various types of this bag kind of Class Queue when interrupting respectively in order to line from this chipset and a processor, first acknowledged sequence number of this chipset bag that this chipset is received from this processor at last before second acknowledged sequence number of the bag that this processor is at first received and line interruption after the line of this chipset and this processor is rebuild the back relatively line is rebuild, if this second acknowledged sequence number and this first acknowledged sequence number do not calculate various types of second number that need not retransmit the bag that send in this bag kind of Class Queue respectively according to this second acknowledged sequence number simultaneously, and send bag to this processor according to described first number and described second number.
9. the Data Link Layer of chipset according to claim 8, it is characterized in that, if this second acknowledged sequence number is identical with this first acknowledged sequence number, then this control circuit sends the various types of described first number destination packet respectively to this processor, and if this second acknowledged sequence number is different with this first acknowledged sequence number, then this control circuit sends respectively to this processor and various types of deducts described second corresponding several destination packets by described first number.
10. the Data Link Layer of chipset according to claim 8, it is characterized in that, this bag kind of Class Queue comprises that one deposits a formation index and a taking-up formation index in, this deposits the formation index in and points to last bag kind that deposits in this bag kind of Class Queue, and this taking-up formation index is pointed in this bag kind Class Queue bag kind that deposits in and do not confirmed by processor at first.
11. the Data Link Layer of chipset according to claim 10 is characterized in that, this Data Link Layer more comprises:
A plurality of first bag kind counters, the bag kind that this control circuit points to from this taking-up formation index with one first index is incremented to this one by one and deposits the bag kind that the formation index is pointed in, simultaneously whenever this first index is changed bag kind time-like pointed, the bag kind that the described first bag kind counter points to according to this first index is totally respectively wrapped kind respectively, and obtains described first number; And
A plurality of second bag kind counters, the bag kind that this control circuit points to from this taking-up formation index with one second index is incremented to the bag kind of the bag of this second acknowledged sequence number correspondence one by one, simultaneously whenever this second index is changed bag kind time-like pointed, the bag kind that the described second bag kind counter points to according to this second index is totally respectively wrapped kind respectively, and obtains described second number.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007101437010A CN100461148C (en) | 2007-07-30 | 2007-07-30 | Data chain connecting layer of chip group and method used in processing pack |
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| CNB2007101437010A CN100461148C (en) | 2007-07-30 | 2007-07-30 | Data chain connecting layer of chip group and method used in processing pack |
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| CN101082898A CN101082898A (en) | 2007-12-05 |
| CN100461148C true CN100461148C (en) | 2009-02-11 |
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| CN103368703B (en) * | 2012-04-10 | 2016-08-17 | 华为技术有限公司 | Data package retransmission method, data packet receiving method and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003316724A (en) * | 1999-12-15 | 2003-11-07 | Isei Denshi Kofun Yugenkoshi | Signal transmission device between control chip sets |
| US20050195201A1 (en) * | 2004-03-08 | 2005-09-08 | Sarath Kotamreddy | Queue partitioning mechanism |
| CN1687920A (en) * | 2005-05-30 | 2005-10-26 | 威盛电子股份有限公司 | Main board and control method thereof |
| US20060123206A1 (en) * | 2004-12-03 | 2006-06-08 | Barrett Wayne M | Prioritization of out-of-order data transfers on shared data bus |
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2007
- 2007-07-30 CN CNB2007101437010A patent/CN100461148C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003316724A (en) * | 1999-12-15 | 2003-11-07 | Isei Denshi Kofun Yugenkoshi | Signal transmission device between control chip sets |
| US20050195201A1 (en) * | 2004-03-08 | 2005-09-08 | Sarath Kotamreddy | Queue partitioning mechanism |
| US20060123206A1 (en) * | 2004-12-03 | 2006-06-08 | Barrett Wayne M | Prioritization of out-of-order data transfers on shared data bus |
| CN1687920A (en) * | 2005-05-30 | 2005-10-26 | 威盛电子股份有限公司 | Main board and control method thereof |
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