CN100461142C - Microprocessor apparatus, processor bus system and method of performing a sparse write transaction - Google Patents
Microprocessor apparatus, processor bus system and method of performing a sparse write transaction Download PDFInfo
- Publication number
- CN100461142C CN100461142C CNB2006101011507A CN200610101150A CN100461142C CN 100461142 C CN100461142 C CN 100461142C CN B2006101011507 A CNB2006101011507 A CN B2006101011507A CN 200610101150 A CN200610101150 A CN 200610101150A CN 100461142 C CN100461142 C CN 100461142C
- Authority
- CN
- China
- Prior art keywords
- sparse
- processing
- write
- writes
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
A microprocessor including processor logic and sparse write logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction, which provides one of multiple sparse memory write transactions on the request signals and which provides corresponding enable bits on the address signals. Each sparse memory write transaction corresponds with one of multiple granularities of data. For example, if the sparse memory write transaction is a quad-pumped cache line write for eight quadwords, the enable bits may be a selected one of byte, word, doubleword, quadword, doublequadword, etc., enable bits. A method of performing a sparse write transaction including providing an address and a request for a memory write transaction, indicating that the memory write transaction is a selected sparse write transaction, asserting enable signals for the selected sparse write transaction, and providing data for the sparse write transaction.
Description
Technical field
The present invention relates to a kind of microprocessor, particularly relate to a kind of microprocessor and method thereof of activation variable-width data transmission, in order to solve when the storage space that writes merging is continuously revised write store problem slowly.
Background technology
The storage (non-temporal stores) that writes merging (write combines) and nonvolatile is not kept in the microprocessor, but is writen to memory bus.In quadruple bus (quad-pumped bus) now, the bus that for example most x86 compatible microprocessors is proposed, data transmission to storer is not to be carried out by cache line (cache line) mode (for example eight of 64 byte cache-lines quadwords (quadword)), is carried out by individual other quadword mode exactly.When complete cache line of transmission, then need two clock period to transmit the quadword of eight combinations, and four quadwords be during each cycle of bus clock in transmission, the descriptor in the computing machine " quad-pumped " therefore has been described.If have only the cache line of part to be written into storer, use another kind of data transmittal and routing form at that time, it allows other quadword transmission, and as partial bus communications protocol (bus protocol), the byte enable signal is set indicates byte specific in the quadword of the transmission that is written into storer.Individual other quadword transmission has taken a bus clock cycle.Under this mode, the state status of this technology is not to have allowed 64 continuous bytes to be written into storer in two clock period, and a quadword is written into storer at single clock in the cycle exactly.
Look back the communications protocol of microprocessor bus framework and associated now, and combine observation and how operate down by the program of using about continuous storage space, when sparse in continuous storage space (sparse) data had been modified and have been written into bus, the inventor had noticed that previous mentioned to write to the relevant bus communication agreement of memory bus with data be unhelpful.For instance, commonly be modified in the checkerboard type part (each other double quadword, each other quadword, each other double word (doubleword) or the like) in the video signal impact damper, to change some outward appearances that show.Yet existing microprocessor can not provide and be used for being chosen in quadword and connect under quadword (quadword-by-quadword) mode, except with the granular degree of byte (granularity), is written into the mechanism of the data of storer with any granular degree.Connected storage sparse writes so sets and be written into bus, and this one writes and be limited in other quadword transmission.
To write the relevant data of (combined writes) (for example writing the storage in conjunction with, nonvolatile) in general bigger because with uniting, therefore no matter bus is quadruple bus or other, is disadvantageous for the frequency range that utilizes data bus fully.Because data bus generally operates in than under the slow several-fold clock speed of microcontroller core clock speed, therefore carry out and unite that to write to storer be very important with optimum efficiency.Therefore expectation writes to storer with complete cache line, and in storer, the indivedual key elements in this cache line can be by the activation of the granular degree of variable-width institute.
Summary of the invention
The invention provides a kind of microprocessor, comprise processor logic circuit and the sparse logical circuit that writes.The processor logic circuit indicates a plurality of address signals and a plurality of request signal, writes processing so that address and request to be provided to the cache lines store device.The sparse logical circuit that writes causes the microprocessor logic circuit to provide a plurality of sparse storeies to write one of processing on a plurality of request signals, and the activation position that a plurality of correspondences are provided on a plurality of address signals.Each sparse storer writes one of the granular degree of corresponding a plurality of data (granularity) of handling.
First part of the signable a plurality of address signals of processor logic circuit and a plurality of request signals is to provide address and request, and one second part that indicates a plurality of address signals and a plurality of request signals is to provide a plurality of sparse storeies to write one of processing and a plurality of activations position is provided.The sparse logical circuit that writes causes the processor logic circuit to provide some activations to be positioned at the request signal of the granular degree of corresponding data.The activation position can be the activation position of byte, double word, quadword, two quadwords or the like.
In another embodiment, sparse storer writes and is treated to the quadruple high speed cache lines and writes processing, in order to write eight quadwords.The activation position can be in byte, double word, quadword and the two quadword activations position one of.
The present invention also provides a kind of processor bus system, comprises processor bus, processor and bus agent.Processor bus comprises a plurality of address signals, data-signal and request signal.Processor is in order to control a plurality of address signals and request signal, comprise that with request the sparse storer of the granular degree of width (granularity) of data writes processing and a plurality of activations position is provided, and write processing so that data to be provided to sparse storer in order to control a plurality of data-signals.Bus agent couples memory bus, in order to partial data is write to by a plurality of activations position selected storage address.
Processor indicates first part and the second portion, wherein, first partly comprises that address and the memory lines on a plurality of address signals and a plurality of request signal writes request respectively, and second portion comprises that a plurality of sparse storeies write one of request of processing and a plurality of activations position on a plurality of address signals and a plurality of request signal respectively.Each sparse storer writes a corresponding person of the granular degree of a plurality of width of handling the request designation data.These data wait the granular degree of width comprise byte, word, double word, quadword and two quadword.
Sparse storer writes to handle and comprises that quadruple (quad-pumped) cache line with eight quadwords writes processing, and a plurality of activations position is one of byte, double word, quadword and two quadword activations position of selecting.In certain embodiments, bus agent writes eight quadwords of part with the granular degree of selecting of width according to a plurality of activations position.
The present invention proposes a kind of sparse method that writes processing of carrying out, and at first, provides processor, address and request to write processing to storer.Write by the processor instruction memory that to be treated to a plurality of sparse institutes that write in the processing one of selected.Then, indicate a plurality of enable signals by processor and give the selected sparse processing that writes.Afterwards, provide data to the selected sparse processing that writes by processor.
This carries out the sparse method that writes processing and comprises also by processor and indicate first processing section that wherein, this first processing section provides address and instruction memory to write processing; And comprise by processor indicating second processing section, and this second processing section comprises a plurality of sparse corresponding person of handling in the coding that write.The method also comprises, indicates second processing section by processor with a plurality of activations position, and a plurality of activations position has the corresponding selected sparse granular degree (granularity) of handling coding that writes.The method can comprise, indicates one of selected byte, double word (doubleword), quadword and two quadword (doublequadword) activation position.The method also comprises, receives chosen sparse processings, a plurality of enable signal and the data of writing by bus agent, and according to a plurality of enable signals and with the selected sparse granular degree that processing is determined that writes, writes signal partly.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Fig. 1 represents the synoptic diagram of existing Microprocessor Interface system.
Fig. 2 represents according to the interaction between the signal of the existing Microprocessor Interface system of Fig. 1, reads with execution and handles R1, then carries out three and writes and handle W1, W2 and W3.
The explanation of forms that Fig. 3 represents is in write cycle " B " during the requested part in, if single quadword reason request (REQ) bus is specified, the signal definition of the address signal of address (ADDR) bus.
Fig. 4 represents the synoptic diagram according to the Microprocessor Interface system of the embodiment of the invention.
The explanation of forms that Fig. 5 represents is according to the embodiment of the invention, at RQ cycle " B " during the part in the request signal of REQ bus, to reach the granular degree of variable-width.
The explanation of forms that Fig. 6 represents is at the sparse RQ cycle that writes merging " B " signal definition of giving the address signal of selected ADDR bus in during the part, with finish when the signal indication of REQ bus is sparse write merging write processing the time the granular degree of double word.
The explanation of forms that Fig. 7 represents is at the sparse RQ cycle that writes merging " B " signal definition of giving the address signal of selected ADDR bus in during the part, with finish when the signal indication of REQ bus is sparse write merging write processing the time the granular degree of quadword.
The reference numeral explanation
100～Microprocessor Interface system; 101～microprocessor;
103～bus agent; 105～memory bus;
400～Microprocessor Interface system; 401～microprocessor;
403～bus agent; 405～memory bus;
407～processor logic circuit; 409～sparse the logical circuit that writes;
411～sparse logical circuit.
Embodiment
The present inventor has understood the disadvantage of the frequency range of the processor bus that can't utilize microprocessor fully.Therefore and also notice because processor bus generally operates in than under the slow several-fold clock speed of microcontroller core clock speed, carry out with optimum efficiency and unite that to write to storer be very important.The inventor understands, and specifically, when the sparse data in the connected storage space (sparse data) had been modified and has been written into bus, it was disadvantageous having now and writing to the relevant bus communication agreement of bus with data.Therefore, the inventor has studied a kind of sparse write diagnostics that writes merging (writecombines), and wherein, cache line can the activation of the granular degree of variable-width (granularity) institute, will illustrate with Fig. 1 to 7.
Fig. 1 represents the synoptic diagram of existing Microprocessor Interface system 100.Microprocessor Interface system 100 comprises microprocessor 101 and the bus agent 103 that engages with memory bus 105.The known a plurality of different types of bus agents of bus agent 103 expression those skilled in the art, for example Memory Controller, main frame/PCI bridge or the like.Processor bus 105 comprises the signal that is used for carrying out data processing, comprises bi-directional address bus ADDR, BDB Bi-directional Data Bus DATA and a plurality of control signal.Though understood according to special configuration and structure, address and data bus can have any right quantity signal, and in the embodiment that is narrated, the ADDR bus has 36 signals, with ADDR[35:0] expression; The DATA bus has 64 signals, with DATA[63:0] expression.If for instance, transmission is the granular degree of quadword (quadword), and those skilled in the art can understand only needs ADDR[35:3].A plurality of control signals comprise that bus clock signal BCLK, bi-directional address dodge spacing wave (bidirectional address strobe signal) ADS (indication is in the correctness of address on the ADDR bus), two-way request bus REQ[4:0], BDB Bi-directional Data Bus busy signal DBSY (being indicated), data preparation signal DRDY (provide the device of data to be indicated in during all clock period, data are passed through the DATA bus transfer at this moment) and response bus RS by the entity that provides data in the DATA bus.Two-way request bus REQ[4:0] offered some clarification on the type of the request of processing, the storer quadword that for example the storer coding reads, memory data reads, memory lines writes (eight quadwords), have a byte activation writes.Response bus RS provides the type of processing response, does not for example have data, normal data, absolute write-back (writeback), and it is finished by the DATA bus.In the embodiment of explanation, the RS bus has 3 signals, with RS[2:0] expression; The REQ bus has five signals, with REQ[4:0] expression.
The signal of memory bus 105 is that the microprocessor that difference is very little now provides.Therefore some processors are multiplex address and data in identical signal group, and it is data or address to indicate current that a plurality of control signals are provided.Alternatively, other microprocessor then is to utilize different addresses or data-bus width or control signal.No matter the thin portion of special processor architecture, almost all processors provide signal to be used for and the bus agent communication, need any processing kenel with indication, indicate the parameter of this processing and transmit or receive data.
Fig. 2 represents according to the interaction between the signal of existing Microprocessor Interface system 100, reads with execution and handles R1, then carries out three and writes processing W1, W2 and W3.As shown in the figure, BCLK, ADS, DBSY and DRDY signal and ADDR, REQ, RS and DATA bus are to be that transverse axis is drawn with the time (TIME).For each processing, microprocessor 101 provides the address on the ADDR bus, and bus agent 103 comes this address of strangulation according to the detection of ADS signal.In order to offer some clarification on, represent with low logic level when control signal is labeled, and those skilled in the art can understand also and can represent by high logic level.The operation of above-mentioned processing in the x86 compatible microprocessors and cited respective signal will illustrate with many lists of references, comprise " Pentium Pro and Pentium II System Architecture " book of being edited by TomShanley, it comprises the intentional and purpose reference data about institute.
The periodic table of BCLK clock signal is shown in the top of sequential chart and has cycle numbering, and the sequential of the processing of the state of these signals will be numbered according to the cycle of correspondence and be described.The cycle 1,3,5, and 7 during, the ADS signal is indicated (for example handle request " A " and reach " B " part) with address on the ADDR bus by microprocessor 101, read and handle R1 to ask one, is following three thereafter and is writing processing W1 to W3.Briefly, under negligible delay, can understand actual signal transition and occur in the cycle that is connected in after the icon signal transition with being right after.For instance, the W1 that the falling edge of ADS signal has begun to occur in the rising edge of BLCK signal between clock period 2 and 3 writes processing, and in fact it occurred in during clock period 3 after short relatively the delay.Manyly write processing, for example W1 to W3 generally is performed and writes to storer or other fellow who writes the binding buffer device.
Be provided in cycle in the clock on address bus ADDR and request bus RQE with each relevant parameter of these requests.As shown in the figure, " A " requested part of each processing is with " AA " expression for the ADDR bus, then is to represent with " RA " for the REQ bus." B " requested part of each processing is with " AB " expression for the ADDR bus, then is to represent with " RB " for the REQ bus.Therefore, read or write processing for each, the ADDR bus shows " AA/AB ", and the REQ bus shows " RA/RB ".During " A " in cycle part, the address of ADDR bus control and treatment, and the processing type of REQ bus control request (for example, the storer coding reads, memory data reads, storer write).During " B " in cycle part, under the situation that writes and read processing.The request bus REQ provide treated length, for example eight quadwords or single quadword.If REQ specifies single quadword in during " B " in cycle part, so " B " of ADDR bus part is explained according to the forms 300 of Fig. 3, wherein, address signal ADDR[31:24] be explanation transmission characteristic (for example non-high-speed cache, write in conjunction with, write formula (write-through) or the like), and position signalling ADDR[15:8] be the activation of explanation byte, it indicates the specified byte in other quadword that is written into storer.
Therefore, during the cycle 1, ADDR and REQ bus indicate cache line and read R1.Handle the relevant data of R1 and transmit in during cycle 4 and 5 with reading.During the cycle 3, cache line writes to be handled W1 and is requested by ADDR and REQ bus, and the cache line of being correlated with is write out in during cycle 7 and 8.During the cycle 5, individual other quadword writes to be handled W2 and is requested by ADDR and REQq bus, and the quadword of being correlated with is written in during the cycle 10.If with write transmission W2 relevant revise the part that data are sparse modification impact dampers, during the cycle 7 in, ADDR and REQ bus controlled variable write to next quadword of sparse modification impact damper in the storer.
Fig. 2 and Fig. 3 have illustrated that the sparse modifier area of transmission connected storage is inefficient by other quadword transmission.As mentioned above, existing microprocessor can't provide and be used for explanation and connect under quadword (quadword-by-quadword) mode at quadword, except with the granular degree of byte, is written into the mechanism of selection part of the data of storer with any granular degree.Because the data relevant with the storage buffer that writes merging are generally bigger, be disadvantageous therefore for the complete data bus frequency range that utilizes.And, therefore carry out and unite that to write to storer be very important with optimum efficiency because the data bus general operation is under the slow several-fold clock speed than microcontroller core clock speed.
According to the system and method for the embodiment of the invention, a kind of characteristic of newtype is provided, write writing of merging as sparse, it is an improvement method for existing x86 bus communication agreement.Writing the writing in the processing of merging according to the embodiment of the invention sparse, whole 64 byte cache now are written into storer, and in during " B " of RQ cycle part, indicate the activation position with a kind of method, the method is similar to how to indicate byte at once in individual other quadword writes.This is assigned to the granular degree of width that the sparse monopolizing characteristic that writes has determined the activation position.
Fig. 4 represents the Microprocessor Interface system 400 according to the embodiment of the invention.This Microprocessor Interface system 400 comprises the bus agent 403 that microprocessor 401 engages with memory bus 405.Bus agent 403 can be Memory Controller, main frame/PCI bridge or the like (in conjunction with Fig. 4 supplementary notes).The signal of memory bus 405 is similar in fact to Microprocessor Interface system 400, and with identical in fact method operation, except the value of ADDR and REQ bus is revised in " B " of RQ cycle part, to prepare for the sparse explanation that writes processing that writes merging as described below.Microprocessor 401 comprises processor logic circuit 407 and the sparse logical circuit 409 that writes.Processor logic circuit 407 is in fact similar in appearance to the processor logic circuit (not shown) of microprocessor 101, to engage with the ADDR bus.The sparse logical circuit 409 that writes is to represent with an independent entity, and its inside is coupled to processor logic circuit 407.In selective embodiment, the sparse logical circuit 409 that writes can be contained in the processor logic circuit 407.In one embodiment, sparsely write the some that logical circuit 409 is stored logic circuit (not shown)s.
The sparse logical circuit 409 that writes judges that scheduled transmission to a plurality of zones of the storer of memory bus 405 are sparse or other.If these zones are sparse, sparsely write processing and will be arranged and carry out, think that efficient data transmission prepares.Bus agent 403 comprises sparse logical circuit 411, and it revises the function of bus agent 403, handles to storer with sparse the writing of activation.Specifically, sparse logical circuit 411 activation bus agents 403, with detect, decoding and carry out by microprocessor 401 memory bus that is provided at 405 sparse and write processing.Sparse logical circuit 411 activation bus agents 403 are to write each sparse partial data that writes the selection of processing, and the partial data of this selection is determined by being provided in the sparse a plurality of activations position that writes the requested part of processing.Be assigned to the granular degree of width that the sparse characteristic that writes processing has determined activation.
Fig. 5 represents according to the embodiment of the invention, illustrate during " B " of RQ cycle part in request signal REQ[4:0] the forms 500 of coding example, to reach the granular degree of variable-width.Therefore, position 4:3 is encoded into binary value 00b (wherein, binary signal represented in additional small letter " b "), indicated have double word (doubleword) (32-bit) the sparse storer that writes merging of granular degree write processing.Position 4:3 is encoded into 01b has indicated the sparse write store with the granular degree of quadword (64-bit) to write processing.Similarly, it is (128-bit) granular degree of the two quadwords (doublequadword) of indication that position 4:3 is encoded into 10b, and position 4:3 is encoded into 11b is (16-bit) granular degree of directive (word).Though REQ[4:3] specific coding shown in forms 500, note, in order to instruct the present invention, and consider selectable signal group and coding and without prejudice to original idea of the present invention and scope, the coding and the selection of the bus signals that this is concrete existing are examples.For example, also can consider the granular degree of byte (8-bit).
Fig. 6 represents forms 600, the signal definition that it has given the address signal of selected ADDR bus in having shown during " B " of the sparse RQ cycle that writes merging part, with finish when the signal indication of REQ bus is sparse write merging write processing the time the granular degree of double word.Postpone ID and extended function signal and provide processor at present to x86.Yet, ADDR[31:24] and ADDR[15:8] signal indicates characteristic and byte activation no longer respectively.What replace is, when the indication of REQ bus is sparse when writing writing of merging and handling, this two field is joined together to form double word activation field DE[15:0], the specific double word in being written into the relevant cache line of storer has been indicated in its distinctive position.For sparse write the instruction for, the characteristic value of ADDR bus and byte activation position are replaced by double word activation position.The double word of each double word activation position correspondence in writing eight quadwords of processing.In one embodiment, for instance, the double word activation of each of DE field position is indicated to logical one, with explanation corresponding double word in eight quadwords of the sparse data that write processing that write merging, be written into the double word of the correspondence in the storer, wherein, logical zero is meant that the corresponding double word that is shown in memory bus 405 is left in the basket, and does not change so that keep at the corresponding double word of storer.Under this mode, be modified in the single sparse selection that writes arbitrary double word in the processing that writes merging in conjunction with being possible, for example, each other double word in one 64 byte paragraph of video signal impact damper.
Fig. 7 represents forms 700, the signal definition that it has given the address signal of selected ADDR bus in having shown during " B " of the sparse RQ cycle that writes merging part, with finish when the signal indication of REQ bus is sparse write merging write processing the time the granular degree of quadword.Postpone ID and expanded functionality signal and provide processor at present to x86.Yet, ADDR[31:24] be left in the basket, and ADDR[15:8] signal no longer indicates the byte activation.What replace is ADDR[15:8] formation quadword activation field QE[7:0], the specific quadword in being written into the relevant cache line of storer has been indicated in its distinctive position
As request bus REQ[4:0 in forms 500] the coding example, provide the specific coding of forms 600 and 700 and signal to select, how the present invention provides the sparse variable-width that writes granular degree with instruction.Be noted that the present invention there is no specific granular degree, signal name, value or the processor bus communications protocol that is limited in these examples.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; any technician of this area can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Following right of priority is quoted in this case: No. the 60/696702nd, the U.S. Provisional Application case of submitting on July 5th, 2005; And No. 11/363826, U.S.'s formal application case of submitting on February 28th, 2006.
The pairing U. S. application case of the application is relevant with following U.S. Patent application co-pending, and it has commonly-assigned us and at least one co-inventor.
Sequence number submission date denomination of invention
11/364704 2/28/2006 APPARATUS?AND?METHOD?FOR?SPARSE
LINE?WRITE?TRANSACTIONS
11/369896 3/7/2006 Apparatus?and?method?for?quad-pumped?address?bus
11/374663 3/13/2006 FLEXIBLE?WIDTH?DATA?PROTOCOL
11/379166 4/18/2006 APPARATUS?AND?METHOD?FOR?ORDERING
TRANSACTION?BEATS?IN?A?DATA?TRANSFER
Claims (21)
1. microprocessor with activation variable-width data transmission comprises:
The processor logic circuit in order to indicate a plurality of address signals and a plurality of request signal, writes processing so that an address and a request to be provided to a cache lines store device; And
The sparse logical circuit that writes, couple this processor logic circuit, in order to causing this processor logic circuit on the described request signal, to provide the sparse storer of a plurality of variable-width data transmission to write one of processing, and on described address signal, provide a plurality of activations position to write processing to carry out above-mentioned sparse storer with the corresponding width data of activation;
Wherein, each this sparse storer writes one of data of handling respectively corresponding above-mentioned a plurality of different in width.
2. the microprocessor with activation variable-width data transmission as claimed in claim 1, wherein, this processor logic circuit indicate described address signal and described request signal one first partly so that this address and this request to be provided, and this processor logic circuit indicates one second part of described address signal and described request signal described activation position to be provided and to provide described sparse storer to write one of processing.
3. the microprocessor with activation variable-width data transmission as claimed in claim 2, wherein, this sparse logical circuit that writes causes this processor logic circuit to provide a plurality of different activation positions to write processing with the sparse storer that the different in width data transmission is provided on the described request signal.
4. the microprocessor with activation variable-width data transmission as claimed in claim 3 wherein, describedly provides a plurality of different activation positions to comprise on request signal one of a plurality of following two kinds of data widths are provided: the quadword data width; Double digital data width.
5. the microprocessor with activation variable-width data transmission as claimed in claim 1, wherein, described sparse storer writes one of processing and comprises that a quadruple high speed cache lines writes processing, in order to write eight quadwords.
6. the microprocessor with activation variable-width data transmission as claimed in claim 1, wherein, described corresponding width data comprises one of selected byte, double word, quadword and two quadwords.
7. processor bus system comprises:
One memory bus comprises a plurality of address signals, data-signal and request signal;
One processor, couple this memory bus, in order to control described address signal and described request signal, writing one of processing in the sparse storer that a plurality of variable-width data transmission are provided on the described request signal and on described address signal, to provide a plurality of activations position to write processing to carry out above-mentioned sparse storer, and so that being provided, these data write processing to this sparse storer in order to control described data-signal with the corresponding width data of activation; And;
One bus agent couples this memory bus, with the above-mentioned data that are enabled are write to a selected storage address.
8. processor bus system as claimed in claim 7, wherein, this processor indicates a first and one second partly, this first partly comprises that the address on described address signal and described request signal and a memory lines write request respectively, and this second comprises partly that respectively the described activation position on described address signal and described request signal and a plurality of sparse storer write one of the request of processing.
9. processor bus system as claimed in claim 8 wherein, more provides a plurality of different activation positions to write processing with the sparse storer that the different in width data transmission is provided on the described request signal.
10. processor bus system as claimed in claim 9 wherein, describedly provides a plurality of different activation positions to comprise on request signal one of a plurality of following two kinds of data widths are provided: the quadword data width; Double digital data width.
11. processor bus system as claimed in claim 7, wherein, each this sparse storer writes one of data of handling respectively corresponding above-mentioned a plurality of different in width.
12. processor bus system as claimed in claim 7, wherein, this corresponding width data comprises one of a byte, a double word, a quadword and a pair of quadword.
13. processor bus system as claimed in claim 7, wherein, this sparse storer writes to handle and comprises that a quadruple high speed cache lines writes processing, in order to write eight quadwords.
14. processor bus system as claimed in claim 13, wherein, this bus agent writes the part of these eight quadwords with described corresponding width data according to described activation position.
15. carry out the sparse method that writes processing, comprising for one kind:
Provide a processor, an address signal and a request signal to write processing to a storer;
Indicate this storer to write to be treated to a plurality of sparse institutes that write in the processing one of selected by this processor;
On the described request signal, provide the sparse of a plurality of variable-width data transmission to write one of processing by this processor, and on described address signal, provide a plurality of activations position with the corresponding width data of activation to carry out the above-mentioned sparse processing that writes; And
Provide data to write processing by this processor to selected this is sparse;
Wherein, one of each these sparse data that write the respectively corresponding above-mentioned a plurality of different in width of processing.
16. the sparse method that writes processing of execution as claimed in claim 15, wherein, providing this address signal and this request signal to write to handle to a cache lines store device comprises: by this processor indicate described address signal and described request signal one first partly so that an address and a request to be provided, and one second part that indicates described address signal and described request signal is to provide described activation position and described sparse one of processing that writes is provided.
17. the sparse method that writes processing of execution as claimed in claim 16, wherein, this processor more provides a plurality of different activation positions sparsely to write processing with what the different in width data transmission was provided on the described request signal.
18. the sparse method that writes processing of execution as claimed in claim 17 wherein, describedly provides a plurality of different activation positions to comprise on request signal one of a plurality of following two kinds of data widths are provided: the quadword data width; Double digital data width.
19. the sparse method that writes processing of execution as claimed in claim 15 wherein, describedly sparsely writes one of processing and comprises that a quadruple high speed cache lines writes processing, in order to write eight quadwords.
20. the sparse method that writes processing of execution as claimed in claim 15, wherein, described corresponding width data comprises one of selected byte, double word, quadword and two quadwords.
21. the sparse method that writes processing of execution as claimed in claim 20 also comprises:
Receive by a bus agent that selected this is sparse to write processing, with the above-mentioned data that are enabled are write to a selected storage address.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US69670205P | 2005-07-05 | 2005-07-05 | |
| US60/696,702 | 2005-07-05 | ||
| US11/363,826 | 2006-02-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1892631A CN1892631A (en) | 2007-01-10 |
| CN100461142C true CN100461142C (en) | 2009-02-11 |
Family
ID=37597510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101011507A Active CN100461142C (en) | 2005-07-05 | 2006-07-05 | Microprocessor apparatus, processor bus system and method of performing a sparse write transaction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100461142C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108256645B (en) * | 2018-01-19 | 2021-02-26 | 上海兆芯集成电路有限公司 | Processor with adjustable data bit width |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1117767A (en) * | 1993-12-15 | 1996-02-28 | 硅图像有限公司 | System and method for synchronization in split-level data cache system |
| US5561780A (en) * | 1993-12-30 | 1996-10-01 | Intel Corporation | Method and apparatus for combining uncacheable write data into cache-line-sized write buffers |
| WO2001048621A1 (en) * | 1999-12-29 | 2001-07-05 | Intel Corporation | Quad pumped bus architecture and protocol |
| US6405285B1 (en) * | 1999-06-25 | 2002-06-11 | International Business Machines Corporation | Layered local cache mechanism with split register load bus and cache load bus |
| EP1416390A2 (en) * | 1998-03-31 | 2004-05-06 | Intel Corporation | Cache pollution avoidance instructions |
| US20040199723A1 (en) * | 2003-04-03 | 2004-10-07 | Shelor Charles F. | Low-power cache and method for operating same |
| EP1478204A2 (en) * | 2003-05-15 | 2004-11-17 | Lucent Technologies Inc. | Method and apparatus for performing authentication in a communications system |
-
2006
- 2006-07-05 CN CNB2006101011507A patent/CN100461142C/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1117767A (en) * | 1993-12-15 | 1996-02-28 | 硅图像有限公司 | System and method for synchronization in split-level data cache system |
| US5561780A (en) * | 1993-12-30 | 1996-10-01 | Intel Corporation | Method and apparatus for combining uncacheable write data into cache-line-sized write buffers |
| EP1416390A2 (en) * | 1998-03-31 | 2004-05-06 | Intel Corporation | Cache pollution avoidance instructions |
| US6405285B1 (en) * | 1999-06-25 | 2002-06-11 | International Business Machines Corporation | Layered local cache mechanism with split register load bus and cache load bus |
| WO2001048621A1 (en) * | 1999-12-29 | 2001-07-05 | Intel Corporation | Quad pumped bus architecture and protocol |
| US20040199723A1 (en) * | 2003-04-03 | 2004-10-07 | Shelor Charles F. | Low-power cache and method for operating same |
| EP1478204A2 (en) * | 2003-05-15 | 2004-11-17 | Lucent Technologies Inc. | Method and apparatus for performing authentication in a communications system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1892631A (en) | 2007-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI229259B (en) | A method and related apparatus and computer program product for distributed memory control and bandwidth optimization | |
| CN1069426C (en) | System direct memory access (DMA) support logic for PCI based computer system | |
| US7441064B2 (en) | Flexible width data protocol | |
| US7171526B2 (en) | Memory controller useable in a data processing system | |
| KR100349787B1 (en) | Single chip microcomputer | |
| US5915099A (en) | Bus interface unit in a microprocessor for facilitating internal and external memory accesses | |
| US7797467B2 (en) | Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features | |
| KR940002088B1 (en) | Odd boundary address aligned dma | |
| JP5977094B2 (en) | Flexible flash command | |
| US20040177176A1 (en) | Systems and methods optimizing data transfer throughput of a system on chip | |
| JP2002140289A (en) | Micro-controller dma operation with adjustable word size transfer and address array/increase | |
| CN101589377A (en) | Content-terminated dma | |
| JP2539058B2 (en) | Data processor | |
| US6742058B2 (en) | Memory controller having a multiplexer selecting either second set of input signals or converted signals from first set of input signals by a bus mode input | |
| JPH11509950A (en) | Microcontroller having an N-bit data bus width with less than N I / O pins and method therefor | |
| EP1746497B1 (en) | Apparatus and method for sparse line write transactions | |
| CN100461142C (en) | Microprocessor apparatus, processor bus system and method of performing a sparse write transaction | |
| US5535349A (en) | Data processing system and method for providing chip selects to peripheral devices | |
| US4489395A (en) | Information processor | |
| US7457901B2 (en) | Microprocessor apparatus and method for enabling variable width data transfers | |
| CN100435123C (en) | Apparatus and method for sparse line write transactions | |
| US5805843A (en) | Microprocessor bus interface unit for interfacing an N-bit microprocessor bus to an M-bit memory device | |
| JP2002024158A (en) | Data transfer device and microcomputer | |
| US7073004B2 (en) | Method and data processing system for microprocessor communication in a cluster-based multi-processor network | |
| CN100527115C (en) | Flexible width data protocol |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |