CN100459081C - Making method of solder protruding block - Google Patents
Making method of solder protruding block Download PDFInfo
- Publication number
- CN100459081C CN100459081C CNB2006100287810A CN200610028781A CN100459081C CN 100459081 C CN100459081 C CN 100459081C CN B2006100287810 A CNB2006100287810 A CN B2006100287810A CN 200610028781 A CN200610028781 A CN 200610028781A CN 100459081 C CN100459081 C CN 100459081C
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- layer
- connecting hole
- metal
- passivation layer
- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method to produce solder lugs includes: a semiconductor liner with a top layer metal is provided; a passivation layer is formed on the semiconductor liner; a connection hole is formed on the passivation layer to expose the top layer metal at the bottom; a first metal layer is formed on the passivation layer and in the connection hole; a blocking layer is formed on the first metal layer; the blocking layer is smeared with photo-resist and forms an opening corresponding with the connection hole; a second metal layer is formed in the opening; the photo-resist is removed; etch the first metal layer until the covering layer is exposed; the method has the advantages of simple technique and low cost.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of solder projection.
Background technology
Along with development of semiconductor, chip size is more and more littler, and traditional encapsulation technology is just becoming the bottleneck that the restriction circuit performance improves, and the encapsulation technology of chip also develops into flip-chip (Flip chip) technology by original cutting line ball encapsulation.Flip chip technology (fct) is after chip manufacturing is finished, and goes up at chip outer lead passivation layer (Pad) and forms solder projection (Solder Bump), and the chip that directly will have solder projection after the cutting is attached to circuit board substrate.The circuit board corresponding positions is equipped with the metal contact that is connected with solder projection on the chip.Flip chip technology (fct) reduces to be electrically connected size because it saves chip area, reduces power consumption, increases advantage such as device speed and is widely used.Number of patent application is the manufacture method that 200410099093.3 Chinese patent has been announced a kind of solder projection, its manufacture method forms the solder projection of high-reliability by the method that strip bulge is set and is embedded into solder projection on the contact pins of semiconductor chip, the chip of formation directly is attached on the circuit board by solder projection.
Figure 1A～figure G is a kind of manufacture method of existing flip-chip solder bump.
As shown in Figure 1, semi-conductive substrate 100 is provided, be formed with semiconductor device on the described Semiconductor substrate 100, wherein, etching stop layer 102 is formed by silicon nitride, be formed with low-k (Low k) dielectric layer 103 on described etching stop layer 102, be formed with the dual-damascene structure that is formed by top layer connecting hole 104 and top-level metallic interconnection layer 106 in described dielectric layer 103, the material of described interconnection layer 106 is a copper.
Shown in Figure 1B, on described Semiconductor substrate 100, form an insulating barrier 108, described insulating barrier 108 is passivation layer (Passivation), is used for protecting the semiconductor device below it.The material of insulating barrier 108 is a silicon nitride.On described insulating barrier 108, form an organic coating layer 109.Described cover layer 109 is a kind of synthetic polymerized resin of anticorrosive, high temperature resistant and wearing and tearing, polyimides (Polymide) for example.Spin coating photoresist on described cover layer 109 forms the connecting hole pattern by exposure imaging then, and the cover layer 109 of the bottom of the described connecting hole pattern of etching and insulating barrier 108 form connecting hole 110.Top-level metallic interconnection layer 106 is exposed in connecting hole 110 bottoms.
Shown in Fig. 1 C, deposition one metal level 112 on the described substrate that has a connecting hole 110, described metal level 112 is an aluminium.Spin coating photoresist and form pattern 115 by exposure imaging on described metal level 112, pattern 115 is above described connecting hole 110.
Shown in Fig. 1 D, do not have protected metal level 112 by the etching removal, and remove photoresist 115, form protruding 112a.
Shown in Fig. 1 E, spin coating photoresist 117 on described cover layer 109 and protruding 112a, and remove the photoresist of protruding 112a top by exposure imaging, expose protruding 112a top.
Shown in Fig. 1 F, deposit a barrier layer 114 at described protruding 112a top, described barrier layer 114 is a titanizing tungsten.Electroplate a metal level projection 116 on described barrier layer 114, described metal level 116 is a gold.Titanizing tungsten increases the caking property of gold and aluminium.
Shown in Fig. 1 G, remove described photoresist 117.Form solder projection 116.
At first will form the aluminium projection by photoetching in the forming process of solder projection 116 in the described method, pass through repeatedly photoetching and deposition then, step is more, complex process.
Summary of the invention
The invention provides a kind of manufacture method of flip-chip solder bump, this method can be simplified the manufacturing process of soldering projection.
For achieving the above object, the manufacture method of a kind of solder projection provided by the invention comprises:
Provide one to have the Semiconductor substrate of top-level metallic;
On described Semiconductor substrate, form passivation layer;
On described passivation layer, form the connecting hole that top-level metallic is exposed in the bottom;
On described passivation layer and in the connecting hole, form the first metal layer;
On described the first metal layer, form the barrier layer;
Spin coating photoresist and formation and the corresponding opening of connecting hole on described barrier layer;
In described opening, form second metal level;
Remove described photoresist;
The described barrier layer of etching, the first metal layer are to exposing cover layer.
Described passivation layer is one of them or its combination of silicon nitride, silica, nitrogen-oxygen-silicon compound, polyimides.
The step of described formation connecting hole is:
Spin coating photoresist on described passivation layer;
By exposure imaging with described connecting hole design transfer to photoresist;
The passivation layer of etching connecting hole bottom portion is to exposing top-level metallic;
Remove described photoresist.
Described method further comprises: form a tack coat in described connecting hole and on the passivation layer before forming the first metal layer.
Described the first metal layer is an aluminium.
Described tack coat is tantalum, tantalum nitride, titanium nitride, titanizing tungsten or its combination.
The formation method of described the first metal layer is a physical vapour deposition (PVD).
The first metal layer top of filling in the described connecting hole is higher than the top of passivation layer.
Described barrier layer comprises tantalum, tantalum nitride, titanium nitride, titanizing tungsten, titanium-silicon-nitrogen compound, tungsten, tungsten nitride or its combination.
The deposition process on described barrier layer is physical vapour deposition (PVD), chemical vapour deposition (CVD) or ald.
Described open bottom is exposed the barrier layer.
Described second metal level is a gold, copper, nickel, silver.
The generation type of described second metal level is for electroplating or physical vapour deposition (PVD).
Described method further comprises: anneal under 200～600 degree conditions.
Compared with prior art, the present invention has the following advantages: the step that forms solder projection among the present invention is at first forming passivation layer on substrate, and forms connecting hole on passivation layer, and the formation connecting hole is for solder projection is electrically connected with top-level metallic.In described connecting hole, fill tack coat and the first metal layer, the ground floor metal fills up described connecting hole and exceeds described connecting hole top, with respect to prior art, the present invention does not carry out chemical wet etching by photoetching process to described the first metal layer, to remove the metal level that on cover layer 309, forms simultaneously when the first metal layer of deposition in the connecting hole, but skip this photoetching process, continue deposited barrier layer and form second metal level, then with second metal level as hard mask, etching is removed the described supratectal the first metal layer material that is deposited on simultaneously when forming the first metal layer.Adopt this technology at first to omit a photoetching process, save cost, shorten the manufacturing cycle, secondly, adopt the hard mask of autoregistration, omitted alignment procedures, have higher accuracy with respect to photoetching process as anti-etching trapping layer.
Description of drawings
Figure 1A～Fig. 1 G is a prior art manufacture method profile;
Fig. 2 is the flow chart of the inventive method embodiment;
Fig. 3 A～Fig. 3 J is the generalized section of the inventive method embodiment.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Flip chip technology (fct) more and more is applied in the semi-conductive packaging technology now.Flip chip technology (fct) is after chip manufacturing is finished, and forms at chip outer lead place and forms solder projection (Bump).The solder projection manufacturing process flow diagram as shown in Figure 2 among the present invention.
Provide one to have the Semiconductor substrate (S200) of top-level metallic.Described Semiconductor substrate has been finished the metal interconnected of manufacturing of leading portion device and back segment, wherein device can be that memory device also can be a logical device, interconnection can have the multiple layer metal interconnection line, but comprises a top layer metallic layer at least, and this metal level can be aluminium or copper.
On described Semiconductor substrate, form passivation layer (S210).Described passivation layer is used for protecting top-level metallic and entire chip.Passivation layer can be made up of multilayer, and for example deposition one inorganic layer forms an organic layer then on described inorganic layer earlier.Passivation material is silicon nitride, silica, SRO, nitrogen-oxygen-silicon compound, polyimides or its combination.
On described passivation layer, form the connecting hole (S220) that top-level metallic is exposed in the bottom.By spin coating photoresist on passivation layer, the exposure imaging etching forms connecting hole, and top-level metallic is exposed in the connecting hole bottom.
On described passivation layer and in the connecting hole, form the first metal layer (S230).At first deposition one tack coat in described connecting hole and on the passivation layer deposits the first metal layer then in described connecting hole and on the passivation layer, and the metal of deposition is an aluminium, and the thickness of deposition is for filling up connecting hole at least.
On described the first metal layer, form barrier layer (S240).Described barrier layer comprises tantalum, tantalum nitride, titanium nitride, titanizing tungsten, titanium-silicon-nitrogen compound, tungsten, tungsten nitride or its combination.
Spin coating photoresist and formation and the corresponding opening of connecting hole (S250) on described barrier layer.Described open bottom is exposed the barrier layer.
In described opening, form second metal level (S260).Second metal layer material can be a gold, copper, and nickel, silver, its generation type is physical vapour deposition (PVD), chemical vapour deposition (CVD) or plating.
Remove the described barrier layer of described photoresist and etching, the first metal layer and tack coat to exposing cover layer (S270).Second metal level makes barrier layer and the first metal layer below it not be etched as hard mask.
Be the detailed step of the inventive method below.Fig. 3 A～Fig. 3 J is the generalized section of the inventive method.
As shown in Figure 3A, provide semi-conductive substrate 300, described Semiconductor substrate 300 has been finished the metal interconnected of the device manufacturing of leading portion and back segment, and described Semiconductor substrate 300 comprises a top layer metallic layer at least.Etching stop layer 302 is a silicon nitride, on described etching stop layer 302, be formed with low-k (Low k) dielectric layer 303, be formed with the dual-damascene structure that is formed by top layer connecting hole 304 and top layer metallic layer 306 in described dielectric layer 303, the material of described top layer metallic layer 306 is a copper.
Shown in Fig. 3 B, on described Semiconductor substrate 300, form an insulating barrier 308, the material of insulating barrier 308 is silicon nitride, silica or SRO.On described insulating barrier 308, form a cover layer 309.Cover layer 309 is nitrogen-oxygen-silicon compound (SiON), silicon nitride.Cover layer 309 also can be synthetic polymerized resins anticorrosive, high temperature resistant and wearing and tearing, for example polyimides (Polymide).Insulating barrier and cover layer are formed passivation layer, and the Semiconductor substrate of protection formation device is injury-free, and prolong the life-span of device.
Shown in Fig. 3 C, coating surface activating agent (HMDS) on described cover layer 309, HMDS can strengthen the adhesive power of photoresist and substrate surface.Spin coating photoresist 311 on described cover layer 309 carries out soft roasting (soft bake) to described photoresist then, evaporates the moisture in the photoresist and strengthens adhesive force.Described Semiconductor substrate 300 is sent into exposure system, exposure system is transferred to the pattern on the mask plate on the photoresist 311 by photoetching, after exposure is finished, by postexposure bake with the influence of eliminating the standing wave that produces in the exposure process and described Semiconductor substrate 300 is sent into developing trough it is developed, if select positive glue for use, the part of sensitization will be reacted with developer solution, pass through deionized water rinsing, the photoresist that removal is reacted and produce connecting hole pattern 310a, 310a exposes cover layer 309, described connecting hole pattern 310a relevant position above described top-level metallic 306 in the bottom.
As described in Fig. 3 D, the described connecting hole pattern of etching 310a forms connecting hole 310 in cover layer 309 and insulating barrier 308, and top-level metallic 306 is exposed in described connecting hole 310 bottoms.Cover layer 309 other zones are subjected to the photoresist protection and can be etched.Remove photoresist 311 by ashing (Ashing) and wet-cleaned.
Shown in Fig. 3 E, deposition one tack coat 312 on described cover layer 309 and in the connecting hole 310 forms the first metal layer 313 on described tack coat.Described tack coat 312 is tantalum, tantalum nitride, titanium nitride, titanizing tungsten or its combination.The first metal layer 313 materials are aluminium, and generation type is a physical vapour deposition (PVD).The first metal layer fills up described connecting hole 310 at least.Described tack coat 312 increases the bonding between the first metal layer 313 and the top-level metallic 306 on the one hand, on the other hand as protective layer, protects in the described Semiconductor substrate 300 copper in the top-level metallic 306 not to outdiffusion.Directly do not remove the first metal layer material of cover layer 309 tops among the present invention behind the formation the first metal layer 313 by chemical wet etching technology; but omitted this chemical wet etching technology; directly on the first metal layer 313, continue deposited barrier layer and form second metal level, then with second metal level as the first metal layer in the mask protection connecting hole 310 firmly and the first metal layer material and bonding layer material on the described cover layer 309 of etching.Method of the present invention has been omitted a photoetching process, has saved the time and the cost of technology, and with respect to photoetching process, forming exposing patterns needs exposure machine accurately to aim at, and the hard mask self-registered technology accuracy among the present invention is higher, and has simplified technological process.
Shown in Fig. 3 F, deposition one barrier layer 314 on described the first metal layer.Described barrier layer 314 comprises tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanizing tungsten (TiW), titanium-silicon-nitrogen compound (TiSiN), tungsten (W), tungsten nitride (WN) or its combination, and deposition process is physical vapour deposition (PVD), chemical vapour deposition (CVD) or ald.Described barrier layer 314 stops the caking property of gold diffusion downwards and the increase the first metal layer 313 and second metal level as the barrier layer of the second metal level gold.
Shown in Fig. 3 G, spin coating photoresist 315 walks abreast into opening 316a on described barrier layer 314.Concrete steps are, coating surface activating agent (HMDS) on barrier layer 314 at first at high temperature, and HMDS changes the hydrophilic hydrophobic state on 314 surfaces, barrier layer, can strengthen the adhesive power of photoresist and substrate surface.After cold drawing cooling on described barrier layer 314 spin coating photoresist 315, and adjust its uniformity of thickness agent of photoresist 315 by described Semiconductor substrate rotating speed, described photoresist 315 is carried out soft roasting (soft bake), evaporate the moisture in the photoresist 315 and strengthen it and the adhesive force on barrier layer 314.Described Semiconductor substrate 300 is sent into exposure system, adopt scioptics (through thelens, TTL) or after optical alignment (OA) aims at, exposure system is transferred to the pattern on the mask plate on the photoresist 315 by photoetching, after exposure is finished, by postexposure bake (PEB) with the influence of eliminating the standing wave that produces in the exposure process and described Semiconductor substrate 300 is sent into developing trough it is developed, if select positive glue for use, the part of sensitization will be reacted with developer solution, pass through deionized water rinsing, the photoresist that removal is reacted and the patterns of openings 316a of the company of generation, described opening 316a exposes barrier layer 314 in the bottom, and described patterns of openings 316a is the relevant position above described connecting hole 310.
Shown in Fig. 3 H, in described patterns of openings, form second metal level 316, described second metal level, 316 materials can be gold, copper, nickel, silver.Its generation type is for electroplating or physical vapour deposition (PVD).
Shown in Fig. 3 I, remove photoresist 315 by ashing (ashing) and wet-cleaned.
Shown in Fig. 3 J; described Semiconductor substrate 300 is sent into etching apparatus; and its upper surface carried out etching; second metal level 316 is not etched as barrier layer 314, the first metal layer 313 and the tack coat 312 of hard its lower floor of mask protection, and barrier layer, the first metal layer and tack coat are not etched away to exposing described cover layer 309 by the part of second metal level, 316 protections on the substrate.Described Semiconductor substrate is sent into annealing device under 200～600 degree temperature, carry out annealing in process.Second metal level 316 that forms on Semiconductor substrate is solder projection, and chip links to each other with circuit board by this solder projection.
The step that forms solder projection among the present invention is at first forming passivation layer on substrate, and forms connecting hole on passivation layer, and the formation connecting hole is for solder projection is electrically connected with top-level metallic.In described connecting hole, fill tack coat and the first metal layer, first metal fills up described connecting hole and exceeds described connecting hole top, with respect to prior art, the present invention does not carry out chemical wet etching by photoetching process to described the first metal layer, to remove the metal level that on cover layer 309, forms simultaneously when the first metal layer of deposition in the connecting hole, but skip this photoetching process, continue deposited barrier layer and form second metal level, then with second metal level as hard mask, etching is removed the described supratectal the first metal layer material that is deposited on simultaneously when forming the first metal layer.Adopt this technology at first to omit a photoetching process, save cost, shorten the manufacturing cycle, secondly, adopt the hard mask of autoregistration, omitted alignment procedures with respect to photoetching process, and had higher accuracy as anti-etching trapping layer.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (14)
1, a kind of manufacture method of solder projection is characterized in that comprising:
Provide one to have the Semiconductor substrate of top-level metallic;
On described Semiconductor substrate, form passivation layer;
On described passivation layer, form the connecting hole that top-level metallic is exposed in the bottom;
On described passivation layer and in the connecting hole, form the first metal layer;
On described the first metal layer, form the barrier layer;
Spin coating photoresist and formation and the corresponding opening of connecting hole on described barrier layer;
In described opening, form second metal level;
Remove described photoresist;
The described barrier layer of etching, the first metal layer are to exposing passivation layer.
2, the method for claim 1 is characterized in that: described passivation layer is one of them or its combination of silicon nitride, silica, nitrogen-oxygen-silicon compound, polyimides.
3, the method for claim 1 is characterized in that: the step that forms connecting hole is:
Spin coating photoresist on described passivation layer;
By exposure imaging with described connecting hole design transfer to photoresist;
The passivation layer of etching connecting hole bottom portion is to exposing top-level metallic;
Remove described photoresist.
4, the method for claim 1 is characterized in that, this method further comprises: form a tack coat in described connecting hole and on the passivation layer before forming the first metal layer.
5, the method for claim 1 is characterized in that: described the first metal layer is an aluminium.
6, method as claimed in claim 4 is characterized in that: described tack coat is tantalum, tantalum nitride, titanium nitride, titanizing tungsten or its combination.
7, the method for claim 1 is characterized in that: the formation method of described the first metal layer is a physical vapour deposition (PVD).
8, the method for claim 1 is characterized in that: the first metal layer top that forms in the described connecting hole is higher than the top of passivation layer.
9, the method for claim 1 is characterized in that: described barrier layer comprises tantalum, tantalum nitride, titanium nitride, titanizing tungsten, titanium-silicon-nitrogen compound, tungsten, tungsten nitride or its combination.
10, the method for claim 1 is characterized in that: the deposition process on described barrier layer is physical vapour deposition (PVD), chemical vapour deposition (CVD) or ald.
11, the method for claim 1 is characterized in that: described open bottom is exposed the barrier layer.
12, the method for claim 1 is characterized in that: described second metal level is gold, copper, nickel, silver.
13, the method for claim 1 is characterized in that: the generation type of described second metal level is for electroplating or physical vapour deposition (PVD).
14, the method for claim 1 is characterized in that, this method further comprises: anneal under 200～600 degree conditions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100287810A CN100459081C (en) | 2006-07-10 | 2006-07-10 | Making method of solder protruding block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100287810A CN100459081C (en) | 2006-07-10 | 2006-07-10 | Making method of solder protruding block |
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| Publication Number | Publication Date |
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| CN101106095A CN101106095A (en) | 2008-01-16 |
| CN100459081C true CN100459081C (en) | 2009-02-04 |
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| CNB2006100287810A Expired - Fee Related CN100459081C (en) | 2006-07-10 | 2006-07-10 | Making method of solder protruding block |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101789032B (en) * | 2009-07-23 | 2012-07-18 | 芯原微电子(上海)有限公司 | Design method and structure thereof of physical layout of CUP weld pad zone |
| CN112635396A (en) * | 2020-12-15 | 2021-04-09 | 上海集成电路研发中心有限公司 | Method for forming metal cobalt interconnection layer and tungsten metal contact hole layer |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0513421A (en) * | 1991-07-04 | 1993-01-22 | Tanaka Kikinzoku Kogyo Kk | Bump forming device |
| CN1431681A (en) * | 2002-01-03 | 2003-07-23 | 台湾积体电路制造股份有限公司 | Method for encapsulation in chip level by use of electroplating mask of elastic body |
| US20040180296A1 (en) * | 2002-01-30 | 2004-09-16 | Taiwan Semiconductor Manufacturing Company | Novel method to improve bump reliability for flip chip device |
| US20050051894A1 (en) * | 2003-09-09 | 2005-03-10 | Intel Corporation | Thick metal layer integrated process flow to improve power delivery and mechanical buffering |
| US20060076677A1 (en) * | 2004-10-12 | 2006-04-13 | International Business Machines Corporation | Resist sidewall spacer for C4 BLM undercut control |
| US20060105560A1 (en) * | 2004-11-16 | 2006-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming solder bumps of increased height |
-
2006
- 2006-07-10 CN CNB2006100287810A patent/CN100459081C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0513421A (en) * | 1991-07-04 | 1993-01-22 | Tanaka Kikinzoku Kogyo Kk | Bump forming device |
| CN1431681A (en) * | 2002-01-03 | 2003-07-23 | 台湾积体电路制造股份有限公司 | Method for encapsulation in chip level by use of electroplating mask of elastic body |
| US20040180296A1 (en) * | 2002-01-30 | 2004-09-16 | Taiwan Semiconductor Manufacturing Company | Novel method to improve bump reliability for flip chip device |
| US20050051894A1 (en) * | 2003-09-09 | 2005-03-10 | Intel Corporation | Thick metal layer integrated process flow to improve power delivery and mechanical buffering |
| US20060076677A1 (en) * | 2004-10-12 | 2006-04-13 | International Business Machines Corporation | Resist sidewall spacer for C4 BLM undercut control |
| US20060105560A1 (en) * | 2004-11-16 | 2006-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming solder bumps of increased height |
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| CN101106095A (en) | 2008-01-16 |
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