CN100452319C - Making method for silicide damaged by low plasma inducing growth - Google Patents

Making method for silicide damaged by low plasma inducing growth Download PDF

Info

Publication number
CN100452319C
CN100452319C CNB200610028945XA CN200610028945A CN100452319C CN 100452319 C CN100452319 C CN 100452319C CN B200610028945X A CNB200610028945X A CN B200610028945XA CN 200610028945 A CN200610028945 A CN 200610028945A CN 100452319 C CN100452319 C CN 100452319C
Authority
CN
China
Prior art keywords
silicide
damaged
making method
low plasma
inducing growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB200610028945XA
Other languages
Chinese (zh)
Other versions
CN101106088A (en
Inventor
陈俭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CNB200610028945XA priority Critical patent/CN100452319C/en
Publication of CN101106088A publication Critical patent/CN101106088A/en
Application granted granted Critical
Publication of CN100452319C publication Critical patent/CN100452319C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a method to produce silicide of low plasma induced damage. Helium, neon, and their combination with argon are taken as industrial gases, and cobalt, nickel, and rare earth metal film are deposited with the physical gas phase deposition method. And metal silicide is produced with the self-aligned silicide technique. The invention can lower common plasma damages in the process of semiconductor silicide production. Compatible with prior arts, the invention is simple in operation.

Description

The making method for silicide of damaged by low plasma inducing growth
Technical field
The present invention relates to a kind of method of manufacturing technology of semiconductor integrated circuit, particularly relate to a kind of making method for silicide of semiconductor technology manufacturing process.
Background technology
Along with the characteristic size of semiconductor device is further dwindled, the further reduction of junction depth has also proposed further demand for development for semi-conducting material and technology.Such as, high drive current, high switching response speed, low signal delay, high s/n ratio or the like.Particularly, when forming, require low square resistance and low contact resistance to reduce signal delay for the silicide of polycrystalline grid, active area; Low simultaneously electric leakage is to reduce noise.Yet to a certain extent, these two problems are a pair of contradiction.
As solution, corresponding cobalt silicide, nickel silicide and some rare earth element silicides arise at the historic moment.Silicide process is towards low silicon consumption, fabricating low-defect-density, low temperature, fast and not damaged develop.For example in silicide growth technology, the material of silicide gradually from TiSi2 to CoSi2 up to NiSi to some in the future possible rare earth element silicides; Temperature controlling is reduced to 400 ℃~500 ℃ from 600 ℃~700 ℃ original scopes, up to 250 ℃.
At present, the formation of silicide is still according to film growth, thermal annealing, and chemical treatment and then the flow process of annealing such are made.Be made as example with cobalt silicide and a field-effect transistor, shown in Fig. 1,2, wherein, Fig. 2 a is pending transistor schematic; Use physical vapor method (generally being magnetically controlled DC sputtering) on the whole surface of Fig. 2 a, to deposit one deck cobalt film (referring to Fig. 2 b) then.Because cobalt meeting and pasc reaction generate cobalt silicide, but do not react with silicon dioxide simultaneously, utilize this characteristic, in ensuing rapid thermal anneal process, cobalt and a backing material monocrystalline and a polysilicon reaction formation high resistant cobalt silicide (referring to Fig. 2 C) mutually; Utilize suitable selective chemical corrosive liquid to remove unreacted metal then, also stay a cobalt silicide that has generated simultaneously, and carried out annealing for the second time, make a cobalt silicon change the cobalt disilicide (referring to Fig. 2 d) of low-resistance phase into.
In this process, a lot of local results of good control needing to obtain that need are arranged.Wherein, how deposit cobalt films (nickel film and corresponding rare earth element film) is a very crucial step process.This process is generally realized by physical vaporous deposition, comprises preheating, and the reverse sputtering etching is removed natural oxidizing layer and other residues, sputter.
The reverse sputtering etching is used to remove natural oxidizing layer and other residues on the silicon chip, so that the reaction that film metal that deposits later and silicon can be good.As shown in Figure 3, feed the inert gas argon gas earlier in reaction chamber, silicon slice placed places and connects AC power on the pedestal.Under the effect of radio frequency AC power, argon gas ionization forms plasma, produces positive argon ion bombardment silicon chip, utilizes splash effect to pound silicon chip the natural oxidizing layer on the silicon chip and other residues, extracts vacuum chamber out by vacuum pump again.
Subsequent thin film deposition generally adopts the technology of direct current sputtering.As shown in Figure 4, in reaction chamber, feed the inert gas argon gas earlier; Target connects the negative pole of DC power supply as negative electrode.When added voltage reached certain value, argon gas ionization formed plasma, produced the positive ion bombardment negative electrode, made it to produce metallic atom and ion.Metallic atom and ion that sputter produces have suitable energy, and deposit forms the corresponding metal film on the bombardment silicon chip, gives silicon chip with energy delivery simultaneously.
But such process is brought many problems.For the reverse sputtering etching, its realization is that the argon ion bombardment by high energy produces splash effect and removes natural oxide film and residue, almost without any selectivity.Therefore, in actual production, be easy to simultaneously cause damage, particularly form very big damage, cause very big electric leakage in the place of the wedge angle of some active areas and isolation camp oxide for silicon substrate.
Same, the sputter procedure subsequently faces equally because the damage problem that the existence of plasma causes.Difference is a little to some extent, because different with reverse sputtering operating pressure and energy coupled modes, at this moment hot electron, metallic atom, ion and ar atmo, ion bombard silicon chip jointly, bring various plasma damages equally.Cause the damage of PN junction depletion region such as metal and silicon substrate interface injustice, produce electric leakage (this shows particularly significantly) in nickel silicide, the energetic charges gate oxide of flowing through makes the gate oxide deterioration cause integrity problem.Excessive power is delivered to and makes the silicon temperature variation cause technology instability or the like on the silicon chip.
So the key of problem is to reduce the energy and the momentum of lotus energy particle, particularly, reduces the energy and the momentum of argon ion in the reverse sputtering etching exactly, the metallic atom in the sputter and the energy of argon and momentum.
In order to address this problem, there has been certain methods to adopt.For the reverse sputtering etching,, perhaps use other energy coupled modes instead as replacing single power supply with a plurality of power supplys.For sputter, add a cover permanent magnet on target, the electronics that relies on the magnetic field outside being dispersed in that gas ionization is produced is done cycloid motion in magnetic field under the effect of Lorentz force, thereby improved ionization efficient, reduce ionization voltage, the energy and the momentum of lotus energy particle are reduced.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of making method for silicide of damaged by low plasma inducing growth, can reduce common plasma damage in the existing semiconductor silication thing manufacturing process, and compatible existing processes is simple to operate simultaneously.
For solving the problems of the technologies described above, the making method for silicide of damaged by low plasma inducing growth of the present invention is to adopt following technical scheme to realize:
The combination of adopting helium, neon and they and argon gas is as working gas, and any film in physical vaporous deposition deposit cobalt, nickel or the rare earth metal is then according to self-aligned silicide prepared metal silicide.
Described physical vaporous deposition comprises having the silicon chip of figure, preheats, and the reverse sputtering etching is removed natural oxidizing layer and other residues, sputter.
Described sputter comprises direct current or radio-frequency magnetron bias sputtering, long-throw sputtering and combination thereof.
Because adopt said method, as inert gas elements, argon is bigger than helium and neon atomic weight, corresponding, under same speed, for silicon substrate, the damage that ar atmo brought is much bigger.And, mist for the He-Ne argon, because famous Penning effect causes ionization voltage to descend greatly (can reach three or 1/4th), the energy of corresponding lotus energy particle (as electronics, intert-gas atoms ion and metallic atom ion) has descended greatly.
Compare with existing method, because helium, neon make the plasma damage in the silicide manufacturing process be reduced to minimum with respect to the reduction that the low atomic weight of argon and Penning effect cause ionization voltage, and compatible existing technology and equipment, with low cost, simple and easy to do.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is existing cobalt silicide manufacture craft flow chart;
Fig. 2 is existing cobalt self-aligned silicide manufacture craft flow chart;
Fig. 3 is existing reverse sputtering etching technics schematic diagram;
Fig. 4 is existing magnetically controlled DC sputtering process schematic representation;
Fig. 5 is the making method for silicide process chart of damaged by low plasma inducing growth of the present invention.
Embodiment
The present invention proposes a kind of preparation method who is used for the required film of metal silicide of semiconductor production, the difference of it and existing method maximum is to adopt the inert gas of combination of helium, neon and they and argon gas as working gas, any film in physical vaporous deposition deposit cobalt, nickel or the rare earth element is produced the self-aligned silicide prepared metal silicide that adopts according to general semiconductor then.
As shown in Figure 5, the concrete implementation step of the making method for silicide of damaged by low plasma inducing growth of the present invention is as follows:
The first step to having the silicon chip of figure, preheats.
In second step, the mist that adopts helium, neon and they and argon gas is as working gas, the natural oxidizing layer of reverse sputtering etching silicon chip surface and other residues (as the particle that drops in residual photoresist and some air etc.).
In the 3rd step, the mist that adopts helium, neon and they and argon gas is as working gas, any film in the certain thickness cobalt of sputtering deposit, nickel or other rare earth metal.
Thickness is by time control, and different membrane materials, different equipment be because the sputter rate difference, asynchronism(-nization), and thickness is approximately respectively 8 nanometers for cobalt, nickel or other rare earth metal thin film, about 12 nanometers and tens nanometers.
Described sputter comprises direct current or radio-frequency magnetron bias sputtering, long-throw sputtering and combination thereof.
The 4th step because cobalt, nickel or other rare earth metal meeting and pasc reaction generate needed silicide, but do not react with silicon dioxide simultaneously, utilize this characteristic, next the first time low temperature thermal annealing.
The 5th step, utilize suitable selective chemical escharotica to remove unreacted metal then, also stay the silicide that has generated simultaneously.
In the 6th step, carry out the higher temperature annealing second time again; Then clean with suitable chemical liquid.
Above-mentioned the 5th, six described cleanings of step can be adopted different chemical liquids.For example, the 5th step was adopted twice cleaning, and the admixing medical solutions of ammoniacal liquor and hydrogen peroxide cleans once, and the mixed liquor with sulfuric acid and hydrogen peroxide cleans once more for the second time.Also available heat hydrochloric acid and hydrogen peroxide mix liquid.Then the 6th step can clean once with same soup.
In the 7th step, silicide preparation technology flow process finishes.

Claims (3)

1, a kind of making method for silicide of damaged by low plasma inducing growth, it is characterized in that: the combination of adopting helium, neon and they and argon gas is as working gas, any film in physical vaporous deposition deposit cobalt, nickel or the rare earth metal is then according to self-aligned silicide prepared metal silicide.
2, the making method for silicide of damaged by low plasma inducing growth according to claim 1 is characterized in that: described physical vaporous deposition, comprise having the silicon chip of figure, and preheat; The reverse sputtering etching is removed natural oxidizing layer and other residues; Sputter.
3, the making method for silicide of damaged by low plasma inducing growth according to claim 2 is characterized in that: described sputter comprises direct current or radio-frequency magnetron bias sputtering, long-throw sputtering and combination thereof.
CNB200610028945XA 2006-07-14 2006-07-14 Making method for silicide damaged by low plasma inducing growth Expired - Fee Related CN100452319C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB200610028945XA CN100452319C (en) 2006-07-14 2006-07-14 Making method for silicide damaged by low plasma inducing growth

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB200610028945XA CN100452319C (en) 2006-07-14 2006-07-14 Making method for silicide damaged by low plasma inducing growth

Publications (2)

Publication Number Publication Date
CN101106088A CN101106088A (en) 2008-01-16
CN100452319C true CN100452319C (en) 2009-01-14

Family

ID=38999907

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB200610028945XA Expired - Fee Related CN100452319C (en) 2006-07-14 2006-07-14 Making method for silicide damaged by low plasma inducing growth

Country Status (1)

Country Link
CN (1) CN100452319C (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531454B (en) * 2012-07-03 2016-08-17 中国科学院微电子研究所 Semiconductor device manufacturing method
CN106571287A (en) * 2015-10-12 2017-04-19 上海新昇半导体科技有限公司 Method for forming epitaxial layer
CN106683996B (en) * 2017-02-14 2020-05-01 上海华虹宏力半导体制造有限公司 Metal silicide and method for manufacturing contact hole on metal silicide
CN112331411B (en) * 2019-09-20 2023-05-26 深圳市腾业格威胶粘制品有限公司 Preparation method of low-temperature-resistant high-resistance transparent conductive film

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6730547B2 (en) * 2001-08-30 2004-05-04 Micron Technology, Inc. Integrated circuit device and fabrication using metal-doped chalcogenide materials
US20040144639A1 (en) * 2003-01-27 2004-07-29 Applied Materials, Inc. Suppression of NiSi2 formation in a nickel salicide process using a pre-silicide nitrogen plasma

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6730547B2 (en) * 2001-08-30 2004-05-04 Micron Technology, Inc. Integrated circuit device and fabrication using metal-doped chalcogenide materials
US20040144639A1 (en) * 2003-01-27 2004-07-29 Applied Materials, Inc. Suppression of NiSi2 formation in a nickel salicide process using a pre-silicide nitrogen plasma
US6998153B2 (en) * 2003-01-27 2006-02-14 Applied Materials, Inc. Suppression of NiSi2 formation in a nickel salicide process using a pre-silicide nitrogen plasma

Also Published As

Publication number Publication date
CN101106088A (en) 2008-01-16

Similar Documents

Publication Publication Date Title
TWI524432B (en) Method and system for depositing a thin-film transistor
CN105518827B (en) The method for realizing seamless cobalt gap filling
JP4142753B2 (en) Sputtering target, sputtering apparatus, semiconductor device and manufacturing method thereof
TWI738410B (en) Target for use in plasma processing chamber and plasma processing chamber
TW201923893A (en) High energy atomic layer etching
CN100452319C (en) Making method for silicide damaged by low plasma inducing growth
TW200300571A (en) Semiconductor device having a low-resistance gate electrode
TW201939074A (en) Light wave separation structures and methods of forming light wave separation structures
JP6929940B2 (en) Methods and equipment using PVD ruthenium
CN109979829A (en) Silicon carbide activates method for annealing
WO2014113148A1 (en) In situ chamber clean with inert hydrogen helium mixture during wafer process
CN101447454B (en) Method for adjusting grid work function of fully-silicified metal grid
US6806172B1 (en) Physical vapor deposition of nickel
US9257291B2 (en) Method for forming a silicide layer at the bottom of a hole and device for implementing said method
TW202012677A (en) Doping techniques
JPH0987839A (en) Method and apparatus for thin film formation
CN112054053B (en) Preparation method of SiC-based ohmic contact with ultrahigh heat dissipation performance
US8987102B2 (en) Methods of forming a metal silicide region in an integrated circuit
KR20110031882A (en) Method of silicide formation by adding graded amount of impurity during metal deposition
Ushiki et al. Improvement of gate oxide reliability for tantalum-gate MOS devices using xenon plasma sputtering technology
Ushiki et al. Reduction of plasma-induced gate oxide damage using low-energy large-mass ion bombardment in gate-metal sputtering deposition
JP2011040513A (en) Method of manufacturing semiconductor device and semiconductor device
US20030003694A1 (en) Method for forming silicon films with trace impurities
JP2012238637A (en) Sputtering method and sputtering apparatus
US20230115130A1 (en) Methods for preparing metal silicides

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

Effective date: 20140115

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI

TR01 Transfer of patent right

Effective date of registration: 20140115

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Patentee before: Shanghai Huahong NEC Electronics Co., Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090114

Termination date: 20200714