CN100451796C - Thin film transistor structure - Google Patents
Thin film transistor structure Download PDFInfo
- Publication number
- CN100451796C CN100451796C CNB2006101671916A CN200610167191A CN100451796C CN 100451796 C CN100451796 C CN 100451796C CN B2006101671916 A CNB2006101671916 A CN B2006101671916A CN 200610167191 A CN200610167191 A CN 200610167191A CN 100451796 C CN100451796 C CN 100451796C
- Authority
- CN
- China
- Prior art keywords
- electrode
- film transistor
- transistor structure
- thin
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The disclosed structure of Thin Film Transistor (TFT) is in use for liquid crystal display of transistors. The TFT includes a grid, a first electrode, a second electrode, a dielectric layer, and a channel. The structure of transistor uses superposition area between first electrode and grid to form parasitic capacitance not drifted by technological flow. Thus, the invention can eliminate external compensation capacitance, and raise aperture rate.
Description
Technical field
The present invention relates to a kind of thin-film transistor structure, particularly relate to a kind of thin-film transistor structure that is used for a transistor liquid crystal display (TFT-LCD).
Background technology
In recent years, the development of flat-panel screens is more and more rapider, has replaced traditional cathode-ray tube display gradually.Flat-panel screens now mainly contains following several: organic light emitting diode display (OrganicLight-Emitting Diodes Display; OLED), plasma scope (Plasma DisplayPanel; PDP), LCD (Liquid Crystal Display; LCD) and Field Emission Display (Field Emission Display; FED) etc.Wherein control the thin film transistor (TFT) (TFT) of the open and close of each pixel in these flat-panel screens, be one of quite critical assembly in these flat-panel screens.
In the panel manufacture process, keep technological process to stablize and to guarantee that just processing quality is good, and then improve fabrication yield.But in manufacture process, because the difference of environmental baseline, technological parameter can produce skew, causes the TFT meeting on the panel that the electrical specification skew be arranged because the region is different, and for example the stray capacitance of TFT can present the height distribution along with the zones of different of panel.This stray capacitance phenomenon pockety can make the voltage jump skewness that panel causes because of stray capacitance everywhere, and then produces film flicker (flicker) phenomenon.
Generally speaking,, can nearby design a building-out capacitor that links to each other with TFT, be used for eliminating the influence of process shifts the TFT stray capacitance at TFT originally in order to suppress film flicker.But, increasing building-out capacitor, the panel that will account for can be used as the area of luminous component, therefore can cause aperture opening ratio (being pixel light-emitting area and pixel total area ratio) to reduce.Simultaneously, excessive building-out capacitor can cause the voltage amplitude of beating excessive, also needs to avoid as far as possible.
In view of this, provide the transistor arrangement of the shared region area of building-out capacitor in a kind of effective minimizing circuit layout, for this reason the technical field problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide a kind of thin film transistor (TFT), solve the variety of issue that exists in the above-mentioned known technology.
To achieve these goals, (Thin Film Transistor, TFT) structure is used for a transistor liquid crystal display (TFT-LCD) to the invention provides a kind of thin film transistor (TFT).This thin film transistor (TFT) comprises a grid, one first electrode, one second electrode, a dielectric layer and a passage (channel) layer.This grid is connected to the one scan line of this LCD, and area is contained a perform region of this TFT structure.This first electrode is positioned at the both sides of this perform region.This second electrode is positioned at the centre of this perform region.This dielectric layer is between this grid and this perform region.This channel layer is positioned at this first and second electrode below, electrically connects with this first and second electrode.Wherein, in the TFT perform region that this gate area contains, this first electrode is parallel with this second electrode, and one of them is connected to a pixel electrode of this LCD this first electrode and this second electrode, and another electrode is connected to a data line of this LCD.
To achieve these goals, the present invention also provides a kind of thin film transistor (TFT) (Thin FilmTransistor, TFT) structure has been used for a transistor liquid crystal display (TFT-LCD).This thin film transistor (TFT) comprises a grid, one first electrode, one second electrode, a dielectric layer and a channel layer.This grid is connected to the one scan line of this LCD, and area is contained a perform region of this TFT structure.This first electrode has two branches, is positioned at the centre of this perform region.This second electrode has three branches, lays respectively at the centre and the both sides of this perform region.This dielectric layer is between this grid and this perform region.This channel layer is positioned at this first and second electrode below, electrically connects with this first and second electrode.Wherein, the branch of this second electrode lays respectively at the both sides of the branch of this first electrode, in the TFT perform region that this gate area contains, this first electrode is parallel with this second electrode, one of them is connected to a pixel electrode of this LCD this first electrode and this second electrode, and another electrode is connected to a data line of this LCD.
Whereby, the present invention can provide a thin film transistor (TFT), has stray capacitance when technology produces skew, is not subjected to bias effect, and keeps stable advantage.Simultaneously, because do not need extra building-out capacitor, increasing the thin-film transistor structure area when obtaining higher conducting electric current, stray capacitance can not increase considerably.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is for looking synoptic diagram on the first embodiment of the present invention;
Fig. 2 is the cut-away section synoptic diagram of first embodiment; And
Fig. 3 is for looking synoptic diagram on the second embodiment of the present invention.
Wherein, Reference numeral:
1 thin-film transistor structure, 11 main TFT
12 attached TFT 111 first electrodes
112 second electrodes, 113 third electrodes
114 the 4th electrodes, 115 grids
116 silicon nitride layers, 117 amorphous silicon layers
118 perform regions
3 thin-film transistor structures, 31 main TFT
32 attached TFT 311 first electrodes
312 second electrodes, 313 third electrodes
314 the 4th electrodes, 315 grids
Embodiment
At first please refer to Fig. 1, it is for looking synoptic diagram on the thin-film transistor structure 1 of first embodiment of the invention.Thin-film transistor structure 1 comprises a main TFT 11 and an attached TFT 12.Main TFT 11 and attached TFT 12 are the mutual electrically connect of parallel way, and share a grid 115.Wherein main TFT 11 comprises one first electrode 111 and one second electrode 112, and wherein second electrode 112 has a lateral dimension, i.e. width, and both are connected respectively to drain electrode and the source electrode of main TFT 11.Attached TFT 12 comprises a third electrode 113 and one the 4th electrode 114, is connected respectively to drain electrode and the source electrode of attached TFT 12.Second electrode 112 and the 4th electrode 114 are electrical connected, and first electrode 111 is connected to different pixels electrode (not shown) with third electrode 113, and second electrode 112 is connected to a data line (not shown) simultaneously.In present embodiment and following examples, source electrode is only different nominally with drain electrode, in order to providing and receiving end of hole or electronics to be provided, and does not have the process variations of essence.
In the present embodiment, the drain electrode and source electrode between passage, with and grid 115 between, form a perform region, within the zone that grid 115 areas are contained.And first electrode 111 is parallel with second electrode 112, has the passage length homogeneity with the passage that keeps TFT.Wherein first electrode 111 with the direction of channel parallel, overlap with this grid 115 and extend outside this perform region, just this first electrode 111 covers perform regions, and extends outside it.In the present embodiment, first electrode 111 has a lateral dimension with grid 115 overlappings place, and promptly width is 1 to 10 μ m, and is preferable, is 4 to 7 μ m; Second electrode also has a lateral dimension simultaneously, and promptly width is 1 to 10 μ m, and is preferable, is 4 to 7 μ m.When skew takes place in technological parameter, for example the technology of first electrode 111 is because of aiming at the not good skew that produces, the part that first electrode, 111 left sides extend outside the perform region may be offset to the right, this moment, first electrode, 111 right sides extended the part skew to the right synchronously outside the perform region, and therefore the total area of first electrode, 111 covering perform regions does not still change.First electrode 111 does not change with the total area that grid 115 overlaps yet simultaneously.Because the capacitance of the electric capacity of dull and stereotyped kenel is by top electrode and the bottom electrode overlapping area and the decision of dielectric layer wherein of electric capacity.Therefore it is constant with the total area that grid 115 overlaps to keep first electrode 111, and the stray capacitance between the grid that can realize main TFT 11 and the drain electrode produces when being offset in technology, is not subjected to bias effect, and keeps stable.
In addition, in the present embodiment, when attached TFT 12 also realizes that by structure technology produces skew, still keep stablizing the effect of parasitic capacitance value.The 4th electrode 114 of wherein attached TFT l2 directly links to each other with second electrode 112, and the horizontal expansion direction that overlaps at attached TFT 12 perform regions and third electrode 113, grid 115 has a concave shape, when making third electrode 113 extend outside the perform region, center section does not overlap with grid 115, and only two ends and grid 115 form the overlapping of two places.Like this, when skew takes place in technological parameter, for example the technology of third electrode 113 is because of aiming at the not good skew that produces, this moment, third electrode 113 integral body were with simultaneous bias, therefore first electrode 113 does not change with the total area that grid 115 overlaps, can realize that the grid of attached TFT 12 and the stray capacitance between the drain electrode when technology produces skew, are not subjected to bias effect, and keep stable.
In the present embodiment, first electrode 111 is that with third electrode 113 fundamental purposes the area that keeps overlapping with grid 115 is not influenced by process shifts, so first electrode 111 need be designed to partly overlap with grid 115 and extend outside the grid 115 with third electrode 113.In the present embodiment, first electrode 111 stretches out for the parallel channels direction with third electrode 113, and under different layouts, but first electrode 111 stretches out with third electrode 113 also vertical channel direction.
Simultaneously, because do not need extra building-out capacitor, increasing the thin-film transistor structure area when obtaining higher conducting electric current, stray capacitance can not increase considerably.
Fig. 2 be among Fig. 1 along the diagrammatic cross-section of the main TFT 11 of AA ' line rip cutting, wherein have a silicon nitride layer 116 between grid 115 and the perform region 118, as a dielectric layer.And below first electrode 111 and second electrode 112, have a channel layer, in the present embodiment, this channel layer is an amorphous silicon layer 117, electrically connects with first electrode 111 and second electrode 112, in order to the passage as the carrier circulation.
Then please refer to Fig. 3, it is for looking synoptic diagram on the thin-film transistor structure 3 of second embodiment of the invention.Thin-film transistor structure 3 comprises a main TFT 31 and an attached TFT 32.Main TFT 31 and attached TFT 32 also are the mutual electrically connect of parallel way, and share a grid 315.Wherein main TFT31 comprises one first electrode 311 and one second electrode 312, is connected respectively to drain electrode and the source electrode of main TFT 31.Attached TFT 32 comprises a third electrode 313 and one the 4th electrode 314, is connected respectively to drain electrode and the source electrode of attached TFT 312.Wherein second electrode 312 and the 4th electrode 314 are electrical connected, and first electrode 311 is connected to different pixels electrode (end shows among the figure) with third electrode 313, and second electrode 312 is connected to a data line (not shown) simultaneously.
In the present embodiment, the drain electrode and source electrode between passage, with and grid 315 between, form a perform region, within the zone that grid 315 areas are contained.First electrode 311 has two branches, is positioned at the centre of this perform region, and second electrode 312 has three branches simultaneously, lays respectively at the centre and the both sides of this perform region; Wherein the branch of first electrode 311 and second electrode 312 is staggered, and promptly the branch of second electrode 312 lays respectively at the both sides of the branch of first electrode 311, and parallel to each other, has the passage length homogeneity with the passage that keeps TFT.Wherein first electrode 311 with the direction of channel vertical, overlap with this grid 315 and extend outside this perform region, promptly this first electrode 311 covers perform regions, and extends outside it.In the present embodiment, each branch of first electrode 311 has a lateral dimension, i.e. width, be 1 to 10 μ m, preferable, be 4 to 7 μ m, the medial fascicle of second electrode 312 has a lateral dimension, and promptly width is 1 to 10 μ m, preferable, be 4 to 7 μ m, second electrode 312 and grid 315 overlappings place, be both sides branch and grid 315 overlappings place, respectively have a lateral dimension, i.e. width, be 1 to 10 μ m, preferable, be 4 to 7 μ m.When skew takes place in technological parameter, for example the technology of first electrode 311 is because of aiming at the not good skew that produces, the part that first electrode, 311 left sides extend outside the perform region may be offset to the right, this moment, first electrode, 311 right sides extended the part skew to the right synchronously outside the perform region, and therefore the total area of first electrode, 311 covering perform regions does not still change.First electrode 311 does not change with the total area that grid 315 overlaps yet simultaneously.Identical with first embodiment, it is constant with the total area that grid 315 overlaps to keep first electrode 311, and the stray capacitance between the grid that can realize main TFT 31 and the drain electrode produces when being offset in technology, is not subjected to bias effect, and keeps stable.
In addition, in the present embodiment, when attached TFT 32 also reaches technology generation skew by structure, still keep stablizing the purpose of parasitic capacitance value.The 4th electrode 314 of wherein attached TFT 32 directly links to each other with second electrode 312, and the grid 315 of attached TFT 32 has a concave shape, when making third electrode 313 extend outside the perform region, center section does not overlap with grid 315, and only two ends and grid 315 form the overlapping of two places.Like this, when skew takes place in technological parameter, for example the technology of third electrode 313 is because of aiming at the not good skew that produces, this moment, third electrode 313 integral body were with simultaneous bias, therefore first electrode 313 does not change with the total area that grid 315 overlaps, can realize that the grid of attached TFT 32 and the stray capacitance between the drain electrode when technology produces skew, are not subjected to bias effect, and keep stable.Simultaneously, because do not need extra building-out capacitor, increasing the thin-film transistor structure area when obtaining higher conducting electric current, stray capacitance can not increase considerably.
In the present embodiment, first electrode 311 is identical with first embodiment with the principle of design of third electrode 313, does not repeat them here.Under different layouts, but first electrode 311 stretches out with third electrode 313 also parallel channels direction.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (19)
1, a kind of thin-film transistor structure, be used for a transistor liquid crystal display (TFT-LCD), it is characterized in that, comprise: a main thin-film transistor structure and an attached thin-film transistor structure, described main thin-film transistor structure and described attached thin-film transistor structure are the mutual electrically connect of parallel way, and this main thin-film transistor structure comprises:
One grid is connected to the one scan line of this LCD, and this gate area contains one first perform region of this main thin-film transistor structure;
One first electrode is positioned at the both sides of this first perform region;
One second electrode is positioned at the centre of this first perform region;
One first dielectric layer is between this grid and this first perform region; And
One channel layer is positioned at this first and second electrode below, electrically connects with this first and second electrode;
Wherein, in first perform region of this main thin film transistor (TFT) that this gate area contains, this first electrode is parallel with this second electrode, one of them is connected to a pixel electrode of this LCD this first electrode and this second electrode, and another electrode is connected to a data line of this LCD;
This attached thin-film transistor structure and this main thin-film transistor structure are shared a grid, and this gate area contains the territory, a secondary service area of this attached thin-film transistor structure, and this attached thin-film transistor structure comprises:
One third electrode is positioned at the side in this territory, secondary service area;
One the 4th electrode is positioned at the centre in this territory, secondary service area and is electrically connected to this second electrode;
One second dielectric layer is between this grid and this territory, secondary service area; And
One amorphous silicon layer is positioned at the 3rd and the 4th electrode below, electrically connects with the 3rd and the 4th electrode.
2, thin-film transistor structure according to claim 1 is characterized in that, this first electrode of part is in channel direction of parallel this main thin-film transistor structure and the overlapping of this grid and extend outside this first perform region.
3, thin-film transistor structure according to claim 1 is characterized in that, this first electrode of part is in a channel direction and the overlapping of this grid of vertical this main thin-film transistor structure and extend outside this first perform region.
4, thin-film transistor structure according to claim 1 is characterized in that, this first dielectric layer is made by silicon nitride.
5, thin-film transistor structure according to claim 1 is characterized in that, one of them is the source electrode of this main thin-film transistor structure for this first electrode and this second electrode, and another electrode is the drain electrode of this main thin-film transistor structure.
6, thin-film transistor structure according to claim 1 is characterized in that, this channel layer is made by amorphous silicon.
7, thin-film transistor structure according to claim 1 is characterized in that, it is 1 to 10 μ m that this first electrode and this grid overlapping part have a lateral dimension.
8, thin-film transistor structure according to claim 1 is characterized in that, it is 1 to 10 μ m that this second electrode has a lateral dimension.
9, thin-film transistor structure according to claim 1 is characterized in that, this third electrode and this grid form several zones that overlaps.
10, a kind of thin-film transistor structure, be used for a transistor liquid crystal display (TFT-LCD), it is characterized in that, comprise a main thin-film transistor structure and an attached thin-film transistor structure, described main thin-film transistor structure and described attached thin-film transistor structure are the mutual electrically connect of parallel way, and this main thin-film transistor structure comprises:
One grid is connected to the one scan line of this LCD, and this gate area contains one first perform region of this main thin-film transistor structure;
One first electrode has two branches, is positioned at the centre of this first perform region;
One second electrode has three branches, lays respectively at the centre and the both sides of this first perform region;
One first dielectric layer is between this grid and this first perform region; And
One channel layer is positioned at this first and second electrode below, electrically connects with this first and second electrode;
Wherein, the branch of this second electrode lays respectively at the both sides of the branch of this first electrode, in the territory, secondary service area of this main thin film transistor (TFT) that this gate area contains, this first electrode is parallel with this second electrode, one of them is connected to a pixel electrode of this LCD this first electrode and this second electrode, and another electrode is connected to a data line of this LCD;
This attached thin-film transistor structure and this main thin-film transistor structure are shared a grid, and this gate area contains the territory, a secondary service area of this attached thin-film transistor structure, and this attached thin-film transistor structure comprises:
One third electrode is positioned at the side in this territory, secondary service area;
One the 4th electrode is positioned at the centre in this territory, secondary service area and is electrically connected to this second electrode;
One second dielectric layer is between this grid and this territory, secondary service area; And
One amorphous silicon layer is positioned at the 3rd and the 4th electrode below, electrically connects with the 3rd and the 4th electrode.
11, thin-film transistor structure according to claim 10 is characterized in that, two branches of this first electrode overlap and extend outside this first perform region at a channel direction of parallel this main thin-film transistor structure and this grid.
12, thin-film transistor structure according to claim 10 is characterized in that, two branches of this first electrode are in a channel direction and the overlapping of this grid of vertical this main thin-film transistor structure and extend outside this first perform region.
13, thin-film transistor structure according to claim 10 is characterized in that, this first dielectric layer is made by silicon nitride.
14, thin-film transistor structure according to claim 10 is characterized in that, one of them is the source electrode of this main thin-film transistor structure for this first electrode and this second electrode, and another electrode is the drain electrode of this main thin-film transistor structure.
15, thin-film transistor structure according to claim 10 is characterized in that, this channel layer is made by amorphous silicon.
16, thin-film transistor structure according to claim 10 is characterized in that, it is 1 to 10 μ m that the per minute brace of this first electrode has a lateral dimension.
17, thin-film transistor structure according to claim 10 is characterized in that, it is 1 to 10 μ m that the medial fascicle of this second electrode has a lateral dimension.
18, thin-film transistor structure according to claim 10 is characterized in that, it is 1 to 10 μ m that the both sides branch of this second electrode and this grid overlapping part respectively have a lateral dimension.
19, thin-film transistor structure according to claim 10 is characterized in that, this third electrode and this grid form several zones that overlaps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101671916A CN100451796C (en) | 2006-12-26 | 2006-12-26 | Thin film transistor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101671916A CN100451796C (en) | 2006-12-26 | 2006-12-26 | Thin film transistor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1987626A CN1987626A (en) | 2007-06-27 |
| CN100451796C true CN100451796C (en) | 2009-01-14 |
Family
ID=38184475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101671916A Active CN100451796C (en) | 2006-12-26 | 2006-12-26 | Thin film transistor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100451796C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190088751A1 (en) * | 2017-09-20 | 2019-03-21 | Boe Technology Group Co., Ltd. | Thin film transistor and manufacturing method therefor, array substrate, and display device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101414083B (en) * | 2007-10-16 | 2010-06-30 | 瀚宇彩晶股份有限公司 | LCD display panel, pixel structure and switch device |
| CN102254917B (en) * | 2011-07-07 | 2014-05-21 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN205067935U (en) * | 2015-11-05 | 2016-03-02 | 京东方科技集团股份有限公司 | Array baseplate and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02285326A (en) * | 1989-04-27 | 1990-11-22 | Toshiba Corp | Active matrix type liquid crystal display element |
| US5097297A (en) * | 1988-03-18 | 1992-03-17 | Seiko Epson Corporation | Thin film transistor |
| CN1470076A (en) * | 2000-10-12 | 2004-01-21 | 三洋电机株式会社 | Transistor and display comprising it |
| US20040125250A1 (en) * | 2002-12-31 | 2004-07-01 | Hyun-Tak Park | Structure of switching device for liquid crystal display device and fabrication method thereof |
| US6906385B2 (en) * | 2003-03-04 | 2005-06-14 | Samsung Electronics Co., Ltd. | Amorphous-silicon thin film transistor and shift resister having the same |
-
2006
- 2006-12-26 CN CNB2006101671916A patent/CN100451796C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5097297A (en) * | 1988-03-18 | 1992-03-17 | Seiko Epson Corporation | Thin film transistor |
| JPH02285326A (en) * | 1989-04-27 | 1990-11-22 | Toshiba Corp | Active matrix type liquid crystal display element |
| CN1470076A (en) * | 2000-10-12 | 2004-01-21 | 三洋电机株式会社 | Transistor and display comprising it |
| US20040125250A1 (en) * | 2002-12-31 | 2004-07-01 | Hyun-Tak Park | Structure of switching device for liquid crystal display device and fabrication method thereof |
| US6906385B2 (en) * | 2003-03-04 | 2005-06-14 | Samsung Electronics Co., Ltd. | Amorphous-silicon thin film transistor and shift resister having the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190088751A1 (en) * | 2017-09-20 | 2019-03-21 | Boe Technology Group Co., Ltd. | Thin film transistor and manufacturing method therefor, array substrate, and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1987626A (en) | 2007-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10032846B2 (en) | Display device | |
| US11175549B2 (en) | Display substrate, display panel and display device | |
| US7626205B2 (en) | Semiconductor device and electro-optical device | |
| US9053986B2 (en) | Semiconductor device and flat panel display including the same | |
| US20170160611A1 (en) | Low temperature poly-silicon tft substrate | |
| US10997911B2 (en) | Pixel driving circuit, pixel structure and manufacturing method thereof | |
| US10424630B2 (en) | Organic light emitting diode display | |
| JP2006065322A (en) | Capacitor and capacitor apparatus | |
| US20180158405A1 (en) | A control component for a current-driven optical media | |
| KR102663635B1 (en) | Light emitting device and display device including the same | |
| CN110071147A (en) | Display panel and electronic equipment | |
| EP2889912B1 (en) | Organic light emitting diode display device | |
| CN100451796C (en) | Thin film transistor structure | |
| JP6462035B2 (en) | Backplane substrate and organic light emitting display device using the same | |
| US10068956B2 (en) | Organic light emitting display | |
| US20240164162A1 (en) | Display panel and display apparatus | |
| JP2016171102A (en) | Thin film transistor | |
| CN107293256A (en) | Pixel circuit, electroluminescent display panel and display device | |
| US7079093B2 (en) | Organic light emitting diodes display | |
| US10868098B2 (en) | OLED display panel and OLED display | |
| CN110071146B (en) | Display panel and electronic device | |
| CN110473883B (en) | Array substrate and OLED display device | |
| KR100693365B1 (en) | Active matrix substrate and display device | |
| US8184226B2 (en) | Thin film transistor structure | |
| US9563084B2 (en) | Liquid crystal display device and array substrate thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |