CN100449457C - Method for regulating CPU arithmetic speed in electronic apparatus - Google Patents
Method for regulating CPU arithmetic speed in electronic apparatus Download PDFInfo
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- CN100449457C CN100449457C CNB2005100690309A CN200510069030A CN100449457C CN 100449457 C CN100449457 C CN 100449457C CN B2005100690309 A CNB2005100690309 A CN B2005100690309A CN 200510069030 A CN200510069030 A CN 200510069030A CN 100449457 C CN100449457 C CN 100449457C
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Abstract
The present invention relates to a method for adjusting the clock speed of a central processing unit of an electronic device. The method comprises the steps that a first system load is obtained according to the active time of the central processing unit in a first time section; the clock speed of the central processing unit is determined according to the first system load.
Description
Technical field
The present invention relates to a kind of method of central processing unit arithmetic speed of adjustment one electronic installation, the arithmetic speed of particularly a kind of central processing unit of dynamic adjustment one electronic installation when the different system load is to reach the method for effective power management.
Background technology
It is very general that mobile phone has become in recent years gradually, and price descends stably and makes that the social broad masses of going up are afforded.Because the continuous lifting of science and technology and technological layer on the market, at set intervals, will be seen the mobile phone release that function is more, more powerful.And mobile phone manufacturer is in order to satisfy all types of consumers' different demands, also glad new science and technology and the technology utilized added more multiselect item and function within the mobile phone of its manufacturing, the intelligent mobile phone of for example selling fast on the market (smartphone), or use the portable electronic devices (Microsoft Window MobileDevice) of microsoft operation system, multimedia application that can execution itself or can carry out the application program of other exploitation because of its open platform (open platform).But because the function of mobile phone is become stronger day by day, the arithmetic capability of processor also must promote to some extent to deal with numerous and diverse system load, and relatively electric power consumption also can improve thereupon.And mobile phone all uses rechargeable type battery (rechargeable battery) to provide this mobile phone required operating voltage at present.Because the power capacity of this rechargeable type battery itself is limited, so but the bigger rechargeable type battery of electrification capacity is to increase the running time of this mobile phone, yet the rechargeable type battery that power capacity is bigger can increase the volume and the weight of this mobile phone simultaneously, therefore can cause this mobile phone not portable, become important topic so how to reduce the power consumption of this mobile phone, when the power consumption of this mobile phone reduces, then do not influencing under original running time, then but the electrification capacity is less for this mobile phone, volume is little, and lightweight rechargeable type battery is manipulated with the user that is more convenient for.
And on the whole existing power management (power management) mode can reach the purpose of adjusting whole electric quantity consumption by the arithmetic speed of adjusting central processing unit or voltage, the user mode that is to say and processor little when system load is not to be in full load, electric power management mechanism just can downgrade the speed of processor or voltage to reach purpose of power saving, and when system load becomes big, based on considering of entire system usefulness, electric power management mechanism just can be adjusted to processor the highest arithmetic speed (full speed) or heighten running voltage, causes the situation when machine to take place to avoid the application program processing speed to cross slowly even can't handle.As for the method for existing detection system load with the utilization rate of processor, can be by the temperature of monitoring processor, when the temperature drift of processor then represents the utilization rate of processor and system load bigger; Or by the current sinking that measures processor, then represent the utilization rate of processor and system load big and be in fully loaded state when the current sinking of processor is bigger than normal, the utilization rate of then representing processor when the current sinking of processor is on the low side is less and may be in the state of low utilization rate or leave unused (idle) with system load.
Yet the method for the utilization rate of existing detection system load and processor, owing to need additionally set up nextport hardware component NextPort to measure the correlation parameter of processor, for example set up temperature sensor (temperature sensor) with measuring temperature or set up the current measurement circuit to measure current sinking etc., so can increase extra cost and take mechanism's configuration space, so how to find out the electrical source consumption of effective saving mobile phone and need not additionally increase cost and the scheme that takies volume, just be the problem of required effort now.
Summary of the invention
The present invention provides a kind of arithmetic speed of central processing unit when the different system load of dynamic adjustment one electronic installation, to reach the method for effective power management, to solve the above problems.
The present invention discloses the method for the central processing unit arithmetic speed of a kind of adjustment one electronic installation, and it includes the following step: (a) draw one first system load the start-up time in a very first time interval according to this central processing unit; And the arithmetic speed that (b) determines this central processing unit according to this first system load.
Description of drawings
Fig. 1 adjusts the process flow diagram of the central processing unit arithmetic speed of an electronic installation for the present invention.
Fig. 2 is the synoptic diagram of the central processing unit operating state of electronic installation of the present invention.
Fig. 3 is the time relationship synoptic diagram of the three phases of flow process of the present invention.
The reference numeral explanation
Step 100,102,104,106,108,110,112,114,116,118,120,122.
Embodiment
See also Fig. 1, Fig. 1 adjusts the process flow diagram of central processing unit (centralprocessing unit) arithmetic speed (clock speed) of an electronic installation for the present invention.This electronic installation is to can be a portable electronic devices, and for example for using the mobile phone of the WINCE of Microsoft operating system, method of the present invention is to include the following step:
Step 100: beginning.
Step 102: draw one first system load (system loading) start-up time (activetime) in a very first time interval according to this central processing unit.
Step 104: whether first system load of judging this very first time interval is greater than one first threshold value, if greater than this first threshold value, execution in step 106; If less than this first threshold value, then execution in step 112.
Step 106: whether the existing arithmetic speed of judging this central processing unit was once downgraded, if, execution in step 108; If not, then execution in step 110.
Step 108: adjust the highest arithmetic speed of arithmetic speed to (fullspeed) of this central processing unit, and execution in step 110.
Step 110: the arithmetic speed of in one second time interval, keeping this central processing unit.
Step 112: judge that whether second system load in one the 3rd time interval be later than this very first time interval is greater than one second threshold value, if greater than this second threshold value, execution in step 106; If less than this second threshold value, then execution in step 114.
Step 114: judgement is later than the interior tertiary system of one the 5th time interval of the 3rd time interval and whether unites load greater than one the 3rd threshold value, if greater than the 3rd threshold value, and execution in step 106; If less than the 3rd threshold value, then execution in step 116.
Step 116: whether the arithmetic speed of judging this central processing unit greater than a minimum arithmetic speed, if, execution in step 118; If not, then execution in step 120.
Step 118: the arithmetic speed of this central processing unit is reduced (the speed adjustment of (the minimum arithmetic speed of the highest arithmetic speed-this central processing unit of this central processing unit)/this central processing unit at interval).
Step 120: the arithmetic speed of keeping this central processing unit is in this minimum arithmetic speed.
Step 122: finish.
Describe above-mentioned method in detail at this, at first aspect the system load calculating of this central processing unit, be with start-up time of this central processing unit in certain section time interval and divided by this section time interval.For instance, see also Fig. 2, Fig. 2 is the synoptic diagram of the central processing unit operating state of electronic installation of the present invention.When if operating system is being carried out certain scheduling processing (schedule), the unloading phase that this central processing unit then being in, and when system load was big, the arithmetic speed of this central processing unit just can be this highest arithmetic speed; If operating system need not to carry out any scheduling when handling, the arithmetic speed that this central processing unit then can enter the idle stage and downgrade this central processing unit is to zero.And in interval T1 of a time, be to be this time section of high arithmetic speed for the running clock of this central processing unit the start-up time of this central processing unit, therefore sum A=A1+A2+A3+A4+...+An start-up time of this central processing unit in this time interval T1, and system load S (the %)=A/T1 (%) in this time interval T1.
As for the calculating of each start-up time and each standby time (idle time), can calculate by the count information that operating system provided.For instance, the calculating of A1 can be converted to a very first time count value of starting state and the one second time counting value that is converted to idle state by present starting state by last idle state by the reading system counter after start for start-up time, again this second time counting value is deducted this very first time count value and draws A1 start-up time, the calculating of D1 then can deduct the 3rd time counting value this second time counting value and draw D1 standby time by reading this second time counting value and being converted to one the 3rd time counting value of next starting state by idle state again for standby time.Therefore can draw each start-up time and each standby time by the aforementioned calculation mode, and and then the system load that can draw each time section, that is to say this first system load be in this very first time interval start-up time sum divided by this very first time interval, this second system load be in the 3rd time interval start-up time sum divided by the 3rd time interval, the load of this tertiary system system be in the 5th time interval start-up time sum divided by the 5th time interval.
See also Fig. 3, Fig. 3 is the time relationship synoptic diagram of the three phases of flow process of the present invention.Next just begin to carry out the phase one of Prediction System load earlier, in this phase one, can the Prediction System load whether be about to become big, and the very first time interval of estimated time is very short in the phase one, is about 1 to 3 second.When this first system load during greater than this first threshold value, then the Prediction System load is about to become big, wherein this first threshold value can set up on their own according to design requirement, for example can be made as 50%, because it is big that the Prediction System load is about to become, so the arithmetic speed of this central processing unit must be adjusted to the highest arithmetic speed that to deal with system load, when the existing arithmetic speed of this central processing unit was once downgraded, then the arithmetic speed adjustment of this central processing unit must be returned this highest arithmetic speed, afterwards execution in step 110 again; In step 110, if when the existing arithmetic speed of this central processing unit is not downgraded or the arithmetic speed of this central processing unit has been adjusted back this during high arithmetic speed, then can keep the arithmetic speed of this central processing unit in this second time interval, meaning can wait for whether the Prediction System load of carrying out the phase one behind this second time interval once more is about to the action that becomes big.As for this second time interval is can be interval for long than this very first time, is about about 25 seconds to 35 seconds.If when this first system load is not greater than this first threshold value in the phase one, then the Prediction System load is not about to become big, and just can enter subordinate phase this moment.
Subordinate phase is for being used for the supervisory system load, meeting be judged whether system is in the big state of charge capacity or be the little steady state (SS) of a charge capacity (stable condition) in this subordinate phase, this is by chance to be in the less or idle steady state (SS) of charge capacity for fear of system in the phase one, but be about to carry out the scheduling processing afterwards and enter the bigger state of charge capacity, thereby cause the erroneous judgement of system load state.And the 3rd time interval of estimated time can be longlyer in subordinate phase, is about 20 to 30 seconds.When this second system load during greater than this second threshold value, even if this moment, the utilization rate of this central processing unit did not reach use fully, then judgement system now is in the big state of charge capacity, wherein this second threshold value can set up on their own according to design requirement, for example this second threshold value can be made as: this first threshold value * (1+ (the existing arithmetic speed of the highest arithmetic speed-this central processing unit of this central processing unit)/(the minimum arithmetic speed of the highest arithmetic speed-this central processing unit of this central processing unit)), that is to say the number percent of the highest and minimum arithmetic speed gap that this first threshold value is improved shared this central processing unit arithmetic speed of gap of the highest arithmetic speed of this central processing unit and existing arithmetic speed, to become this second threshold value.Because the judgement system now is in the big state of charge capacity, so the time be not suitable for reducing the arithmetic speed of this central processing unit, and the arithmetic speed of this central processing unit must be adjusted to the highest arithmetic speed that can deal with system load.In like manner, when the existing arithmetic speed of this central processing unit was once downgraded, then the arithmetic speed adjustment of this central processing unit must be returned this highest arithmetic speed, afterwards execution in step 110 again; In step 110, if when the existing arithmetic speed of this central processing unit is not downgraded or the arithmetic speed of this central processing unit has been adjusted back this during high arithmetic speed, then can in this second time interval, keep the arithmetic speed of this central processing unit, meaning can wait for whether the Prediction System load of carrying out the phase one behind this second time interval once more is about to the action that becomes big, yet the time interval in this wait also can be another the 4th time interval, wherein the 4th time interval can be greater than the 3rd time interval, meaning i.e. the 4th time interval can be not equal to this second time interval, and it can set up on their own according to design requirement.If when this second system load is not greater than this second threshold value in subordinate phase, judge that promptly present system is not in the big state of charge capacity, just can enter the phase III this moment.
Whether can the Prediction System load be about to become big in the phase III, its purpose with the phase one is identical, and the 5th time interval of estimated time is very short in the phase III, is about 1 to 3 second.When this tertiary system system load during greater than the 3rd threshold value, then the Prediction System load is about to become big, wherein the 3rd threshold value can set up on their own according to design requirement, for example can be made as the value identical with this first threshold value, as 50%, because it is big that the Prediction System load is about to become, so the arithmetic speed of this central processing unit must be adjusted to the highest arithmetic speed that to deal with system load, when the existing arithmetic speed of this central processing unit was once downgraded, then the arithmetic speed adjustment of this central processing unit must be returned this highest arithmetic speed, afterwards execution in step 110 again; In step 110, if when the existing arithmetic speed of this central processing unit is not downgraded or the arithmetic speed of this central processing unit has been adjusted back this during high arithmetic speed, then can in this second time interval, keep the arithmetic speed of this central processing unit, meaning can wait for whether the Prediction System load of carrying out the phase one behind this second time interval once more is about to the action that becomes big, yet the time interval in this wait also can be another the 6th time interval, wherein the 6th time interval can be greater than the 3rd time interval, meaning i.e. the 6th time interval can be not equal to this second time interval, and it can set up on their own according to design requirement.If when this tertiary system system load was not greater than the 3rd threshold value in the phase III, then the Prediction System load was not about to become big, just can downgrade the arithmetic speed of this central processing unit this moment.Need to judge earlier that whether the arithmetic speed of this central processing unit this moment is greater than this minimum arithmetic speed this moment, if the arithmetic speed of this central processing unit equals this minimum arithmetic speed at present, the arithmetic speed that then can keep this central processing unit is in this minimum arithmetic speed, and then saves the electrical source consumption of this central processing unit; If the arithmetic speed of this central processing unit is greater than this minimum arithmetic speed at present, then can reduce the arithmetic speed of this central processing unit at present, to save the electrical source consumption of this central processing unit.The arithmetic speed that can be this central processing unit as for the amplitude that reduces reduces (the speed adjustment of (the minimum arithmetic speed of the highest arithmetic speed-this central processing unit of this central processing unit)/this central processing unit at interval), that is to say and the arithmetic speed of this central processing unit can be divided into m grade by this highest arithmetic speed to this minimum arithmetic speed, and via above-mentioned estimate with deterministic process after, if the system load that meets three phases is during all less than individual other threshold value, the arithmetic speed that then can downgrade this central processing unit is to a lower grade, if again through above-mentioned flow process once estimate with the system load of judging and meeting three phases all less than individual other threshold value the time, then can be again the arithmetic speed of this central processing unit be downgraded a low grade again.
After executing above-mentioned flow process, can get back to step 100 and re-execute whole flow processs, by estimating at any time and judging the system load state, the arithmetic speed of this central processing unit be can in time adjust, and system stability operation and the equilibrium point of saving power consumption reached.
And above-mentioned flow process can not only be confined to estimating of three phases and judge the system load program; but also cutting estimating and determining program for multistage more or less stage; look closely design requirement and decide, so long as the category that the mode that is used as dynamically adjusting the arithmetic speed of this central processing unit according to system load all belongs to the present invention to be protected.
Method compared to the utilization rate of existing detection system load and processor, method of the present invention is to utilize the present system load of software detection, and utilize the result after the calculation dynamically to adjust the arithmetic speed of this central processing unit when the different system load, to reach the method for effective power management, and need not additionally set up nextport hardware component NextPort to measure the correlation parameter of this central processing unit, and the signal that need not read this central processing unit is to detect the running situation of this central processing unit, therefore just can not increase extra cost and take mechanism's configuration space, so the present invention provides a scheme of effectively saving the electrical source consumption of mobile phone.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (19)
1. method of adjusting the central processing unit arithmetic speed of an electronic installation, it includes the following step:
(a). with the start-up time of this central processing unit in a very first time interval and divided by this very first time interval to obtain one first system load; And
(b). determine the arithmetic speed of this central processing unit according to this first system load.
2. the method for claim 1, wherein step (b) comprises in addition:
(c). whether first system load of judging this very first time interval is greater than one first threshold value; And
(d). determine the arithmetic speed of this central processing unit according to the judged result of step (c).
3. method as claimed in claim 2, wherein, step (d) comprises in addition: (e). when this first system load during greater than this first threshold value and the existing arithmetic speed of this central processing unit when not downgraded, in one second time interval, keep the arithmetic speed of this central processing unit.
4. method as claimed in claim 3, wherein, this second time interval is greater than this very first time interval.
5. method as claimed in claim 2, wherein, step (d) comprises in addition:
(f). when this first system load during greater than this first threshold value and the existing arithmetic speed of this central processing unit when having been downgraded, adjust the highest arithmetic speed of arithmetic speed to of this central processing unit; And
(g). after execution in step (f), in one second time interval, keep the arithmetic speed of this central processing unit.
6. method as claimed in claim 5, wherein, this second time interval is greater than this very first time interval.
7. method as claimed in claim 2, wherein, step (d) comprises in addition:
(h). when this first system load during, judge that whether second system load in one the 3rd time interval that is later than this very first time interval is greater than one second threshold value less than this first threshold value; And
(i). determine the arithmetic speed of this central processing unit according to the judged result of step (h).
8. method as claimed in claim 7, wherein, the 3rd time interval is greater than this very first time interval.
9. method as claimed in claim 7, wherein, this second threshold value is to equal this first threshold value * (1+ (the existing arithmetic speed of the highest arithmetic speed-this central processing unit of this central processing unit)/(the minimum arithmetic speed of the highest arithmetic speed-this central processing unit of this central processing unit)).
10. method as claimed in claim 7, wherein, step (i) comprises in addition:
(j). when this second system load during greater than this second threshold value and the existing arithmetic speed of this central processing unit when not downgraded, in one the 4th time interval, keep the arithmetic speed of this central processing unit.
11. method as claimed in claim 10, wherein, the 4th time interval is greater than the 3rd time interval.
12. method as claimed in claim 7, wherein, step (i) comprises in addition:
(k). when this second system load during greater than this second threshold value and the existing arithmetic speed of this central processing unit when having been downgraded, adjust the highest arithmetic speed of arithmetic speed to of this central processing unit; And
(l). after execution in step (k), in one the 4th time interval, keep the arithmetic speed of this central processing unit.
13. method as claimed in claim 12, wherein, the 4th time interval is greater than the 3rd time interval.
14. method as claimed in claim 7, wherein, step (i) comprises in addition:
(m). when this second system load during, judge that whether tertiary system system load in one the 5th time interval that is later than the 3rd time interval is greater than one the 3rd threshold value less than this second threshold value; And
(n) determine the arithmetic speed of this central processing unit according to the judged result of step (m).
15. method as claimed in claim 14, wherein, the 3rd threshold value is to equal this first threshold value.
16. method as claimed in claim 14, wherein, step (n) comprises in addition:
(o). when this tertiary system system load during, control the highest arithmetic speed of arithmetic speed to of this central processing unit greater than the 3rd threshold value; And
(p) after execution in step (o), in one the 6th time interval, keep the arithmetic speed of this central processing unit.
17. method as claimed in claim 14, wherein, step (n) comprises in addition:
(q) when the load of this tertiary system system less than the arithmetic speed of the 3rd threshold value and this central processing unit during greater than a minimum arithmetic speed, the arithmetic speed of this central processing unit is reduced (the speed adjustment of (the minimum arithmetic speed of the highest arithmetic speed-this central processing unit of this central processing unit)/this central processing unit is at interval).
18. method as claimed in claim 14, wherein, step (n) comprises in addition:
(r) when the load of this tertiary system system equals a minimum arithmetic speed less than the arithmetic speed of the 3rd threshold value and this central processing unit, keep the arithmetic speed of this central processing unit.
19. the method for claim 1, wherein this electronic installation is to be a mobile phone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100690309A CN100449457C (en) | 2005-05-10 | 2005-05-10 | Method for regulating CPU arithmetic speed in electronic apparatus |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100690309A CN100449457C (en) | 2005-05-10 | 2005-05-10 | Method for regulating CPU arithmetic speed in electronic apparatus |
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| CN1862451A CN1862451A (en) | 2006-11-15 |
| CN100449457C true CN100449457C (en) | 2009-01-07 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129371A (en) * | 1994-10-05 | 1996-08-21 | 三菱电机株式社 | Variable speed system |
| US20010004909A1 (en) * | 1999-11-17 | 2001-06-28 | Pope Kenneth L. | Vapor flow and hydrocarbon concentration sensor for improved vapor recovery in fuel dispensers |
| US20030023890A1 (en) * | 2001-07-27 | 2003-01-30 | Samsung Electronics Co., Ltd. | Method for reducing current consumption in a mobile communication terminal |
| US20040039954A1 (en) * | 2002-08-22 | 2004-02-26 | Nvidia, Corp. | Method and apparatus for adaptive power consumption |
-
2005
- 2005-05-10 CN CNB2005100690309A patent/CN100449457C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129371A (en) * | 1994-10-05 | 1996-08-21 | 三菱电机株式社 | Variable speed system |
| US20010004909A1 (en) * | 1999-11-17 | 2001-06-28 | Pope Kenneth L. | Vapor flow and hydrocarbon concentration sensor for improved vapor recovery in fuel dispensers |
| US20030023890A1 (en) * | 2001-07-27 | 2003-01-30 | Samsung Electronics Co., Ltd. | Method for reducing current consumption in a mobile communication terminal |
| US20040039954A1 (en) * | 2002-08-22 | 2004-02-26 | Nvidia, Corp. | Method and apparatus for adaptive power consumption |
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| CN1862451A (en) | 2006-11-15 |
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