CN100447766C - Selectable block protection for non-volatile memory - Google Patents
Selectable block protection for non-volatile memory Download PDFInfo
- Publication number
- CN100447766C CN100447766C CNB2004800245681A CN200480024568A CN100447766C CN 100447766 C CN100447766 C CN 100447766C CN B2004800245681 A CNB2004800245681 A CN B2004800245681A CN 200480024568 A CN200480024568 A CN 200480024568A CN 100447766 C CN100447766 C CN 100447766C
- Authority
- CN
- China
- Prior art keywords
- sector
- pin
- protection
- protect
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
A semiconductor non-volatile memory device, having a chip configuration with a plurality of pins including a write protect pin, a serial in pin and an optional parallel data bus with input-output pins (I/O<7-0>), plus other pins, all electrically communicating with the memory array and particularly a sector protection register of variable size and location. The sector protection register defines which sectors or group of sub-sectors to protect and is controlled by the use of commands via the serial in pin or the optional input-output pins. The sector protection may be selectably controlled by either use of a signal to the write protect pin or use of commands via the serial in pin or the optional input-output pins to the command and control logic. A logic circuit instantly determines whether the write protect pin or the commands are controlling the sector protection.
Description
Technical field
The present invention relates to non-volatile memory device, relate in particular to electric erasable and programable nonvolatile memory device with write-protect ability.
Background technology
In some flash non-volatile memories of prior art, be that custom provides " write-protect " pin of being associated with memory chip package to prevent programming and erase operation such as some position of bootstrap block sector.Sector in flash memory device is the simple subregion of memory array itself.Flash memory device is made up of the memory cell array that is grouped into many row and columns.Each provisional capital comprises many storage unit of representing a plurality of bytes.The arrangement of most of flash arrays all can be grouped into a plurality of row each self-contained thousands of bytes (kilobyte) sector or piece subsequently.
It is very general that flash array is separated into some sectors, and in some flash memory device, the size of each sector also can change each other.For example the equipment of one 8 megabit is made up of the sector of the sector of single 32 kilobyte, the sector of 84 kilobyte, single 64 kilobyte and the sector of 7 128 kilobyte.In a specific system design, first sector of 32 kilobyte can be allocated for the storage guidance code in array, and the sector of 4 littler kilobyte can be divided and is used in configuration data and parameter storage.Some bigger sectors can be used for the main program code of storage system and the storage that is used in user data can be divided in remaining sector in the array.
In many system designs, some avoid unintentionally or the programming and the erase operation of malice all to wish protection certain in these sectors.In above-mentioned example, the sector of storage guidance code, structured data and main program code needs most protection.If, will cause system can't realize appropriate function subsequently because carelessness has been wiped any sector in these sectors or programmed with error message.It is just so important and be wiped free of under the situation with reprogramming not influence of basic operation to system at them to distribute to the sector of storage of subscriber data, all they extremely do not need protection.
The method that is used for the write-protect scheme of aforementioned definitions they dirigibility and function on all have limitation.A target of the present invention provides a kind of than the prior art Write-protection method that is used for non-volatile memory device of universal flexible more.
Summary of the invention
Realized above-mentioned target already in non-volatile memory device, this target is that the combination by the sector protection scheme that protection register in user-programmable sector is provided and controls simultaneously by software command with to the independent available write-protect pin of same memory device realizes.
The certain user wishes to use the hardware protection method via the write-protect pin by master processor or ASIC.These users may think that the hardware protection method is safer reliable, because programming or erase command that it has avoided storage device processes to be sent unintentionally by other equipment that are positioned on the same memory bus.Yet other user does not but wish or the extra of control hardware write-protect pin can not be provided for memory device.These users control the write-protect to memory device with regard to wishing the use software approach.
In the present invention, the user selects the sector (for example specifying a particular row to protect register as the sector) protected by certain programmed data in the defined range and wipes, programmes or read it with specific command sequence.Thereby the sector that these definition or mark are used to protect just can be enabled the protection of this sector and can avoid programming and erase operation subsequently by sending a specific command sequence.In addition, the mark that defines in the sector protection register sector that is used to protect can also remain on assigned state with this pin by assignment (assert) write-protect pin and is protected.The use of write-protect pin also will stop the use of the software command sequence of disable sector protection.In this way, the user can select a suitable sector to protect mode or can mix mode separately.
Preferably, the single additional row of entire memory array is protected register as the sector, wherein each byte of this sector protection register all is used for storing the sector locking information about storer specific sector number (or sub-sector).Because used an independent line storage unit, so can make shielded or not shielded sector number increase according to the density of memory device or minimizing.Because only need sector protection register to be programmed to be used to specify which sector protected, so only need to send individual command.Like this, just need single operation to specify the protection that is used for single sector or a plurality of sectors.A kind of sector of using protects the sector guard method of register to comprise following step: the sector that (1) definition will be protected; (2) wipe sector protection register; (3) this sector protection register of programming makes each byte all indicate corresponding protected sector, and promptly byte 0 is used for sector 0, and byte 1 is used for sector 1, or the like, byte N is used for sector N; And (4) choose any one or two kinds of Write-protection methods execution write-protects from software or hardware controlling method; wherein said software approach uses the specific command sequence of sending into command interpreter to start the sector protection; described hardware approach; with the signal assignment write-protect pin that starts the sector protection; wherein no matter when the sector protection starts; even write-protect is assignment not, the protection of described sector also keeps starting.
Description of drawings
Fig. 1 is the system schematic that has comprised master processor and had the memory device of memory array according to of the present invention, and wherein above-mentioned memory array has sector protection register.
Fig. 2 is the memory array planning that type shown in Fig. 1 is separated into each sector, and wherein first sector is divided into four sub-sectors.
Fig. 3 A shows the arrangement of the sector protection register that uses in memory array mode shown in Figure 2, and wherein each byte all comprises the sector locking information.
Fig. 3 B shows the example of the sector 0 protection value of the protection of sector shown in Fig. 3 A register.
Fig. 4 A show the sector protection register that is used to visit type shown in Fig. 3 A such as the command sequence of wiping, programming and reading.
Fig. 4 B shows the byte and the position level structure of order of the sector protection register of the type shown in Fig. 3 A that is used to programme.
Fig. 4 C shows the byte and the bit-level structure of the order of the sector protection register that is used to read type shown in Fig. 3 A.
Fig. 5 A shows the form of the value of enabling sector protection and disable sector guarded command of a sector protection register of having listed to be used for shown in Fig. 3 A.
Fig. 5 B shows the diagram of the write protect signal that uses in system shown in Figure 1.
Fig. 5 C shows the form of sector guard mode of the various situations of the write-protect pin that is used to be loaded with the write protect signal shown in Fig. 5 B, is used to send enable the sector guarded command and be used for forbidding and sends the sector guarded command.
Fig. 5 D shows the form of the status register that uses in the system shown in Figure 1.
Fig. 6 shows the synoptic diagram of realizing the circuit of form shown in Fig. 5 C.
Fig. 7 is the process flow diagram according to sector of the present invention guard method.
Embodiment
Referring to Fig. 1, Computer Memory Unit 100 has the nonvolatile memory array 104 that has sector protection register 104A.Sector protection register 104A is suitable for memory protection or locking information.Each byte of sector protection register all is used to the locking information of a sector or this sector of a series of sub-sector storage of memory array 104.
Master processor 146 is communicated by letter with memory array 104 via interface control 108, and this serial line interface has following pin: chip base pin selection 124 (CS#), system clock pin one 26 (SCK), serial data input pin 128 (SI), serial data output pin 130 (SO), write-protect pin one 32 (WP#), replacement pin one 34 (RESET#) and status-pin 136 (RDY/BSY#).Except passing through serial data input pin 128 and serial data output pin 130 is connected, master processor 146 also can use 8 I/O pin 138-145 (I/O) and memory device communication.If supplying data and this data of this equipment of input by interface control 108 is operational code or address, just handle these data subsequently by order and steering logic 102, perhaps (b) if this data are raw data, just with it by the I/O buffering with latch 122 and be sent to memory array 104.Cushion and latch the data output and the output of this data of 122 supply memory arrays 104 by I/O and control 108 by interface subsequently.In addition, these data can be sent to and have order and the steering logic 102 that has comprised the specific function that sector protection register 104A inside is read.Export via interface control 108 from the feedback on the functions of the equipments of order and steering logic 102, the commonplace logical one 18 of ready/busy and status register 120.Interface control 108, order and steering logic 102 and auxiliary circuit and pin comprise that also memory array organization all is known.For example can be referring to the Data Flash Application Note AN-4 on the www.atmel.com.
Utility command and steering logic 102 come the built-in function of opertaing device to be sent to the signal input of interface control 108 with response.Write-protect logical one 06 is the part of overall command and steering logic 102.A function of order and steering logic 102 execution be with addressing information pass to byte address latch 110 and sevtor address latch 114 and control them.Byte selection 112 and row selection 116 decodings are latched row and the row in address and the activation memory array 104.
Write-protect logical one 06 is responsible for the sector protection of this equipment of control.Write-protect logical one 06 decoding write-protect pin is the state of WP# input pin 132 and the order of processing " enabling the sector protects " and " disable sector protection ".Determine whether allow to memory array 104 programme or erase operation this be the function of write-protect logical one 06.
Write-protect (WP#) pin one 32 just can start the write-protect process of hardware controls when enabling.The commonplace output 136 of ready/busy has reflected the state of memory array 104 when programming or wipe sector protection register 104A.Subsequently these control function will be discussed in further detail.
Fig. 2 shows the inner structure of typical memory array 200 in more detail according to the present invention.Typical memory array 200 is examples of general memory array 104 among Fig. 1.Memory array 200 comprise scope from the sector 0 to the sector 8 sectors 202 to 216 of 7.Each sector in this example all has 512 pages or 512 storage unit of going altogether.First sector 202 is that sector 0 also is divided into four sub-sector 202a to 202d: sub-sector 0a, sub-sector 0b, sub-sector 0c and sub-sector 0d.Sub-sector 0a has 8 pages of storage unit, and sub-sector 0b also has 8 pages, and sub-sector 0c has 240 pages and sub-sector 0d has 256 pages.Notice that sub-sector does not need all to have identical size.Because used single memory cell rows to define shielded sector or sub-sector, so can protect the number of sector and sub-sector respectively according to the density (byte number in the delegation) of memory array 200 as sector protection register.For example, the every line storage unit in 8 megabit device can be represented 256 bytes.In the case, just there are 256 modules to be protected respectively or not protect in this 8 megabit device altogether, such as 4 sub-sectors and other sectors of 255 of sector 0.
Which does not have so that master processor can survey which sector is labeled protection can encoded packets to be contained in locking in the sector protection register or protection information.With reference to figure 3A, table 300A shows the representative content of sector protection register 104A among Fig. 1.Whether sector that the hexadecimal code indication is associated with each register byte or sub-sector are labeled is used for protection.Otherwise sexadecimal number FFH can represent then can be used to indicate a particular sector not protected to the protection sexadecimal number 00H of a particular sector.For example in Fig. 3 A, sector 1 and 7 is labeled and is used to protect the sector 2 to 6 by 2 to 6 expressions of sector protection register byte then not to be labeled protection.Other hexadecimal code can be indicated the protection mark of certain a little sector in the particular sector.
Fig. 3 B further shows the typical code of the sub-sector of independence that is used to protect same sector (such as sector 0).Use a byte (or 8) to specify the protection of 4 sub-sectors altogether, such as sub-sector 0a, 0b, 0c and the 0d of sector 0.In this byte, a bit is corresponding to (two) just different with one sub-sector, and wherein a pair of " 1 " indication this sub-sector of protection a pair of " 0 " is then indicated and do not protected this sub-sector.The byte 0 of sector protection register is used for sector 0, and from left to right arranges sub-sector 0a, 0b, 0c and 0d shown in form 300B.Therefore, just be assigned to sub-sector 0a to the highest two and be assigned to sub-sector 0d minimum two.The protective capability scope of sector 0 from 0 sub-sector to all sub-sectors.For example when not having sub-sector protected, the binary value of byte 0 is exactly 00000000 in the sector protection register, just equals sexadecimal number 00H, and this is shown in the first row 302B of table 300B.In the second row 304B, protected sector 0d, then its binary value is exactly 00000011, and the hexadecimal value that equates with it is 03H.Jump to fifth line 310B forward, protected sub-sector 0b therein, then binary value is exactly 00110000, and its hexadecimal value is 30H just.In addition, can protect any two sub-sectors simultaneously.For example, if protect sub-sector 0a, 0b, then as the row 8316B shown in subsequently its corresponding data values binary form be shown 11110000 or hexadecimal representation be F0H.Be expert among the 7314B, protected sub-sector 0a, 0c, 0d, then its binary value is 11001111, and its hexadecimal value equals AFH.When shown in last column 322B, data value being appointed as 11111111 or just protect complete sector 0 during FFH.
Referring to Fig. 4 A, show the typical command code that is used for sector protection register 104A.Command sequence comprises the instruction of wiping, programming or reading sector protection register 104A.Each command instruction all has particular code makes master processor 146 and steering logic 102 to confirm and decode it.In table 400A, listed exemplary codes.Therefore be used for wiping sequence, hexadecimal command code can be the 3DH 2AH 7FH CFH shown in the first row 402A of form 400A.For a programmed sequence, corresponding code can be the 3DH 2AH 7FH FCH shown in the second row 404A.Read sequence for one, code can be the 32H 00H 00H 00H shown in the third line 406A.Follow after each command code is the data of the corresponding command.Clearly be not need data in wiping sequence.The data (Fig. 4 B) of following programming code are to specify register (Fig. 3) information is protected in the sector of which sector or the protection of sub-sector mark.Follow the data (Fig. 4 C) that read code and be the content of the sector protection register (Fig. 3) that has reflected the sector that is labeled protection or sub-sector.Read with the program command request msg and write sector protection register or reading of data (104A among Fig. 1) therefrom.
For the operation of these command sequences is shown, again with reference to figure 1.Usually the first step is to wipe it before programming sector protection register 104A.In order to wipe sector protection register 104A, at first essential assignment chip is selected (CS#) pin one 24.Must import (SI) pin one 28 or 8 two-way I/O (I/O then via serial
7-0) 4 suitable byte command sequences of pin one 38-145 clock input.After clock has been imported last byte of command sequence, must remove chip and select the assignment of (CS#) pin one 24 to start the erase cycles of inner self-timing.This equipment is had much to do during ready/busy state pin one 36 indication erase cycles.Also can determine ready/busy state by read status register 120.If this equipment just cuts off the power supply before described erase cycles is finished, just can't guarantee the content of sector protection register 104A subsequently.During erase cycles, can forbid replacement pin one 34 to prevent incomplete wiping to sector protection register 104A.Enabling or the disable sector protection time all can be wiped sector protection register 104A.
Another characteristic of the present invention is to use in the sector protection register 104A erase status of each to indicate the mark of a sector to be used for protection.As long as therefore wiped sector protection register 104A, then all sectors all are labeled and are used for protection.This just make stop the accident programming of the pages in the main memory array 104 of having enabled the sector protection or the protection scheme wiped more effective.If after wiping sector protection register 104A with before this register of programming, immediately the program/erase command of mistake is sent to this equipment for some reason; then, just can not handle this wrong program/erase command because all sectors are all protected.
For the sector protection register 104A that programmes, at first just need the assignment chip to select (CS#) pin one 24.In case assignment chip selection (CS#) pin one 24, just must be via SI pin one 28 or I/O
7-0The 4 byte command sequences that the input of pin one 38-145 clock is suitable.After clock has been imported last byte of command sequence, just must the clock input be used for the data that register 104A content is protected in this sector.As shown in Figure 3A, first byte corresponding to sector 0, the second byte corresponding to sector 1 or the like.If for example have 8 sectors in the equipment, subsequently just must clock import the data of 8 bytes.If there is not the data byte of clock input suitable quantity, just can not guarantee subsequently to clock input word not save the guard mode of corresponding sector.For example, if only clock has been imported preceding 6 bytes rather than 8 whole bytes, just can't guarantee the guard mode of latter two sector.When clock has been imported last data byte, then must remove chip and select the assignment of (CS#) pin one 24 to start the program cycles of inner self-timing.
This equipment is had much to do during ready/busy state pin one 36 indication program cycles.Also can determine ready/busy state by read status register 120.At this equipment during the program cycles just is the content that can't guarantee sector protection register 104A under the situation of outage.During program cycles, can forbid replacement pin one 34 to prevent incomplete programming to sector protection register 104A.Be similar to the processing of wiping discussed above, enable or disable sector when protection also Reprogrammable sector protection register 104A all.Enabling under the situation of sector protection reprogramming to sector protection register 104A allows the temporary transient forbidding of user that the sector protection of one independent sector be need not complete disable sector protection.
Preferably read sector protection register 104A immediately to check this programming or erase operation whether successful in programming or after wiping sector protection register 104A.Also can read sector protection register 104A at other times.Fetch program comprises the steps: at first essential assignment chip selection (CS#) pin one 24.Subsequently via SI pin one 28 or I/O
7-0The 4 byte command sequences that the input of pin one 38-145 clock is suitable.After clock has been imported last byte of command sequence, just may be according to the difference of equipment at SO pin one 30 or I/O
7-0Pin one 38-145 goes up data clock input before some " haveing nothing to do " byte that clock output is used for sector protection register 104A.In a preferred embodiment, 8 sectors in memory array 104, have been used, so clock is exported the data of 8 bytes.First byte corresponding to 0, the second byte in sector corresponding to 1, the three byte in sector corresponding to sector 2 or the like.
A notable feature of the present invention is can also can be realized by the method for hardware controls by software by the sector protection that sector protection register 104A is set up.Referring to Fig. 5 A to 5D, the method for described software control has used an order of enabling the sector protection to enable the sector protection.Table 500A in Fig. 5 A has listed the hexadecimal code sequence that is used to enable sector protection and disable sector guarded command.The code length of enabling the sector guarded command is 4 bytes and is designated as 3DH 2AH 7FH A9H.The code of disable sector guarded command then is designated as 3DH 2AH 7FH 9AH.Enable with the order of disable sector protection only in the end different on the byte.Be to use software control method to enable the process of sector protection subsequently.At first essential assignment chip is selected (CS#) pin one 24.In case assignment chip selection (CS#) pin one 24, just as mentioned above via SI pin one 28 or I/O
7-0The 4 byte command sequences that the input of pin one 38-145 clock is suitable.After clock has been imported last byte of this command sequence, then must remove chip and select just to enable the sector protection after the assignment of (CS#) pin one 24.Similarly, in assignment disable sector protection after chip selection (CS#) pin one 24, and via SI pin one 28 or I/O
7-0The input of pin one 38-145 clock is used for the 4 suitable byte sequences of disable sector guarded command.After clock has been imported last byte of this command sequence, the then essential assignment just disable sector protection afterwards of removing chip selection (CS#) pin one 24.
Except the guard method of software control, also can carry out the sector protection of hardware controls in addition by assignment write-protect (WP#) pin one 32.As long as assignment write-protect (WP#) pin one 32, just can't wipe or any sector that reprogramming is protected by sector protection register 104A mark.When assignment write-protect (WP#) pin one 32, will ignore the order of disable sector protection in addition.It can be crucial from the parasitic noise that assignment becomes non-assignment causing this write-protect (WP#) pin one 32 unintentionally that masked-write protection (WP#) pin one 32 is avoided.In this equipment, combine noise filter make that the sector that is being labeled becomes must be before protected or not protected to this write-protect (WP#) pin one 32 assignment or more than the non-assignment 100ns.
When assignment write-protect (WP#) pin one 32; with some sector in the protected storage array; and when removing assignment write-protect (WP#) pin one 32, do not enable the sector guarded command and just will no longer protect described memory array 104 as long as when assignment write-protect (WP#) pin one 32, send.
If sent during assignment write-protect (WP#) pin one 32 and enabled the sector guarded command, the assignment of then simply removing write-protect (WP#) pin one 32 can't the disable sector protection.In the case, just need during the assignment of interior releasing write-protect (WP#) pin one 32, send the disable sector guarded command and come the disable sector protection.
Only write-protect (WP#) pin one 32 just covers the sector guard method of sub-software control under the situation of protection sector.Three different stages that illustrate write-protect (WP#) pin one 32 in Fig. 5 B.Incident in these three different phases is presented among Fig. 5 C.In the phase one (time cycle), at write-protect (WP#) pin one 32 for high or separate assignment and previous for to send under the situation of enabling the sector guarded command, then as the stage (time cycle) so do not exist shown in the row 1 of 1502C to protect and protect yet with regard to disable sector.Sending disable sector guarded command and write-protect (WP#) pin one 32 for high or separate under the situation of assignment, then need not to consider before whether to have sent and enable the sector guarded command and just can not protect the sector.This is being the forbidding in the sector guard mode row shown in row 2 of stage (time cycle) 1502C.Enable sector guarded command and write-protect (WP#) pin one 32 still for separating under assignment or the high situation having sent, then need not to consider before whether to have sent the disable sector guarded command and just can enable the sector and protect.This has shown in the row 3 of stage (time cycle) 1502C.In time cycle 2504C, when assignment write-protect (WP#) pin one 32, then need not to consider whether to have sent and enable sector protection or disable sector guarded command and just can enable the sector and protect.In time cycle 3506C, when write-protect (WP#) pin one 32 is separated assignment or when high once more, enable the sector guarded command and just can keep enabling the sector and protect if during time cycle 1502C or time cycle 2504C, sent.This has shown in the row 1 of time cycle 3506C.Separated assignment once more or sent when high when write-protect (WP#) pin one 32 and enable the sector guarded command and also can as shown in the row 3 of time cycle 3506C, enable the sector protection certainly.On the other hand, but during time cycle 3506C, sent just disable sector protection of disable sector guarded command.This has shown in the row 2 of time cycle 3506C.
Can be by status register 500D monitoring sector guard mode.Referring to Fig. 5 D, the status register 500D that has 8 bit data is applicable to the state of indication protection.Bit 1 in status register 500D provides as above discussion and has shown enabling or the information of disable sector protection shown in last row of 500C.The logical one indication has been enabled sector protection logical zero and has then been indicated disable sector protection.Bit 7 these equipment of indication are ready or are busy with carrying out some operation.Bit 2 to 5 these device density code of indication.
The hardware that figure 6 illustrates the write-protect logical one of discussing 06 in Fig. 5 B, Fig. 5 C and Fig. 5 D is realized.Write-protect (WP#) pin one 32 is connected to OR door 610, makes can not consider to enable sector guarded command logic 602 and disable sector guarded command logic 604 and enable sector protection logic 620 when assignment write-protect (WP#) pin one 32.This has just realized the row 2 of time cycle 2504C among Fig. 5 C.Use single set-reset (S-R) to latch 608 and control the result who enables sector protection and disable sector guarded command.This S-R is set under the situation of enabling the sector guarded command latchs 608 sending.When this S-R being set latching 608, so just will activate sector protection logic 620 because the result of OR door 610 will be a logical one.If before sending the order of enabling the sector protection shown in time cycle 3506C, then the S-R that combines with AND door 606 latchs 608 and just can avoid the assignment disable sector of separating of write-protect (WP#) pin one 32 is protected logic 620.When write-protect (WP#) pin one 32 and disable sector guarded command logic 604 when all being high, just can rely on AND door 606 replacement S-R to latch 608.The result be sector protection logic 620 with step-down to indicate this protection disabled.This is to be avoided protecting disabled safety practice when assignment is reset (RESET#) pin one 34 unintentionally by noise or some other environmental factor.
Referring to Fig. 7 and Fig. 8, show the guard method of a kind of sector by process flow diagram.The sector protection register 104A that utilizes the single additional row of memory array has been used in this sector guard method.
This sector guard method can be divided into two parts.First relates to the programming of sector protection register 104A.Second portion is then handled enabling and forbidding of sector protection.First is from defining the sector (step 704) (702) of the memory array that will protect.As previously mentioned, sector protection register 104A has a plurality of bytes.Each byte all is used to store the locking information of a designated sector.Byte 0 is used for sector 0; Byte 1 is used for sector 1 or the like.The locking information that also byte 0 segmentation can be used for as previously mentioned, sub-sector usually.Each sub-sector all has the ability that is locked separately.
Can wipe previously stored any sector protection information before programming, to remove all undesirable residual datas.
In step 708, sector protection information is programmed into the respective byte of sector protection register 104A.Data and imperative structures in Fig. 2, Fig. 3, Fig. 4 and Fig. 5, have been described in detail.
At step 710 place, read from the sector and protected the locking information of register 104A with verification of programming.This step is optional.
Need not the wiping and reprogramming sector protection register 104A of enabling each time or all carrying out during the disable sector protection as shown in Figure 7.Only be to change in system just to need reprogramming sector protection register 104A when being labeled the sector that is used to protect.
The second portion of sector guard method relates to use software or the hardware controls technology is enabled or disable sector protection (step 802).
If select to enable sector protection (step 804), system just must determine that subsequently being to use hardware still is method for protecting software (step 806).Use hardware protection method (step 808), this process only needs assignment write-protect (WP#) pin one 32 (steps 810).Use method for protecting software (step 812), at first the assignment chip is selected (CS#) pin one 24 (steps 814).After the assignment chip is selected (CS#) pin one 24, just must be via SI pin one 28 or I/O
7-0Pin one 38-145 will enable the sector guarded command and import this equipment (step 816).Subsequently in order to enable the just essential assignment of chip being selected (CS#) pin one 24 of removing of sector protection.(step 818)
If disable sector protection (step 822), system just must determine that being to use hardware still is software approach (step 824) subsequently.If use hardware approach (step 826), system will at first remove the assignment (step 828) of write-protect (WP#) pin one 32 subsequently.If the software control method that is used to enable with the disable sector protection is never used in system design, then only remove write-protect (WP#) but the assignment of pin one 32 disable sector just.If yet system uses the combination of hardware and software control method to be used to enable and the disable sector protection, system just should determine before whether sent the order (step 830) of enabling the sector protection subsequently.This can check that whether also enabling this sector protects and finish by read status register 120.If (step 834) still enabled in the sector protection, then system just can advance to the software approach (step 836) of disable sector protection subsequently.
In order to use software control method to come disable sector protection (step 836), (CS#) pin one 24 (steps 838) are selected by system at first assignment chip.After the assignment chip was selected (CS#) pin one 24, system just must be via SI pin one 28 or I/O
7-0The order (step 840) of pin one 38-145 input disable sector protection.Subsequently in order the disable sector protection just to remove the assignment (step 842) of chip being selected (CS#) pin one 24.
Claims (11)
1. semiconductor non-volatile memory device, this equipment comprises:
The memory array that in the middle of a plurality of sectors, has sector protection register;
Via the interface that a plurality of pins are communicated with described memory array, described a plurality of pins comprise write-protect (WP#) pin and serial input (SI) pin and have a plurality of input-output (I/O
7-0) in the parallel data bus line of pin any one or a plurality of, wherein said write-protect (WP#) pin is electrically connected to the device that uses signal controlling sector protection;
Command interpretation device, this device use the order of sending into described command interpretation device to control sector protection and described sector protection register; And
Be connected to the logical unit of described command interpretation device and described write-protect (WP#) pin, this device is used for determining at once that described write-protect (WP#) pin still is that described command interpretation device is being controlled the protection of described sector.
2. memory device as claimed in claim 1 is characterized in that, described order is imported (SI) pin via described serial and sent into described command interpretation device.
3. memory device as claimed in claim 1 is characterized in that, described order is via a plurality of input-output (I/O of described parallel data bus line
7-0) pin sends into described command interpretation device.
4. memory device as claimed in claim 1 is characterized in that, described logical unit determines that any write-protect data that provided by other pins are provided the write protect signal on described write-protect (WP#) pin.
5. memory device as claimed in claim 1 is characterized in that, also comprises being connected to the status register that order and steering logic also are connected to described interface.
6. memory device as claimed in claim 1 is characterized in that, a plurality of data bytes of described sector protection register-stored, and wherein the individual data byte is corresponding to a sector or one group of sub-sector of described memory array.
7. memory device as claimed in claim 6 is characterized in that, the size of described sector protection register is variable.
8. memory device as claimed in claim 1 is characterized in that, described sector protection register comprises the described memory array of delegation.
9. memory device as claimed in claim 8 is characterized in that, the position of described sector protection register is variable in described memory array.
10. memory device as claimed in claim 1 is characterized in that described memory array comprises the flash memory transistor.
11. one kind is used to have the method that the sector protects the sector of the nonvolatile memory array of register to protect, described method comprises:
The sector that definition will be protected in described array;
Wipe described sector protection register;
With the sectors of data byte that will protect of the definition described sector protection register of programming, be stored in the locking information that a data byte in the sector protection register is used to define a designated sector, and each the sub-sector in the sector can be locked separately; And
From software approach and hardware approach are any one or two kinds of, choose Write-protection method; wherein said software approach uses the specific command sequence of sending into command interpreter to start the sector protection; described hardware approach; with the signal assignment write-protect pin that starts the sector protection; wherein no matter when the sector protection starts; even write-protect is assignment not, the protection of described sector also keeps starting.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US50618303P | 2003-09-26 | 2003-09-26 | |
| US60/506,183 | 2003-09-26 | ||
| US10/835,410 | 2004-04-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1842775A CN1842775A (en) | 2006-10-04 |
| CN100447766C true CN100447766C (en) | 2008-12-31 |
Family
ID=37031161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800245681A Expired - Fee Related CN100447766C (en) | 2003-09-26 | 2004-09-21 | Selectable block protection for non-volatile memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100447766C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101625889B (en) * | 2009-07-29 | 2013-09-18 | 深圳国微技术有限公司 | Memory with redefined pins and protection method thereof |
| CN102385556B (en) * | 2011-11-08 | 2014-11-26 | 聚辰半导体(上海)有限公司 | Serial nonvolatile memory and method for cancelling write-protect of memory |
| CN108037725B (en) * | 2017-12-08 | 2019-09-03 | 中冶南方工程技术有限公司 | A kind of method and apparatus for reading and writing plc data |
| KR20200021815A (en) * | 2018-08-21 | 2020-03-02 | 에스케이하이닉스 주식회사 | Memory controller, memory system having the memory controller and operating method thereof |
| CN112967407B (en) * | 2021-02-25 | 2023-08-11 | 北京贝能达信息技术股份有限公司 | Register for automatic ticket vending and checking system, system with same and data processing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1176427A (en) * | 1997-07-24 | 1998-03-18 | 谢用富 | Selective keyboard write-in protector |
| US5930826A (en) * | 1997-04-07 | 1999-07-27 | Aplus Integrated Circuits, Inc. | Flash memory protection attribute status bits held in a flash memory array |
| US6032237A (en) * | 1994-08-03 | 2000-02-29 | Hitachi Ltd. | Non-volatile memory, memory card and information processing apparatus using the same and method for software write protect control of non-volatile memory |
-
2004
- 2004-09-21 CN CNB2004800245681A patent/CN100447766C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6032237A (en) * | 1994-08-03 | 2000-02-29 | Hitachi Ltd. | Non-volatile memory, memory card and information processing apparatus using the same and method for software write protect control of non-volatile memory |
| US5930826A (en) * | 1997-04-07 | 1999-07-27 | Aplus Integrated Circuits, Inc. | Flash memory protection attribute status bits held in a flash memory array |
| CN1176427A (en) * | 1997-07-24 | 1998-03-18 | 谢用富 | Selective keyboard write-in protector |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1842775A (en) | 2006-10-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7275128B2 (en) | Selectable block protection for non-volatile memory | |
| CN107871521B (en) | Semiconductor memory device, flash memory and continuous read method thereof | |
| CN1129916C (en) | Programmable access protection in a flash memory device | |
| CN102317928B (en) | Modifying commands | |
| KR101938210B1 (en) | Operating method of memory systme including nand flash memory, variable resistance memory and controller | |
| CN100517228C (en) | Method and apparatus for executing the boot code of embedded systems | |
| US7502256B2 (en) | Systems and methods for reducing unauthorized data recovery from solid-state storage devices | |
| CN101369453B (en) | Flash memory device and method of controlling flash memory device | |
| CN101957798B (en) | There is the device of memory integrated circuit | |
| TWI534809B (en) | A non-volatile memory device for which control information may be set from an external source | |
| CN108962314B (en) | Memory with dynamic permission bit writing logic and method | |
| KR20140111323A (en) | Device selection schemes in multi chip package nand flash memory system | |
| CN110021318B (en) | Semiconductor memory device with a plurality of memory cells | |
| CN106373610A (en) | Semiconductor memory device and operating method thereof | |
| CN100447766C (en) | Selectable block protection for non-volatile memory | |
| CN109243508A (en) | Semiconductor memory system and its operating method | |
| EP3057100B1 (en) | Memory device and operating method of same | |
| CN103946798A (en) | Bit stream aliasing in memory system with probabilistic decoding | |
| JP4896842B2 (en) | Portable electronic device | |
| US7310277B2 (en) | Non-volatile semiconductor storage device with specific command enable/disable control signal | |
| KR100953062B1 (en) | Method of inputting address in a non volatile memory device and method of operating the same | |
| JP2001319484A (en) | Non-volatile semiconductor memory | |
| CN104733042A (en) | Semiconductor device | |
| US6442058B2 (en) | Control circuit and semiconductor device including same | |
| US10515031B2 (en) | Memory device and data processing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081231 Termination date: 20130921 |