CN100442851C - Reference address computing device and method for motion compensation of image processing - Google Patents
Reference address computing device and method for motion compensation of image processing Download PDFInfo
- Publication number
- CN100442851C CN100442851C CNB200410086803XA CN200410086803A CN100442851C CN 100442851 C CN100442851 C CN 100442851C CN B200410086803X A CNB200410086803X A CN B200410086803XA CN 200410086803 A CN200410086803 A CN 200410086803A CN 100442851 C CN100442851 C CN 100442851C
- Authority
- CN
- China
- Prior art keywords
- motion vector
- view data
- positions
- shift
- motion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The present invention discloses a calculating device of the reference address of the motion compensation of image processing, which comprises a shifter, a motion-vector correcting chart, a block shift address list and an adder, wherein the shifter is used for logically shifting the motion vector of image data to three bits towards right; the motion-vector correcting chart provides the difference correction values of the motion vector of image data logically shifted to three bits towards right and a video verifying prototype; the block shift address list is connected with the motion-vector correcting chart for providing the shift address of calculated image data corresponding to an image origin; the adder is connected to the shifter and the block shift address list for adding the result of the motion vector of image data logically shifted to three bits towards right and the shifting address of a current decoding block to obtain the reference address of the motion compensation of the image data. The present invention can simplify circuits and calculate correct results.
Description
Technical field
The present invention relates to a kind of reference address device and method of motion compensation of image processing, particularly relate to a kind of reference address computing device and method that is used in specification four (MPEG4) of moving image expert group and DivX (this DivX is a kind of image encoding specification that is cooperated MP3 or Windows Media Audio V2 audio be combined into by the MPEG-4V3 picture format of Microsoft) motion compensation.
Background technology
The decoder of specification four (MPEG4) of moving image expert group and DivX is according to the image in previous transmission and the decoding, with the macro zone block decoding of each compression in specification four (MPEG4) of moving image expert group and the DivX coded bit stream.For image at the volley effectively is compressed in the macro zone block, each macro zone block is all relevant with before image macro zone block, and macro zone block is called motion vector with displacement between the image macro zone block that is associated.Therefore when decoding, how motion vector can be calculated quickly and accurately, the efficient of whole decoding can be influenced.
When the motion vector (Motion vector--MV) of the chroma block (Chrominance block) that calculates moving image expert specification four (MPEG4) of group and DivX, its vector value goes to calculate according to luma blocks (Luminance block), in the Immediate Mode (non_inter_laced_predictation Direct mode) of the noninterlaced of moving image expert group specification four (MPEG4), its motion vector (MV) is that the motion vector by the macro zone block of a last image same position is calculated; And in four motion vector pattern (Inter4v mode) of DivX, promptly four motion vectors (MV) are contained in bit stream (Bit-stream) the inside of a macro zone block (Macro block) the inside.But by specification (spec), by video verification prototype (Verification Model--VM) that DivX provided when calculating four motion vector pattern (Inter4v mode), used algorithm, and the video verification prototype of moving image expert group (MPEG4) is when calculating the Immediate Mode (non_inter_laced_predictationDirect mode) of noninterlaced, used algorithm, its computing circuit is quite complicated, essential will be the circuit optimization.
As shown in Figure 1, circuit diagram for the picture decoder of existing DivX, include a controller 1, a dynamic access internal memory 2, bit stream decoder 3, one anti-phase discrete cosine decoder 4, a motion compensator 5, a motion vector decoder 6 and picture buffer 7, this circuit is in order to the view data of decoding DivX.Wherein motion vector decoder 6 includes the reference address counting circuit 8 of a motion compensation, in order to the reference address of compute motion compensated.
As shown in Figure 2, be the video verification prototype (VM) of existing motion vector calculation circuit in order to calculating DivX, at first need an absolute value change-over circuit 11, table look-up 12 for one, this is tabled look-up and 12 provides remainder values, a shift unit 13 is in order to multiply by 2 again divided by 16, next the remainder values and motion vector (MV) value own that need an adder 14 to go addition to table look-up out multiply by 2 result again divided by 16, and then according to the sign before calculating, do the action of reversion again, 11 li of absolute value change-over circuits, must determine earlier that its motion vector value is positive or negative, if on the occasion of words, need not change, if but be negative value, then need to do 2 complement arithmetics (2 ' s complement transform), therefore need one 2 complement arithmetic circuit 15, its expression formula is A=~ A+1, A represents a certain numerical value in the following formula, this 2 complement arithmetic circuit 15 needs an adder, intermediate demand is two numerical value additions then, so need an adder again, last result still needs a circuit that conversion is positive and negative, so need an adder again, with the video verification prototype (VM) of DivX, the motion vector (MV) that calculates chroma block (Chrominance block) this moment just needs three adders and some extra circuit, and its circuit is quite complicated.
It seems from the video verification prototype (VM) of specification four (MPEG4) of moving image expert group, then need two inverters and three adders, its circuit is also quite complicated.Fig. 3 is the circuit diagram of the reference address of existing compute motion compensated then, comprises a motion vector calculation circuit 21, a block displacement address table 22 and an adder 23.Therefore, if the hardware circuit of the calculation of motion vectors (MV) of above-mentioned two specifications (spec) is realized out, what its circuit was quite complicated and the institute's transistor size that uses certainty is suitable is many.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of reference address computing device and method of motion compensation of image processing, and the circuit of reference address of motion compensation that will calculate the view data of specification four (MPEG4) of moving image expert group and DivX is simplified more and calculated correct result.
To achieve these goals, the invention provides a kind of reference address computing device of motion compensation of image processing, its characteristics are, comprising: a shift unit, and it is with three positions of motion vector logical shift to the right of view data; One motion vector correction is tabled look-up, and this motion vector correction is tabled look-up provides the difference correction value of three positions of the motion vector of view data logical shift to the right and video verification prototype; One block displacement address table is connected in this motion vector correction and tables look-up, the displacement address with respect to image origin of the view data of calculating in order to provide; And an adder, be connected in this shift unit and this block displacement address table, in order to result and the displacement address addition of decoding block at present, obtain the reference address of the motion compensation of view data with three positions of motion vector logical shift to the right of view data.
The reference address computing device of the motion compensation of above-mentioned image processing, its characteristics are that wherein this shift unit comprises three bit shift devices.
The reference address computing device of the motion compensation of above-mentioned image processing, its characteristics be, wherein the zero-bit of this block displacement address table corrected value of being tabled look-up by motion vector correction is set.
The reference address computing device of the motion compensation of above-mentioned image processing, its characteristics are, wherein this motion vector correction three of zero-bits to the of tabling look-up with the motion vector of view data are unit, per unit is represented the position 16 times, per 16 positions are a unit, wherein third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, repeat.
The present invention also provides a kind of motion vector calculation device of image processing, and its characteristics are, comprising: a shift unit, with three positions of motion vector logical shift to the right of view data; One motion vector correction is tabled look-up, and this motion vector correction is tabled look-up provides the difference correction value of three positions of the motion vector of view data logical shift to the right and video verification prototype; And an adder, be connected in this shift unit and this motion vector correction and table look-up, in order to addition that the result of three positions of motion vector logical shift to the right of view data and motion vector correction are tabled look-up, obtain the motion vector of view data.
The motion vector calculation device of above-mentioned image processing, its characteristics are that wherein this shift unit comprises three bit shift devices.
The motion vector calculation device of above-mentioned image processing, its characteristics are, wherein this motion vector correction three of zero-bits to the of tabling look-up with the motion vector of view data are unit, per unit is represented the position 16 times, per 16 positions are a unit, wherein third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, repeat.
The present invention also provides a kind of reference address computational methods of motion compensation of image processing, and its characteristics are, comprise the steps: three positions of motion vector of logical shift view data to the right; Set up motion vector correction and table look-up, this motion vector correction is tabled look-up and is set up by the difference of three positions of motion vector logical shift to the right of video verification prototype and view data; Set up block displacement address table, the block displacement address table of this view data is known, just determines when image compression; Set the zero-bit of block displacement address table, the zero-bit of the block displacement address table of this view data is by the motion vector correction decision of tabling look-up; With the result of three positions of motion vector logical shift to the right of view data and the displacement address addition of block at present, obtain the reference address of motion compensation.
The reference address computational methods of the motion compensation of above-mentioned image processing, its characteristics are, wherein set up the step that motion vector correction is tabled look-up, also include: the value of the video verification prototype (VM) of computed image data is meant the value of coming the video verification prototype (VM) of computed image data according to the definition of view data; Three positions of the motion vector of computed image data logical shift to the right; And the value of two more above-mentioned formulas, available result is, three of zero-bits to the with the motion vector of view data are unit, per unit is represented the position 16 times, per 16 positions are a unit, wherein third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, repeat.
Effect of the present invention is to simplify circuit and calculates correct result.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the circuit diagram of picture decoder of the DivX of prior art;
Fig. 2 is the circuit diagram of prior art in order to the motion vector of calculating DivX;
Fig. 3 is the circuit diagram of the reference address of prior art motion compensation;
Fig. 4 is the circuit diagram of the reference address of compute motion compensated of the present invention;
The comparison diagram of three positions of motion vector logical shift to the right that Fig. 5 tables look-up for motion vector correction according to the present invention and the difference value of video verification prototype;
Fig. 6 is the circuit diagram of calculation of motion vectors of the present invention; And
Fig. 7 is the flow chart of the method for the reference position of compute motion compensated of the present invention.
Wherein, Reference numeral:
The 1-controller, 2-dynamic access internal memory
3-bit stream decoder, the anti-phase discrete cosine decoder of 4-
The 5-motion compensator, 6-motion vector decoder
The 7-picture buffer, the reference address counting circuit of 8-motion compensation
11-absolute value change-over circuit, 12-tables look-up
The 13-shift unit, the 14-adder
15-2 complement arithmetic circuit, 21-motion vector calculation circuit
22-block displacement address table, the 23-adder
31, the 51-motion vector correction is tabled look-up
32,52-shift unit
33-block displacement address table, 34, the 53-adder
Embodiment
Please refer to shown in Figure 4ly, be the reference address computing device of the motion compensation of image processing of the present invention.The motion vector calculation device of this image processing comprises a shift unit 32, this shift unit 32 includes three bit shift devices, they can be with three positions of motion vector logical shift to the right of view data, the present invention comprises that also a motion vector correction tables look-up 31, this motion vector correction is tabled look-up and 31 is provided three positions of motion vector logical shift to the right of view data and the difference correction value of video verification prototype, and table look-up 31 value of motion vector correction is one to calculate good value in advance.This motion vector correction 31 three of zero-bits to the with the view data motion vector of tabling look-up are unit, per unit is represented the position 16 times, per 16 positions are a unit, wherein third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, repeat, though the motion vector of view data be on the occasion of or negative value, the phenomenon that it repeats is all identical.The motion vector calculation device of this image processing also includes a block displacement address table 33, block displacement address table 33 is connected in motion vector correction and tables look-up after 31, the displacement address of the view data of calculating in order to provide, this displacement address are meant the view data block that the calculated displacement address with respect to image origin.Wherein, the zero-bit of block displacement address table 33 is to be set by table look-up 31 corrected value of motion vector correction, and it is unaffected to be because the block displacement address all is eight multiple, and its zero-bit, first and second all are zero.Use an adder 34 at last again, adder 34 is connected in shift unit 32 and block displacement address table 33, it is used for the result of three positions of motion vector logical shift to the right of view data and the displacement address addition of view data, and obtains the reference address of the motion compensation of view data.
Please refer to shown in Figure 5, comparison diagram for the difference value of three positions of motion vector logical shift to the right of view data and video verification prototype, be to utilize program that the result of three positions of motion vector logical shift to the right of video verification prototype and view data is calculated, wherein, the 4th hurdle among the figure is the value of three positions of motion vector logical shift to the right of view data, third column among the figure is the value of video verification prototype, and second hurdle among the figure is time position, and first hurdle among the figure is a comparative result.Result from figure can learn third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, three of zero-bits to the with the motion vector of view data are unit, per unit is represented the position 16 times, per 16 positions are a unit, repeat, no matter and motion vector be on the occasion of or negative value, the phenomenon that it repeats is all identical.
Please refer to shown in Figure 6ly, be the motion vector calculation device of image processing of the present invention.The motion vector calculation device of this image processing includes a shift unit 52, this shift unit 52 includes three bit shift devices, can be with three positions of motion vector logical shift to the right of view data, and one motion vector correction table look-up 51, this motion vector correction is tabled look-up and 51 is provided three positions of motion vector logical shift to the right of view data and the difference correction value of video verification prototype, and table look-up 51 value of motion vector correction is a value that has pre-defined.And motion vector correction 51 three of the zero-bits to the with the motion vector of view data of tabling look-up are unit, per unit is represented the position 16 times, per 16 positions are a unit, wherein third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, repeat, no matter and motion vector be on the occasion of or negative value, the phenomenon that it repeats is all identical.Use an adder 53 again, adder 53 is connected in shift unit 52 and motion vector correction tables look-up 51, and it is the addition of tabling look-up of the result of three positions of motion vector logical shift to the right of view data and motion vector correction, and obtains the motion vector of view data.
Please refer to shown in Figure 7, reference address computational methods for the motion compensation of image processing of the present invention, its step comprises: step S100, three positions of the motion vector of logical shift view data to the right, then, step S102, setting up motion vector correction tables look-up, this motion vector correction is tabled look-up and is set up by the difference of three positions of motion vector logical shift to the right of video verification prototype and view data, three of zero-bits to the with the motion vector of view data are unit, per unit is represented the position 16 times, per 16 positions are a unit, the difference of three positions of the motion vector of computed image data logical shift to the right and video verification prototype, wherein the 3rd, four, five, six, seven, 14, the result of three positions of motion vector logical shift to the right of 15 positions and view data differs 1, all the other are identical, repeat, utilize this characteristic, then this shows three of zero-bits to the of the motion vector that needs the checking image data, if this value is the 3rd, four, five, six, seven, 14,15 positions then are set as 1 to the position 0 of block displacement address table.Afterwards, step S104 sets up block displacement address table, and this block displacement address table is known, just determines when image compression, and the block displacement address is meant the displacement address of the present view data block that is calculated with respect to image origin.Step S106, set the zero-bit of block displacement address table again, the value decision that the zero-bit of this block displacement address table is tabled look-up by motion vector correction, it is unaffected to be because the block displacement address all is eight multiple, its zero-bit, first and second are all zero.Step S108 at last with the result and the addition of view data displacement address of three positions of motion vector logical shift to the right of view data, obtains the reference address of motion compensation.
Wherein, set up the step S102 that motion vector correction is tabled look-up, also include: calculate the video verification prototype (VM) of DivX with c program, be meant the value of calculating the video verification prototype (VM) of DivX according to the definition of four motion vector pattern (Inter4v mode) of DivX.Its program is, after the motion vector of view data takes absolute value, divided by 16, multiply by 2 and take absolute value the remainder addition after tabling look-up of the motion vector of view data again, and is last again according to the sign of the motion vector of view data, determines its sign.Second step is three positions of motion vector logical shift to the right with c program computed image data, and the value of two more above-mentioned at last algorithms can obtain the comparative result as Fig. 5, and certainly, above-mentioned calculating also can be undertaken by alternate manner.Its result is a unit for three of zero-bits to the with the motion vector of view data, per unit is represented the position 16 times, per 16 positions are a unit, the difference of three positions of the motion vector of computed image data logical shift to the right and video verification prototype, wherein third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, repeat.
Aspect moving image expert group (MPEG4) specification, calculate in the chroma block in the Immediate Mode (non_inter_laced_predictation Direct mode) of noninterlaced, by moving image expert group (MPEG4) the video verification prototype that specification provided, its operation result is the same with DivX, so under the checking by c program, the circuit that we proposed can be supported this two kinds of specifications (spec).
Learn by prior art, realize out that its circuit is quite complicated according to the hardware circuit of the motion vector (MV) of two specifications (spec) institute computed image data of moving image expert group (MPEG4) and DivX.And the motion vector calculation of image processing of the present invention ground device can be simplified circuit and calculate correct result.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.
Claims (9)
1, a kind of reference address computing device of motion compensation of image processing is characterized in that, comprising:
One shift unit, it is with three positions of motion vector logical shift to the right of view data;
One motion vector correction is tabled look-up, and this motion vector correction is tabled look-up provides the difference correction value of three positions of the motion vector of view data logical shift to the right and video verification prototype;
One block displacement address table is connected in this motion vector correction and tables look-up, the displacement address with respect to image origin of the view data of calculating in order to provide; And
One adder is connected in this shift unit and this block displacement address table, in order to result and the displacement address addition of decoding block at present with three positions of motion vector logical shift to the right of view data, obtains the reference address of the motion compensation of view data.
2, the reference address computing device of the motion compensation of image processing according to claim 1 is characterized in that, this shift unit comprises three bit shift devices.
3, the reference address computing device of the motion compensation of image processing according to claim 1 is characterized in that, the corrected value that the zero-bit of this block displacement address table is tabled look-up by motion vector correction is set.
4, the reference address computing device of the motion compensation of image processing according to claim 1, it is characterized in that, three of the zero-bits to that this motion vector correction is tabled look-up with the motion vector of view data are unit, per unit is represented the position 16 times, per 16 positions are a unit, wherein third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, repeat.
5, a kind of motion vector calculation device of image processing is characterized in that, comprising:
One shift unit is with three positions of motion vector logical shift to the right of view data;
One motion vector correction is tabled look-up, and this motion vector correction is tabled look-up provides the difference correction value of three positions of the motion vector of view data logical shift to the right and video verification prototype; And
One adder is connected in this shift unit and this motion vector correction and tables look-up, and in order to addition that the result of three positions of motion vector logical shift to the right of view data and motion vector correction are tabled look-up, obtains the motion vector of view data.
6, the motion vector calculation device of image processing according to claim 5 is characterized in that, wherein this shift unit comprises three bit shift devices.
7, the motion vector calculation device of image processing according to claim 5, it is characterized in that, wherein this motion vector correction three of zero-bits to the of tabling look-up with the motion vector of view data are unit, per unit is represented the position 16 times, per 16 positions are a unit, wherein third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, repeat.
8, a kind of reference address computational methods of motion compensation of image processing is characterized in that, comprise the steps:
Three positions of the motion vector of logical shift view data to the right;
Set up motion vector correction and table look-up, this motion vector correction is tabled look-up and is set up by the difference of three positions of motion vector logical shift to the right of video verification prototype and view data;
Set up block displacement address table, the block displacement address table of this view data is known, just determines when image compression;
Set the zero-bit of block displacement address table, the zero-bit of the block displacement address table of this view data is by the motion vector correction decision of tabling look-up;
With the result of three positions of motion vector logical shift to the right of view data and the displacement address addition of block at present, obtain the reference address of motion compensation.
9, the reference address computational methods of the motion compensation of image processing according to claim 8 is characterized in that, wherein set up the step that motion vector correction is tabled look-up, and also include:
The value of the video verification prototype of computed image data is meant the value of coming the video verification prototype of computed image data according to the definition of view data;
Three positions of the motion vector of computed image data logical shift to the right; And
The value of two more above-mentioned formulas, available result is, three of zero-bits to the with the motion vector of view data are unit, per unit is represented the position 16 times, per 16 positions are a unit, wherein third and fourth, the result of three positions of motion vector logical shift to the right of five, six, seven, 14,15 positions and view data differs 1, all the other are identical, repeat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410086803XA CN100442851C (en) | 2004-10-28 | 2004-10-28 | Reference address computing device and method for motion compensation of image processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410086803XA CN100442851C (en) | 2004-10-28 | 2004-10-28 | Reference address computing device and method for motion compensation of image processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1767642A CN1767642A (en) | 2006-05-03 |
| CN100442851C true CN100442851C (en) | 2008-12-10 |
Family
ID=36743194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200410086803XA Expired - Fee Related CN100442851C (en) | 2004-10-28 | 2004-10-28 | Reference address computing device and method for motion compensation of image processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100442851C (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134084A (en) * | 1995-03-20 | 1996-10-23 | 大宇电子株式会社 | Improved motion compensation apparatus for use in image encoding system |
| CN1139358A (en) * | 1995-06-19 | 1997-01-01 | 三星电子株式会社 | Start and end adresses generating circuit for motion compensation during moving picture compression coding |
| US20010022817A1 (en) * | 2000-03-08 | 2001-09-20 | Toru Yamada | Image data processing apparatus and motion compensation processing method used therefor, and recording medium |
| CN1463161A (en) * | 2002-06-01 | 2003-12-24 | 三星电子株式会社 | Device and method of correcting image movement |
| US6778604B1 (en) * | 1998-11-05 | 2004-08-17 | Tektronix, Inc. | Motion compensation performance improvement by removing redundant edge information |
-
2004
- 2004-10-28 CN CNB200410086803XA patent/CN100442851C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134084A (en) * | 1995-03-20 | 1996-10-23 | 大宇电子株式会社 | Improved motion compensation apparatus for use in image encoding system |
| CN1139358A (en) * | 1995-06-19 | 1997-01-01 | 三星电子株式会社 | Start and end adresses generating circuit for motion compensation during moving picture compression coding |
| US6778604B1 (en) * | 1998-11-05 | 2004-08-17 | Tektronix, Inc. | Motion compensation performance improvement by removing redundant edge information |
| US20010022817A1 (en) * | 2000-03-08 | 2001-09-20 | Toru Yamada | Image data processing apparatus and motion compensation processing method used therefor, and recording medium |
| CN1463161A (en) * | 2002-06-01 | 2003-12-24 | 三星电子株式会社 | Device and method of correcting image movement |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1767642A (en) | 2006-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| AU2019229381B2 (en) | Image prediction method and device | |
| US6859499B2 (en) | Deblocking filtering apparatus and method | |
| CN102045561B (en) | Device and method of processing image data to be displayed on a display device | |
| JP2006041943A (en) | Motion vector detecting/compensating device | |
| CN101754047B (en) | Method for detection of film mode or camera mode | |
| JP5081898B2 (en) | Interpolated image generation method and system | |
| US20090016623A1 (en) | Image processing device, image processing method and program | |
| US8682088B2 (en) | Image processing apparatus and image processing method | |
| CN102187678A (en) | Encoding method and encoding device for compression encoding of moving images | |
| CN100442851C (en) | Reference address computing device and method for motion compensation of image processing | |
| JP4963220B2 (en) | Filter calculator and motion compensation device | |
| US20060083307A1 (en) | Apparatus and method for calculating the reference address of motion compensation of an image | |
| JP2009015637A (en) | Computational unit and image filtering apparatus | |
| JP4516051B2 (en) | Filter processing device, multiplier, and motion compensation processing device | |
| EP3941036A1 (en) | Method, electronic device, and storage medium for selecting reference frame | |
| US11614919B2 (en) | Circuit | |
| US8406552B1 (en) | Fast in-loop filtering in VC-1 | |
| US20050131979A1 (en) | Apparatus for calculating absolute difference value, and motion estimation apparatus and motion picture encoding apparatus which use the apparatus for calculating the absolute difference value | |
| US9756344B2 (en) | Intra refresh method for video encoding and a video encoder for performing the same | |
| US20110032993A1 (en) | Image decoding device, image decoding method, integrated circuit, and receiving device | |
| US8243831B2 (en) | Image deblocking filter and image processing device utilizing the same | |
| US7840080B1 (en) | Motion estimator architecture for low bit rate image communication | |
| US8390741B2 (en) | Image processing apparatus and image processing method | |
| JP4963194B2 (en) | Filter processing device, multiplier, and motion compensation processing device | |
| US8270478B2 (en) | Method and apparatus for computing a sliding sum of absolute differences |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081210 Termination date: 20131028 |