CN100437850C - Capacitor wiring substrate, decoupling circuit and high frequency circuit - Google Patents
Capacitor wiring substrate, decoupling circuit and high frequency circuit Download PDFInfo
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- CN100437850C CN100437850C CNB2003101047204A CN200310104720A CN100437850C CN 100437850 C CN100437850 C CN 100437850C CN B2003101047204 A CNB2003101047204 A CN B2003101047204A CN 200310104720 A CN200310104720 A CN 200310104720A CN 100437850 C CN100437850 C CN 100437850C
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Abstract
To provide a capacitor in which a low ESL and a high capacitance are realized.The capacitor has a stack member formed by stacking a plurality of dielectric layers, on the inside of which are arranged a plurality of internal electrodes arranged in the direction orthogonal to the direction of stacking, and a plurality of feed-through conductors electrically connected to the internal electrodes and penetrating the dielectric layers in the stacking direction, wherein the plurality of feed-through conductors is composed of a plurality of sorts of feed-through conductors different in the height positions of both upper ends and lower ends, while the plurality of sorts of feed-through conductors is provided with electrical inter-sort connections through connecting conductors arranged between contiguous dielectric layers. (C)2006,JPO&NCIPI.
Description
Technical field
The present invention relates to capacitor, circuit board, decoupling circuit and high-frequency circuit particularly, relate to the capacitor that can advantageously be suitable in high-frequency region, and the circuit board, decoupling circuit and the high-frequency circuit that use this capacitor to constitute.
Background technology
As representational capacitor, be that example describes with the stacked capacitor.
In the equivalent electric circuit that uses stacked capacitor, be designated as C in electrostatic capacitance, equivalent series inductance (ESL capacitor; When equivalent series inductance) being designated as L, resonance frequency (f0) is used
f0＝1/[2π×√(L×C)]
Relation represent.From this formula as can be known, if ESL is low, then resonance frequency (f0) raises, and can use in higher frequency domain.Therefore, in order in microwave region, to use stacked capacitor, need seek lower ESL.
In addition, stacked capacitor is accompanied by high speed, the high frequencyization of MPU in recent years in order to be used for the MPU chip supply power at microprocessing units such as work station or personal computer (MPU), requires to reduce ESL.
In addition, usually be connected high speed, the high frequencyization that stacked capacitor on the circuit board also is accompanied by MPU in recent years, require low ESLization as decoupling capacitor.
Here, according to Fig. 4 (a) and (b) in the past stacked capacitor is described simply.Fig. 4 (a) is the Y-Y line section plan of (b) that the overlap condition of the 1st and the 2nd conductor layer is shown.Fig. 4 (b) is the X-X line side cut away view of (a).
Stacked capacitor in the past 50 shown in Figure 4 is forming the 1st conductor layer 53 respectively on an interarea of dielectric layer 52, forming the 2nd conductor layer 54 on another interarea.Stacked a plurality of these dielectric layers 52.In addition, the thickness direction at these dielectric layers 52 is forming the 1st and the 2nd perforation conductor 55,56.The 1st perforation conductor 55 is connected to the 1st conductor layer 53, the 2 perforation conductors 56 and is connected to the 2nd conductive layer 54.Like this, constitute laminated body 51.
And the 1st and the 2nd connects the outermost surface that conductor 55,56 is exposed to a side of laminated body 51, connects the 1st and the 2nd splicing ear 57,58 respectively.Like this, constitute the stacked capacitor 50 of 2 terminals.
And then, in the 1st laminated body 53, form unconnected the 1st non-conductor with the 2nd perforation conductor 56 and form district 63, in the 2nd conductor layer 54, form respectively and form district 64 with the 1st perforation conductor 55 unconnected the 2nd non-conductors.
And the 1st and the 2nd connects conductor 55,56 shown in Fig. 4 (a), along the whole zone of the 1st and the 2nd conductor layer 53,54, alternately is configured to grid-shaped (referring to Patent Document 1 to 4).
[patent documentation 1]
Te Kaiping 7-201651 communique (3-5 page or leaf, Fig. 1-5)
[patent documentation 2]
Te Kaiping 11-204372 communique (4-6 page or leaf, Fig. 1-4)
[patent documentation 3]
The spy opens 2001-148324 communique (4-7 page or leaf, Fig. 1-6)
[patent documentation 4]
The spy opens 2001-148325 communique (5-7 page or leaf, Fig. 1-9)
Yet, if according to above-mentioned stacked capacitor 50,, then to consider to increase the 1st and the 2nd when connecting conductor 5,56 in order to seek to reduce ESL, reduce these the 1st and the 2nd methods that connects the distance between conductor 55,56 centers.
But,, then, therefore exist the problem of the electrostatic capacitance that can not increase stacked capacitor 50 because the non-conductor in the 1st and the 2nd conductor layer 53,54 forms the area increase in district 63,64 if do like this.
The present invention produces in view of the above-mentioned problems, and its purpose is to provide energy enough simple and cheap manufacture methods, realizes the capacitor of low ESL and high power capacity.
Other purpose of the present invention is to provide circuit board, decoupling circuit or the high-frequency circuit that uses capacitor as described above to constitute.
The content of invention
Capacitor of the present invention possesses:
The 1st capacitor part, it constitutes by forming following device: the 1st conductor layer and the 2nd conductor layer of mutual configuration between 1st dielectric layer stacked by most layers ground; Connect conductor with above-mentioned the 1st conductor layer the connected to one another a plurality of the 1st; Connect conductor with above-mentioned the 2nd conductor layer the connected to one another a plurality of the 2nd,
The 2nd capacitor part, it constitutes by forming following device: the 3rd conductor layer and the 4th conductor layer of mutual configuration between 2nd dielectric layer stacked by most layers ground; Connect conductor with above-mentioned the 3rd conductor layer the connected to one another the 3rd; Connect conductor with above-mentioned the 4th conductor layer the connected to one another the 4th,
Above-mentioned the 1st capacitor department and above-mentioned the 2nd capacitor department, at the stacked direction joint of dielectric layer,
Between above-mentioned the 1st capacitor department and above-mentioned the 2nd capacitor department, form the 1st bonding conductor layer and the 2nd bonding conductor layer,
The tale that above-mentioned the 1st perforation conductor and the above-mentioned the 2nd connects conductor is more than the tale that above-mentioned the 3rd perforation conductor and the 4th connects conductor, and, the above-mentioned the 1st at least one that connects conductor is connected to the above-mentioned the 3rd by above-mentioned the 1st bonding conductor layer and connects conductor, and the above-mentioned the 2nd at least one that connects conductor is connected to the above-mentioned the 4th by above-mentioned the 2nd bonding conductor layer and connects conductor.
Promptly, in the 1st capacitor part, connect the conductor tale of conductor owing to increasing the 1st and the 2nd, so shorten electric current, thereby reduction is by the self-inductance and the mutual inductance composition of the magnetic flux generation of induction by current along the distance that flows between two terminals of capacitor.Thus, can reduce the overall equivalent series inductance of capacitor (ESL).
The opposing party and, in the 2nd capacitor part,, therefore can make the 3rd conductor layer amass increase with the relative of the 4th conductor layer owing to can reduce by the 3rd and the 4th quantity that connects conductor.Thus, can make small-sized, the high capacity of the 2nd capacitor part.
According to these effects, can provide the capacitor of having realized low ESL and high power capacity.In addition, owing to the production line that does not need to change on a large scale in the past, therefore become simple and inexpensive method of manufacturing.
In addition, according to these characteristics, capacitor of the present invention possesses the circuit board with the circuit of high-frequency signal action at the circuit of high speed motion, and is effective especially in decoupling circuit or the high-frequency circuit.
And then capacitor of the present invention effectively utilizes at a high speed and jumbo feature, and it is also very favourable to be used as the decoupling circuit that is connected to the power circuit that is used for the MPU module that the MPU chip possesses.
Description of drawings
Fig. 1 illustrates stacked capacitor of the present invention, and X-X line sectional arrangement drawing (a) is shown, and (b) is the Y-Y line section plan that the overlap condition of the 1st, the 2nd conductor layer is shown, and (c) is the Z-Z line section plan that the overlap condition of the 3rd, the 4th conductor layer is shown.
Fig. 2 illustrates other example of stacked capacitor of the present invention, and V-V line sectional arrangement drawing (a) is shown, and (b) is the W-W line section plan that the charged state of the 2nd conductor layer is shown.
Fig. 3 illustrates the profile of structure example that stacked capacitor of the present invention is used as the MPU module of decoupling capacitor.
Fig. 4 illustrates stacked capacitor in the past, (a) is the plane graph that the overlap condition of the 1st, the 2nd conductor layer is shown, and (b) is profile.
Embodiment
Below, explain example of the present invention with reference to accompanying drawing.
Fig. 1 illustrates an example stacked capacitor as capacitor of the present invention, (a) be X-X line sectional arrangement drawing, (b) being the Y-Y line section plan that the overlap condition of the 1st, the 2nd conductor layer is shown, (c) is the Z-Z line section plan that the overlap condition of the 3rd, the 4th conductor layer is shown.
Among Fig. 1, stacked capacitor 10 at lamination form the 1st and the 2nd splicing ear 7a, 8a on the one side surface of laminated body 1 of a plurality of dielectric layers 2, simultaneously, form the 3rd and the 4th splicing ear 7b, 8b at the opposing party back side of laminated body 1.And then laminated body 1 engages with the 1st capacitor part 11 and the 2nd capacitor part 12 along stack direction.Shape is identical with the flat of the 2nd capacitor part 12 for the 1st capacitor part 11.
The 1st capacitor part 11 form respectively a plurality of by lamination dielectric layer 2; Be configured between the dielectric layer 2, through dielectric layer 2 relative the 1st conductor layer 3a and the 2nd conductor layer 4a; Connect the thickness direction of dielectric layer 2, the 1st perforation conductor 5a that couples together between the 1st conductive layer 3a; The 2nd perforation conductor 6a that couples together between the 2nd conductor layer 4a.And then the 1st and the 2nd connects the surface that conductor 5a, 6a expose a side of laminated body 1, is connected respectively to the 1st and the 2nd splicing ear 7a, 8a.And, in the 1st conductor layer 3a, form with unconnected the 1st non-conductor of the 2nd perforation conductor 6a and form district 13a, in the 2nd conductor layer 4a, form with unconnected the 2nd non-conductor of the 1st perforation conductor 5a and form district 14a.
On the other hand, the 2nd capacitor part 12 form respectively a plurality of by lamination dielectric layer 2; Be configured between the dielectric layer 2, through dielectric layer 2 relative the 3rd conductor layer 3b and the 4th conductor layer 4b; Connect the thickness direction of dielectric layer 2, the 3rd perforation conductor 5b that couples together between the 3rd conductive layer 3b; The 4th perforation conductor 6b that couples together between the 4th conductor layer 4b.And then the 3rd and the 4th connects the back side that conductor 5b, 6b expose a side of laminated body 1, is connected respectively to the 3rd and the 4th splicing ear 7b, 8b.And, in the 3rd conductor layer 3b, form with unconnected the 3rd non-conductor of the 4th perforation conductor 6b and form district 13b, in the 4th conductor layer 4b, form with unconnected the 4th non-conductor of the 3rd perforation conductor 5b and form district 14b.
According to above structure, though the 1st of the 1st capacitor part 11 connects the 1st conductor layer 3a that conductor 5a has been connected to along the thickness direction lamination, but owing to connect the 2nd non-conductor formation district 14a of the 2nd conductor layer 4a, therefore not conducting in the 2nd conductive layer 4a simultaneously with contactless state.Equally, though the 2nd of the 1st capacitor part 11 connects the 2nd conductor layer 4a that conductor 6a has been connected to along the thickness direction lamination, but owing to connect the 1st non-conductor formation district 13a of the 1st conductor layer 3a, therefore not conducting in the 1st conductor layer 3a simultaneously with contactless state.In addition, in the 2nd capacitor part 12 1 sides, for the 3rd perforation conductor 5b, the 4th perforation conductor 6b is also identical.
Here, the 1st configuration density that connects conductor 5a and the 2nd perforation conductor 6a connects the configuration density height that conductor 5b and the 4th connects conductor 6b than the 3rd.Therefore, because the 1st capacitor part 11 is identical with the flat shape of the 2nd capacitor part 12, thus the 1st the connecting conductor tale that conductor 5a and the 2nd connects conductor 6a also to connect the conductor tale of conductor 5b and the 4th perforation conductor 6b than the 3rd of the 2nd capacitor part 12 many of the 1st capacitor part 11.
In addition, the 1st at least one that connects conductor 5a of the 1st capacitor part 11 is connected to the 3rd of the 2nd capacitor part and connects conductor 5b, and be same, and the 2nd at least one that connects conductor 6a is connected to the 4th and connects conductor 6b.
In addition, when shortening the distance that electric current flows through, cancel out each other by the magnetic flux of induction by current, the 1st connects conductor 5a and the 2nd connects conductor 6a and alternately forms grid-shaped.
The 1st conductor layer 3a～the 4th conductor layer 4b is made of the material that with Ni, Cu or their alloy is main component, and its thickness is 1～2 μ m.In addition, the 1st perforation conductor 5a～4th perforation conductor 6b is made of the material that with Ni, Cu or their alloy is main component.In addition, splicing ear 7a, 8a, 7b, 8b use pad or spherical scolding tin etc.
Secondly, the manufacture method of stacked capacitor 10 of the present invention is described.In addition, in Fig. 1 etc., each symbol is as broad as long in the front and back of sintering.
At first, in the large-area green ceramic sheet 2 of the dielectric layer that becomes the 1st capacitor part 11, the printing drying by conductive paste forms electrically conductive film 3a, the 4a as the 1st and the 2nd conductor layer respectively.At this moment, also form the 1st and the 2nd non-conductor simultaneously and form district 13a, 14a.And then in the green ceramic sheet 2 of the dielectric body layer that becomes the 2nd capacitor part 12, the printing drying by conductive paste forms respectively as the 3rd and the 4th conductor layer electrically conductive film 3b, 4b.At this moment, also form the 3rd and the 4th non-conductor simultaneously and form district 13b, 14b.
Then, the alternately stacked needed number of the green ceramic sheet 2 that has formed electrically conductive film 3a, 4a, form the large-area laminated body that extracts the 1st capacitor part 11.Equally, the alternately stacked needed number of the green ceramic sheet 2 that has formed electrically conductive film 3b, 4b, form the large-area laminated body that extracts the 2nd capacitor part 12.
Then,, form electrically conductive film 3a, 4a, form the through hole that connects green ceramic sheet 2 along thickness direction on the surface of the laminated body that extracts the 1st capacitor part 11 by the irradiation of laser or the die-cut method of having used micropunch or having rocked.And then, by filling conductive paste in this through hole, form conductor part 5a, 6a as the 1st and the 2nd perforation conductor.Here, form and make the 1st through hole that connects conductor 5a that becomes the 1st capacitor part 11 connect the 1st conductor layer 3a with contact condition, the 2nd non-conductor that connects the 2nd conductor layer 4a with contactless state forms district 14a, become the 2nd through hole that connects conductor 6a and connect the 2nd conductor layer 4a with contact condition, the 1st non-conductor that connects the 1st conductor layer 3a with contactless state forms 13a.
Equally, form electrically conductive film 3b, 4b, form the through hole that connects green ceramic sheet 2 along thickness direction on the surface of the laminated body that extracts the 2nd capacitor part 12.And then, by filling conductive paste in this through hole, form conductor part 5b, 6b as the 3rd and the 4th perforation conductor.Here, form and make the 3rd through hole that connects conductor 5b that becomes the 2nd capacitor part 12 connect the 3rd conductor 3b with contact condition, the 4th non-conductor that connects the 4th conductor layer 4b with contactless state forms district 14b, become the 4th through hole that connects conductor 6b and connect the 4th conductor layer 4b with contact condition, the 3rd non-conductor that connects the 3rd conductor layer 3b with contactless state forms district 13b.
Then, the stacked above-mentioned large-scale laminated body that extracts the 1st capacitor part the 11, the 2nd capacitor part 12.At this moment, carry out feasible the 1st one of connecting conductor 5a who is formed on the 1st capacitor part 11 of contraposition and be connected to the 3rd perforation conductor 5b that is formed on the 2nd capacitor part 12, and, one of the 2nd capacitor 6a who is formed on the 1st capacitor part 11 is connected to and is formed on the 4th of the 2nd capacitor part 12 and connects conductor 6b, and is simultaneously stacked along vertical direction.
Then, large-scale laminated body is processed by shearing blade, cut-outs such as cutting mode obtain the not laminated body 1 of sintering state.
In addition, the technology that replaces above formation through hole, also can become on the green ceramic sheet 2 of dielectric body layer, according to die-cut method of having used micropunch or having rocked etc., leave through hole in advance, according to the screen printing method, printing on green ceramic sheet 2 becomes in the electrically conductive film of conductor layer 3a～4b, by filling conductive paste in through hole, form and laminated conductor part 5a～6b.
Then, for this laminated body 1 of sintering state not, carried out carrying out sintering after debinding handles.
Like this, can obtain forming the 1st conductor layer 3a～the 4th conductor layer 4b in inside, when the 1st perforation conductor 5a～4th connects conductor 6b, the 1st at least one that connects conductor 5a is electrically connected to the 3rd and connects conductor 5b, and the 2nd at least one that connects conductor 6a be electrically connected to the 4th and connect conductor 6b, exposed the 1st and the 2nd on a side surface and connected conductor 5a, 6a, exposed the laminated body 1 of the 3rd and the 4th perforation conductor 5b, 6b at the opposing party back side.
At this moment, the 1st connects conductor 5a～4th connects conductor 6b owing to the surface is oxidized, therefore removes oxide film thereon by surface grinding.
Then, connect exposed portions serve, the formation Ni coating that conductor 5a～4th connects conductor 6b, Sn coating the 1st.Also can be the coating of Au or Cu.
Then, according to the method for screen printing scolding tin glue or applying the method that flux carries ball bonding tin later on, form scolding tin as splicing ear 7a, 8a, 7b, 8b.Then, by implementing to backflow processing, form splicing ear 7a, 8a, 7b, 8b.In addition, in the 2nd capacitor part 12, also can connect in the exposed portions serve of conductor 5b, 6b, form splicing ear 7b, 8b the 3rd and the 4th.
Like this, can obtain stacked capacitor shown in Figure 1 10.
Fig. 2 illustrates other example of stacked capacitor of the present invention, (a) is V-V line longitudinal axis face figure, (b) is the W-W line section plan that the overlap condition of the 2nd conductor layer is shown.
Among Fig. 2, through bonding conductor layer 5c, the 1st perforation conductor 5a and the 3rd connects conductor 5b and is connected, and through bonding conductor layer 6c, the 2nd perforation conductor 6a and the 4th connects conductor 6b and is connected.
If according to Fig. 2, then between the 1st capacitor part 11 and the 2nd capacitor part 12, forming bonding conductor layer 5c, the 6c shown in Fig. 2 (b).The 1st connects conductor 5a is connected to the 3rd perforation conductor 5b through bonding conductor layer 5c, and same, the 2nd perforation conductor 6a is connected to the 4th through bonding conductor layer 6c and connects conductor 6b.
Like this,, make configuration freely the 3rd and the 4th connect conductor 5b, 6b, simultaneously, greatly improve two connection reliability that connect conductor by intermediate configurations bonding conductor layer 5c, 6c in the 1st capacitor part 11 and the 2nd capacitor part 12.
In addition, also can form this connection electrode 5c at two opposite faces of the 1st capacitor part 11 and the 2nd capacitor part 12, two opposite faces in the 1st capacitor part 11 and the 2nd capacitor part 12 form connection electrode 6c, add a slice dielectric layer 2 therebetween, connect the connection electrode of positive and negative with the support holes conductor that connects dielectric layer 2.
Fig. 3 illustrates the profile of structure example that stacked capacitor 10 of the present invention is used as the MPU module 20 of decoupling capacitor.
As shown in Figure 3, MPU chip 30 is installed on circuit board 21.In addition, on circuit board 21, when stacked capacitor 10 of the present invention (A) is installed, in the cavity of circuit board 21, accommodating stacked capacitor 10 of the present invention (B).And stacked capacitor 10 (A), 10 (B) are parallel-connected to power supply terminal P, G, play the effect of decoupling capacitor.
In the inside of circuit board 21, forming mains side conductor layer 23 and ground connection side conductor layer 24.Mains side conductor layer 23 connects conductor 25 through mains side and is electrically connected to power supply terminal P.Ground connection side conductor layer 24 connects conductor 26 through the ground connection side and is electrically connected to earth terminal G.The electrode of MPU chip 30 is connected respectively to mains side conductor layer 23 and ground connection side conductor layer 24.
The 1st splicing ear 7a of stacked capacitor 10 (A) connects conductor 25 through mains side conductor layer 23, mains side, is connected to power supply terminal P.The 2nd splicing ear 8a of stacked capacitor 10 (A) connects conductor 26 through ground connection side conductor layer 24, ground connection side, is connected to earth terminal G.
Here, laminated body, capacitor 10 (A) only utilizes the 1st splicing ear 7a, the 2nd splicing ear 8a on surface.Can not form the 3rd, the 4th splicing ear 7b, the 8b at the back side.At this moment, if do not remove the oxide film thereon of the 3rd, the 4th perforation conductor 5b, 6b, then, therefore preferably do not remove the oxide film thereon of the 3rd, the 4th perforation conductor 5b, 6b owing to can prevent unnecessary conducting.
The the 1st, the 3rd splicing ear 7a, the 7b of laminated body capacitor 10 (B) is through mains side conductor layer 23, be electrically connected to power supply terminal P, simultaneously, the 2nd, the 4th splicing ear 8a, the 8b of stacked capacitor 10 (B) are electrically connected to earth terminal G through ground connection side conductor layer 24.
As described above, if foundation stacked capacitor 10 of the present invention (A B), then owing to be big capacity, hangs down ESL, so under situation about using as the decoupling capacitor in the CPU module 20, also can be corresponding fully with high speed motion.
And then, being not limited to MPU module 20, can also be useful in stacked capacitor 10 in the circuit board of general radio communication device.
In addition, the present invention is not limited to above example, adds various changes without departing from the spirit and scope of the present invention, improvement does not have any obstacle yet.
Embodiment
Generate stacked capacitor of the present invention 10 shown in Figure 1 and laminated body in the past 50 shown in Figure 4, measured electrostatic capacitance C and equivalent series inductance L.Here, both sides' size of stacked capacitor 10,50 all is 3.2mm * 3.2mm, has formed to grid-shaped to amount to 36 the 1st and the 2nd perforation conductor 5a (55), 6a (56).Have only stacked capacitor 10 to form and amount to 2 the 3rd and the 4th perforation conductor 5b, 6b at middle body.
The result who measures, stacked capacitor in the past 50 shown in Figure 4 becomes C=7.8 μ F, and L=20pH is relative therewith, and stacked capacitor of the present invention 10 shown in Figure 1 becomes C=15 μ F, L=8pH.
As can be known from these results, stacked capacitor 10 of the present invention is because the conductor tale of the 1st perforation conductor 5a and the 2nd perforation conductor 6a is more than the conductor tale that above-mentioned the 3rd perforation conductor 5b and the 4th connects conductor 6b, the 1st one of connecting conductor 5a is connected to the 3rd and connects conductor 5b, the 2nd one of connecting conductor 6a is connected to the 4th and connects conductor 6b, therefore can realize low ESL and jumbo stacked capacitor.
Claims (9)
1. capacitor is characterised in that:
Possess:
The 1st capacitor part, it constitutes by forming following device: the 1st conductor layer and the 2nd conductor layer of mutual configuration between by the 1st multilayer laminated dielectric layer; Connect conductor with above-mentioned the 1st conductor layer the connected to one another a plurality of the 1st; Connect conductor with above-mentioned the 2nd conductor layer the connected to one another a plurality of the 2nd,
The 2nd capacitor part, it constitutes by forming following device: the 3rd conductor layer and the 4th conductor layer of mutual configuration between by the 2nd multilayer laminated dielectric layer; Connect conductor with above-mentioned the 3rd conductor layer the connected to one another the 3rd; Connect conductor with above-mentioned the 4th conductor layer the connected to one another the 4th,
Above-mentioned the 1st capacitor part and above-mentioned the 2nd capacitor part, at the stacked direction joint of dielectric layer,
Between above-mentioned the 1st capacitor part and above-mentioned the 2nd capacitor part, form the 1st bonding conductor layer and the 2nd bonding conductor layer,
The tale that above-mentioned the 1st perforation conductor and the above-mentioned the 2nd connects conductor is more than the tale that above-mentioned the 3rd perforation conductor and the 4th connects conductor, and, the above-mentioned the 1st at least one that connects conductor is connected to the above-mentioned the 3rd by above-mentioned the 1st bonding conductor layer and connects conductor, and the above-mentioned the 2nd at least one that connects conductor is connected to the above-mentioned the 4th by above-mentioned the 2nd bonding conductor layer and connects conductor.
2. capacitor is characterised in that:
Possess
The 1st capacitor part, it constitutes by forming following device: the 1st conductor layer and the 2nd conductor layer of mutual configuration between by the 1st multilayer laminated dielectric layer; Connect conductor with above-mentioned the 1st conductor layer the connected to one another a plurality of the 1st; Connect conductor with above-mentioned the 2nd conductor layer the connected to one another a plurality of the 2nd,
The 2nd capacitor part, it constitutes by forming following device: the 3rd conductor layer and the 4th conductor layer of mutual configuration between by the 2nd multilayer laminated dielectric layer; Connect conductor with above-mentioned the 3rd conductor layer the connected to one another the 3rd; Connect conductor with above-mentioned the 4th conductor layer the connected to one another the 4th,
Above-mentioned the 1st capacitor part and above-mentioned the 2nd capacitor part, at the stacked direction joint of dielectric layer,
Between above-mentioned the 1st capacitor part and above-mentioned the 2nd capacitor part, form the 1st bonding conductor layer and the 2nd bonding conductor layer,
The above-mentioned the 1st connects conductor and the above-mentioned the 2nd connects the configuration density height of the configuration density of conductor than above-mentioned the 3rd perforation conductor and the 4th perforation conductor, and, the above-mentioned the 1st at least one that connects conductor is connected to the above-mentioned the 3rd by above-mentioned the 1st bonding conductor layer and connects conductor, and the above-mentioned the 2nd at least one that connects conductor is connected to the above-mentioned the 4th by above-mentioned the 2nd bonding conductor layer and connects conductor.
3. capacitor according to claim 1 and 2 is characterised in that:
The above-mentioned the 1st connects conductor and the 2nd connects the conductor decentralized configuration on the plane of dielectric layer.
4. capacitor according to claim 3 is characterised in that:
Above-mentioned the 1st perforation conductor and the 2nd connects conductor and disposes in the mode that adjoins each other across identical distance.
5. capacitor according to claim 1 is characterised in that:
The 1st capacitor part and the 2nd capacitor part engage by the 3rd dielectric layer,
On two faces of facing mutually of the 1st capacitor part and the 2nd capacitor part, form the 1st bonding conductor layer respectively, connect conductor with above-mentioned the 1st bonding conductor layer the connected to one another the 5th and connect above-mentioned the 3rd dielectric layer and form,
On two faces of facing mutually of the 1st capacitor part and the 2nd capacitor part, form the 2nd bonding conductor layer respectively, connect conductor with above-mentioned the 2nd bonding conductor layer the connected to one another the 6th and connect above-mentioned the 3rd dielectric layer and form.
6. capacitor according to claim 2 is characterised in that:
The 1st capacitor part and the 2nd capacitor part engage by the 3rd dielectric layer,
On two faces of facing mutually of the 1st capacitor part and the 2nd capacitor part, form the 1st bonding conductor layer respectively, connect conductor with above-mentioned the 1st bonding conductor layer the connected to one another the 5th and connect above-mentioned the 3rd dielectric layer and form,
On two faces of facing mutually of the 1st capacitor part and the 2nd capacitor part, form the 2nd bonding conductor layer respectively, connect conductor with above-mentioned the 2nd bonding conductor layer the connected to one another the 6th and connect above-mentioned the 3rd dielectric layer and form.
7. circuit board is characterised in that:
Possess claim 1,2,5, each described capacitor of 6.
8. decoupling circuit is characterised in that:
Possess claim 1,2,5, each described capacitor of 6.
9. high-frequency circuit is characterised in that:
Possess claim 1,2,5, each described capacitor of 6.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002316793 | 2002-10-30 | ||
| JP2002316793 | 2002-10-30 |
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| CN1499546A CN1499546A (en) | 2004-05-26 |
| CN100437850C true CN100437850C (en) | 2008-11-26 |
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| CNB2003101047204A Expired - Fee Related CN100437850C (en) | 2002-10-30 | 2003-10-30 | Capacitor wiring substrate, decoupling circuit and high frequency circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3214629B1 (en) * | 2014-10-30 | 2021-05-12 | Hitachi Automotive Systems, Ltd. | Laminated capacitor and in-vehicle control device |
| US10229789B2 (en) * | 2016-10-28 | 2019-03-12 | Samsung Electro-Mechanics Co., Ltd. | Multilayer thin-film capacitor |
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2003
- 2003-10-30 CN CNB2003101047204A patent/CN100437850C/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07326536A (en) * | 1994-05-31 | 1995-12-12 | Kyocera Corp | Ceramic capacitor |
| JPH0817675A (en) * | 1994-06-24 | 1996-01-19 | Kyocera Corp | Chip type laminated ceramic capacitor |
| US6034864A (en) * | 1997-11-14 | 2000-03-07 | Murata Manufacturing Co., Ltd. | Multilayer capacitor |
| US6344961B1 (en) * | 1999-11-19 | 2002-02-05 | Murata Manufacturing Co., Ltd | Multi-layer capacitator, wiring substrate, decoupling circuit, and high-frequency circuit |
| US6351369B1 (en) * | 1999-11-19 | 2002-02-26 | Murata Manufacturing Co., Ltd | Multi-layer capacitor, wiring substrate, decoupling circuit, and high-frequency circuit |
| US6407907B1 (en) * | 1999-12-28 | 2002-06-18 | Tdk Corporation | Multilayer ceramic capacitor |
| US6452781B1 (en) * | 2000-10-06 | 2002-09-17 | Tdk Corporation | Multilayer electronic device |
| WO2002054421A2 (en) * | 2000-12-29 | 2002-07-11 | Intel Corporation | Multiple tier array capacitor and methods of fabrication therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1499546A (en) | 2004-05-26 |
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Granted publication date: 20081126 Termination date: 20131030 |