CN100435484C - Qatput mode circuit of high speed A/D converter - Google Patents
Qatput mode circuit of high speed A/D converter Download PDFInfo
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- CN100435484C CN100435484C CNB2006100542227A CN200610054222A CN100435484C CN 100435484 C CN100435484 C CN 100435484C CN B2006100542227 A CNB2006100542227 A CN B2006100542227A CN 200610054222 A CN200610054222 A CN 200610054222A CN 100435484 C CN100435484 C CN 100435484C
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Abstract
The present invention relates to an output mode circuit for a high speed A/D converter, which comprises a two-way divider, wherein the data output end of data from the inner part of an A/D converter is selected by quantity which is input a control electrical level to output data to a CMOS concurrent output and CMOS alternative output circuits which are connected by five D type master slave flipflops, and a CMOS-LVDS electrical level translator; a two divide frequency divider, a not gate and an output time sequence control circuit respectively supplies clock signals to the five D type master slave flipflops of the CMOS concurrent output and the CMOS alternative output circuits. Thus, the output mode circuit has three alternative output modes, well meets the requirements for the data output mode by the high speed and the super high speed A/D converters, greatly improves convenience and flexibility of the selection of the output mode according to the practical situation of data acquisition and processing. The present invention is good for data acquisition, and has the advantages of reliable output data and high data accuracy.
Description
(1) technical field
The present invention relates to be used for the output integrated circuit of A/D converter, particularly a kind of high-speed a/d converter Qatput mode circuit.Use high speed, the super high-speed A/D transducer of this Qatput mode circuit to be widely used in the equipments such as digital oscilloscope, radar, sonar and electronic countermeasures, carry out data acquisition and processing (DAP).
(2) background technology
Common A/D converter dateout is the CMOS/TTL serial data way of output, and output data rate is identical with clock frequency, along with the increase output data rate of clock frequency also increases.But at a high speed, super high-speed A/D transducer is as adopting the CMOS/TTL serial data way of output again, then data rate is very high, increased the data acquisition difficulty, the device of A/D converter output interface is necessary for CMOS or TTL high speed device, increased the selection difficulty of A/D converter output interface device, be unfavorable for reducing cost.Simultaneously, along with the raising of A/D converter speed, former the CMOS/TTL serial data way of output and output circuit thereof can not meet the demands, and occur loss of data easily, and the dateout precision is not high.Therefore, must seek to be suitable for the data way of output of high-speed a/d converter and used Qatput mode circuit thereof.
At present, the data way of output of the high-speed a/d converter more than the sample rate 200MSPS mainly contains 3 kinds of forms: (1) has only the CMOS alternate mode; (2) has only LVDS pattern (Low Voltage Differential Signal), two kinds of (3) CMOS alternate mode and LVDS patterns.But convenience and the flexibility of carrying out way of output selection according to the actual conditions of data acquisition and processing (DAP) are relatively poor, have simultaneously that CMOS is parallel, CMOS alternately and the high-speed a/d converter technology of three kinds of pattern way of outputs of LVDS yet there are no report, corresponding high-speed a/d converter also yet there are no report both at home and abroad with Qatput mode circuit.
(3) summary of the invention
Technical problem to be solved by this invention is to invent a kind of high-speed a/d converter Qatput mode circuit, with the requirement of satisfying at a high speed, super high-speed A/D transducer data are exported, has parallel, the CMOS alternate data output mode of LVDS (Low Voltage Differential Signal), CMOS simultaneously, raising is carried out convenience and the flexibility that the way of output is selected according to the actual conditions of data acquisition and processing (DAP), makes and is easy to image data, dateout is more reliable, precision is higher.
The present invention solves the problems of the technologies described above the technical scheme of being taked and is that Qatput mode circuit of the present invention comprises a two-way distributor, have a data input pin, a control level input and two data outputs, by the height of input control level to from the one digit number of A/D converter inside according to selecting its data output end;
÷ 2 frequency dividers carry out ÷ 2 frequency divisions to the clock signal of input, and output frequency is the clock signal of input clock frequency 1/2nd;
Not gate for CMOS inverter formation, its input is connected with the output of ÷ 2 frequency dividers, carries out anti-phase to the clock signal of input;
An output timing control circuit, its input end of clock is connected with the output of ÷ 2 frequency dividers, and the clock signal of input is carried out the sequential conversion, is controlled the phase relation of two outputs by the height of input control level;
One by five D type master-slave flip-flop F1, F2, F3, F4, CMOS that F5 is linked to be and line output and CMOS replace output circuit, be divided into two groups, the data output end of the D type master-slave flip-flop of previous stage is connected with the data input pin of back one-level D type master-slave flip-flop in every group, the data input pin of every group of first order D type master-slave flip-flop is connected with arbitrary data output end of two-way distributor, the input end of clock of 5 D type master-slave flip-flops respectively with ÷ 2 frequency dividers, not gate, the output of output timing control circuit connects, data to input under the clock effect are shifted, output CMOS parallel data or CMOS alternate data;
A CMOS-LVDS level translator is connected with arbitrary data output end of two-way distributor, and the CMOS level of importing is carried out level conversion, output Low Voltage Differential Signal LVDS.
Described two-way distributor circuit is formed by connecting by two cmos transmission gates and a CMOS inverter, its data input pin and two data output ends are located on the cmos transmission gate, its control level input one tunnel directly is connected with one group of grid of two cmos transmission gates, and the CMOS inverter of leading up to is connected with another group grid of two cmos transmission gates.
The circuit structure of five D type master-slave flip-flops that described formation CMOS and line output and CMOS replace output circuit is identical, the circuit of its each D type master-slave flip-flop constitutes by connect two-stage CMOS inverter in the output of general CMOS D type master-slave flip-flop, cascade between two CMOS inverters is not established the data output end of D type master-slave flip-flop on the level CMOS inverter.
Described ÷ 2 divider circuits constitute by connect three grades of CMOS inverters in the output of general CMOS D type master-slave flip-flop, the output of an one CMOS inverter is connected with the data input pin of general CMOS D type master-slave flip-flop, behind other two CMOS inverter cascades as the output of ÷ 2 frequency dividers.
Described output timing control circuit comprises three not gates that three CMOS inverters form, a two-way selector, respectively by six CMOS inverters is connected identical with structure of cmos transmission gate and constitute two groups drive delay circuits, after one of them not gate is anti-phase, be divided into three tunnel outputs from the clock signal of ÷ 2 frequency dividers of its input end of clock input, one the tunnel is anti-phase after cmos transmission gate is passed to connected one group of driving delay circuit by a not gate, form one of output of output timing control circuit, one the tunnel directly is connected with an input of two-way selector, one the tunnel is connected with this two-way selector one input after a not gate is anti-phase, the two-way selector is provided with the control level input, height by the input control level is selected this two input, the two-way selector output end is connected with one group of driving delay circuit, forms one of output of output timing control circuit.
Described two-way selector circuit is formed by connecting by two cmos transmission gates and a CMOS inverter, two cmos transmission gate inputs are respectively two inputs of two-way selector, the output of two cmos transmission gates is the output of two-way selector, control level input one tunnel directly is connected with one group of grid of two cmos transmission gates, and one the tunnel is connected with another group grid of two cmos transmission gates after the CMOS inverter is anti-phase.
Described CMOS-LVDS level converter circuit is formed by connecting by three CMOS inverters, cmos transmission gate, differential amplifier, level conversion unit and a biasing circuit, cascade between three CMOS inverters, establish CMOS-LVDS level translator input on the first order CMOS inverter gate, second level CMOS inverter output is connected with the cmos transmission gate input, level CMOS inverter is not connected with differential amplifier, level conversion unit input with the cmos transmission gate output, establishes CMOS-LVDS level translator output on the level conversion unit.
Beneficial effect.Because the present invention has adopted technique scheme, have CMOS and line output simultaneously, CMOS is output and LVDS Qatput mode circuit alternately, use it at a high speed, super high-speed A/D transducer is as output circuit, make at a high speed, it is parallel that super high-speed A/D transducer can have CMOS simultaneously, CMOS replaces and the LVDS output mode, see Table 1 (logic function table), because the parallel output mode of CMOS is 1/2nd of an input clock frequency with the output data rate that replaces Qatput mode circuit, compare data rate with the serial data way of output and reduce by one times, the option interface circuit improves data acquisition accuracy and sample rate easily.Though the LVDS output data rate is identical with clock frequency, LVDS is difference output, and amplitude is very little, is about 350mV, and very high transmission speed and good switch performance are arranged.Therefore Qatput mode circuit of the present invention can satisfy the requirement to the data way of output of high speed, super high-speed A/D transducer well, improved greatly according to the actual conditions of data acquisition and processing (DAP) and carried out convenience that the way of output selects and flexibility (can select wherein a kind of, two or three), made and be easy to image data, dateout is more reliable, data precision is higher.
(4) description of drawings
Fig. 1 is a schematic block circuit diagram of the present invention;
Fig. 2 is an output timing control circuit block diagram of the present invention;
Fig. 3 is a two-way distributor circuit structure diagram of the present invention;
Fig. 4 is a D type of a present invention master-slave flip-flop circuit structure diagram;
Fig. 5 is ÷ 2 divider circuit structure charts of the present invention;
Fig. 6 is an output timing control circuit structure chart of the present invention;
Fig. 7 is a CMOS-LVDS level converter circuit structure chart of the present invention;
Fig. 8 is the connection layout of Qatput mode circuit of the present invention and M position high-speed a/d converter;
Fig. 9 is a work schedule oscillogram of the present invention;
Figure 10 is the timing diagram of ÷ 2 frequency dividers output of the present invention and two-way distributor output;
Figure 11 is the timing diagram of not gate output of the present invention and two-way distributor output;
Figure 12 is two timing diagrams of the input of level D type master-slave flip-flop data and clock not that CMOS of the present invention and line output and CMOS replace output circuit.
Table 1 logic function table
(5) embodiment
The specific embodiment of the present invention is not limited only to following description, is now further specified in conjunction with the accompanying drawings.
As shown in Figure 1, Qatput mode circuit of the present invention comprises a two-way distributor DMUX, ÷ 2 frequency divider, not gate, output timing control circuit, the CMOS that is linked to be by five D type master-slave flip-flop F1, F2, F3, F4, F5 and line output and CMOS replace output circuit, a CMOS-LVDS level translator.
Two-way distributor DMUX: have a data input pin IN, a control level input M
2With two data output OUT1, OUT2, by input control level M
2Height to from the encoded of A/D converter inside and latch after the one digit number certificate, as M bit data D
M, select its data output end OUT1, OUT2, M
2During for high level, select data output end OUT2, replace the output circuit dateout to the CMOS that is linked to be by five D type master-slave flip-flop F1, F2, F3, F4, F5 and line output and CMOS, this moment, OUT1 disconnected, and free of data output is in high-impedance state, M
2During for low level, select data output end OUT1, to CMOS-LVDS level translator dateout, this moment, OUT2 disconnected, and free of data output is in high-impedance state.Two cmos transmission gates that its circuit manages that PM1, PM2 and NMOS pipe NM1, NM2 constitute by PMOS and manage the CMOS inverter (not gate) that NM3 constitutes by PMOS pipe PM3 and NMOS and be formed by connecting, its data input pin IN and two data output end OUT1, OUT2 are located on the cmos transmission gate, its control level input M
2One the tunnel directly is connected with one group of grid of two cmos transmission gates, and the not gate of leading up to is connected its structure such as Fig. 1, shown in Figure 3 with one group of grid of two cmos transmission gates.Data input pin IN meets the M bit data output D after the inner encoded and latches of A/D converter during use
M, data transaction speed is identical with clock frequency.The output OUT2 data transaction of two-way distributor DMUX between the low period of ÷ 2 frequency divider output Q, and than ÷ 2 frequency dividers output trailing edge hysteresis t
1, t
1Between cycle, its sequential relationship as shown in figure 10 at 120 psecs (ps) and 1/2nd clocks.The maximum operating frequency of requirement two-way distributor exceeds more than the 100MHz than the maximum clock frequency of A/D converter work.
÷ 2 frequency dividers: the clock signal C LOCK from its input CLK input is carried out ÷ 2 frequency divisions, from its output Q output frequency is the clock signal of input clock frequency 1/2nd, its circuit constitutes by connect three grades of CMOS inverters in the output of general CMOS D type master-slave flip-flop, the output of an one CMOS inverter is connected with the data input pin of general CMOS D type master-slave flip-flop, behind other two CMOS inverter cascades as the output Q of ÷ 2 frequency dividers, to by five D type master-slave flip-flop F1, F2, F3, F4, CMOS that F5 is linked to be and line output and CMOS replace a D type master-slave flip-flop F1 of output circuit, not gate and output timing control circuit are carried clock signal, its structure such as Fig. 1, shown in Figure 5.Its input clock signal CLOCK frequency is the clock frequency of A/D converter, and the output conversion is at the rising edge of clock, and the sequential relation as shown in figure 10.Require more than the maximum clock frequency 100MHz of its maximum operating frequency greater than A/D converter work.
Not gate: be the CMOS inverter, be connected with the output Q of ÷ 2 frequency dividers, the clock signal of input is carried out anti-phase, the D type master-slave flip-flop F2, the F4 that replace output circuit to the CMOS that is linked to be by five D type master-slave flip-flop F1, F2, F3, F4, F5 and line output and CMOS provide clock signal.Its output is exported leading t than two-way distributor DMUX output OUT2
2, t
2Be that sequential relationship as shown in figure 11 more than 30 psecs (ps).
The output timing control circuit: its input end of clock CLK is connected with the output Q of ÷ 2 frequency dividers, and the clock signal of input is carried out the sequential conversion, by input control level M
1The phase relation of height control two output Q1, Q2, the not level D type master-slave flip-flop F3, the F5 that replace output circuit to the CMOS that is linked to be by five D type master-slave flip-flop F1, F2, F3, F4, F5 and line output and CMOS provide clock signal.This output timing control circuit comprises three not gates that three CMOS inverters form, a two-way selector MUX, respectively by six CMOS inverters is connected identical with structure of cmos transmission gate TG and constitute two groups drive delay circuits, after one of them not gate is anti-phase, be divided into three tunnel outputs from the clock signal behind ÷ 2 frequency divider frequency divisions of its input end of clock CLK input, one the tunnel is anti-phase after cmos transmission gate TG passes to connected one group of input IN that drives delay circuit by a not gate, its output Q forms one of the output of output timing control circuit Q1, one the tunnel directly is connected with the input IN1 of two-way selector MUX, one the tunnel is connected with this two-way selector MUX one input IN2 after a not gate is anti-phase, and the two-way selector is provided with control level input M
1, by input control level M
1Height this two input IN1, IN2 are selected, thereby the phase relation of control output timing control circuit two output Q1, Q2, i.e. M
1During for high level, select the input IN1 of two-way selector MUX, the phase place of output timing control circuit two output Q1, Q2 is opposite, and CMOS that five D type master-slave flip-flops are linked to be and line output and CMOS replace D type master-slave flip-flop F3, the F5 output CMOS alternate data Q of output circuit
A, Q
BWhen M1 is low level, select the input IN2 of two-way selector MUX, the phase place of output timing control circuit two output Q1, Q2 is identical, and CMOS that five D type master-slave flip-flops are linked to be and line output and CMOS replace D type master-slave flip-flop F3, the F5 output CMOS parallel data Q of output circuit
A, Q
BTwo-way selector MUX output OUT is connected with one group of input IN that drives delay circuit, and its output Q forms one of the output of output timing control circuit Q2.Described two-way selector MUX circuit is formed by connecting by two cmos transmission gates and a CMOS inverter (not gate), two cmos transmission gate inputs are respectively two input IN1, the IN2 of two-way selector, the output of two cmos transmission gates is the output OUT of two-way selector, control level input M
1A road directly be connected with one group of grid of two cmos transmission gates, the one tunnel is connected the structure of output timing control circuit such as Fig. 1, Fig. 2, shown in Figure 6 with another group grid of two cmos transmission gates after the CMOS inverter is anti-phase.The output timing control circuit is input to the difference of the transmission delay of output Q1 and Q2 should be less than 80ps, output Q1, Q2 provide clock for not level trigger F3 and trigger F5 that CMOS and line output and CMOS replace output circuit, and sequential relationship should satisfy Figure 12 requirement.
CMOS that is linked to be by five D type master-slave flip-flops and line output and CMOS replace output circuit: five D type master-slave flip-flop F1, F2, F3, F4, F5 is divided into two groups, its every group of first order D type master-slave flip-flop F1, the data input pin D of F4 is connected with the data output end OUT2 of two-way distributor DMUX, the D type master-slave flip-flop F1 of each group, F2, F3 and F4, the data output end Q of previous stage is connected with the data input pin D of back one-level between F5, the input end of clock C of each D type master-slave flip-flop respectively with ÷ 2 frequency dividers, not gate, the output of output timing control circuit connects, the input end of clock C that is master-slave flip-flop F1 is connected with the output Q of ÷ 2 frequency dividers, F2, the output of the input end of clock C NAND gate of F4 connects, not the level F3, the input end of clock C of F5 respectively with the output Q1 of output timing control circuit, Q2 connects, data to input under the clock effect are shifted, never level master-slave flip-flop F3, output Q output CMOS parallel data or the CMOS alternate data Q of F5
A, Q
BThe circuit structure of five D type master-slave flip-flops is identical, the circuit of its each D type master-slave flip-flop constitutes by connect two-stage CMOS inverter in the output of general CMOS D type master-slave flip-flop, cascade between two CMOS inverters is not established the data output end Q of D type master-slave flip-flop on the level CMOS inverter.CMOS and line output and CMOS replace output circuit structure such as Fig. 1, shown in Figure 4.The input data are inserted trigger between the clock low period, and trigger F3, F5 dateout between the clock high period are more than the maximum clock frequency 100MHz of trigger maximum operating frequency greater than A/D converter work.As shown in figure 12, replace the data input of the not level trigger F3 of output circuit and trigger F5 and the sequential relationship of clock for CMOS and line output and CMOS.T among Figure 12
3, t
4Should satisfy t
3+ t
4=T, and t
4〉=50ps, t
3〉=0.5T, T are the clock cycle of A/D converter work.Just can satisfy parallel schema as long as satisfy the sequential relationship of alternate mode.
The CMOS-LVDS level translator: its input IN is connected with the data output end OUT1 of two-way distributor DMUX, and the CMOS level of importing is carried out level conversion, its output Q, Q output LVDS Low Voltage Differential Signal Q
L, Q
L, be a string line output pattern.This CMOS-LVDS level converter circuit is by three CMOS inverters, a cmos transmission gate, differential amplifier, level conversion unit and biasing circuit are formed by connecting, cascade between three CMOS inverters, second level CMOS inverter output is connected with the cmos transmission gate input, CMOS-LVDS level translator input is located on the first order CMOS inverter gate, CMOS-LVDS level translator output is located on the level conversion unit, level CMOS inverter and cmos transmission gate output and differential amplifier not, the level conversion unit input connects, and transmits the CMOS level signal to it.Its structure such as Fig. 1, shown in Figure 7.Its specification requirement should be satisfied the requirement of general low-voltage differential signal (LVDS).
CMOS inverter of the present invention, not gate, cmos transmission gate, CMOS D type master-slave flip-flop, differential amplifier, level conversion unit, biasing circuit are general basic circuit, connect and compose by PMOS and NMOS pipe, the effective PM1 of PMOS in Fig. 3, PM2, PM3 and the effective NM1 of NMOS, NM2, NM3 indicate, PMOS pipe and NMOS pipe among other figure are all only drawn with its general symbol(s), do not indicate.
The work schedule waveform of Qatput mode circuit of the present invention as shown in Figure 9, operation principle is as follows:
1) LVDS pattern operation principle
Input control level M
2Be low level, two-way distributor DMUX selects its OUT1 output, with data D
MBe input to the CMOS-LVDS level translator, the CMOS level signal is converted to the output of LVDS data, dateout is the serial output form.
2) CMOS alternate mode operation principle
Input control level M
1Be high level, the output Q1 of output timing control circuit is opposite with the Q2 phase place.The output of ÷ 2 frequency dividers was converted to low level by high level when the rising edge of the 1st clock reached, N data input trigger F1 of M position between this low period, the 1st the clock cycle output of the 2nd clock period ÷ 2 frequency dividers later is high level by low transition, blocked the data input of trigger F1, trigger F1 exports N data between this high period, simultaneously with N data input trigger F2, N+1 data input trigger F4.The 2nd clock cycle the 3rd clock period ÷ 2 frequency dividers output later is converted to low level by high level, trigger F2 exports N data between this low period, trigger F4 exports N+1 data, and simultaneously with N data input trigger F3, and trigger F1 imports N+2 data.The 3rd clock cycle the 4th clock period ÷ 2 frequency dividers output later is high level by low transition, trigger F3 exports N data between this high period, trigger F5 imports N+1 data, trigger F1 exports N+2 data, and with this data input trigger F2, trigger F4 imports N+3 data.The 4th clock cycle the 5th clock period ÷ 2 frequency dividers output later is converted to low level by high level, trigger F3 output keeps N data between this low period, trigger F5 exports N+1 data, and trigger F2 exports the N+2 data, and trigger F4 exports N+3 data.So circulate, trigger F3 dateout is that N is individual, N+2 is individual, N+4 is individual ..., trigger F5 dateout is N+1, N+3 is individual, N+5 is individual ..., trigger F5 delays a clock cycle dateout than trigger F3.Therefore, one group of serial data of input is converted to alternately output of trigger F3 and trigger F5, and output data rate is 1/2nd of input data rate, and promptly the dateout width is 2 times of input, thereby makes output data rate reduce by one times.
3) CMOS parallel schema operation principle
Input control level M
1Be low level, the output Q1 of output timing control circuit is identical with the Q2 phase place.Operation principle and CMOS alternate mode are basic identical, just trigger F3 and trigger F5 are same clock input and output data, promptly begin dateout in the 3rd clock cycle later the 4th clock period trigger F3 and trigger F5, trigger F3 dateout is that N is individual, N+2 is individual, N+4 is individual ..., trigger F5 dateout is N+1, N+3 is individual, N+5 is individual ....One group of serial data of input is converted to trigger F3 and trigger F5 and line output, and output data rate is 1/2nd of input data rate, and promptly the dateout width is 2 times of input, thereby makes output data rate reduce by one times.
Fig. 8 is used to have the circuit connection diagram of the high-speed a/d converter of M bit data output for Qatput mode circuit of the present invention, and high-speed a/d converter is with the data input D of Qatput mode circuit
1, D
2D
MRespectively with the inner encoded and latches of M position high-speed a/d converter after bits per inch according to output D
1, D
2D
MJoin, the input end of clock CLK of its Qatput mode circuit (CLOCK abbreviation) provides the clock CLOCK of latch to link to each other with high-speed a/d converter inside, and all high-speed a/d converters are imported M with the control of Qatput mode circuit
1And M
2Correspondence connects together, each high-speed a/d converter with the output of Qatput mode circuit as the final bits per inch of high-speed a/d converter according to output.Q among the figure
A1, Q
B1, Q
L1, Q
L1Be respectively the 1st (lowest order) CMOS parallel or the alternate data output and the output of LVDS data of high-speed a/d converter, Q
A2, Q
B2, Q
L2, Q
L2Be respectively the 2nd CMOS parallel or the alternate data output and the output of LVDS data of high-speed a/d converter, Q
AM, Q
BM, Q
LM, Q
LMBe respectively M position (highest order) CMOS parallel or the alternate data output and the output of LVDS data of high-speed a/d converter.
V in the accompanying drawing of the present invention
DDBe supply voltage, V
BBBe bias voltage, its value is 1.125～1.375V, is provided by reference power supply, and R, R1 are resistance.
The present invention adopts the CMOS technology manufacturing of standard.
Claims (7)
1. high-speed a/d converter Qatput mode circuit is characterized in that it comprises:
A two-way distributor has a data input pin, a control level input and two data outputs, by the height of input control level to from the one digit number of A/D converter inside according to selecting its data output end;
÷ 2 frequency dividers carry out ÷ 2 frequency divisions to the clock signal of input, and output frequency is the clock signal of input clock frequency 1/2nd;
Not gate for CMOS inverter formation, its input is connected with the output of ÷ 2 frequency dividers, carries out anti-phase to the clock signal of input;
An output timing control circuit, its input end of clock is connected with the output of ÷ 2 frequency dividers, and the clock signal of input is carried out the sequential conversion, is controlled the phase relation of two outputs by the height of input control level;
One by five D type master-slave flip-flop F1, F2, F3, F4, CMOS that F5 is linked to be and line output and CMOS replace output circuit, be divided into two groups, the data output end of the D type master-slave flip-flop of previous stage is connected with the data input pin of back one-level D type master-slave flip-flop in every group, the data input pin of every group first order D type master-slave flip-flop is connected with arbitrary data output end of two-way distributor, the input end of clock of 5 D type master-slave flip-flops respectively with ÷ 2 frequency dividers, not gate, the output of output timing control circuit connects, data to input under the clock effect are shifted, output CMOS parallel data or CMOS alternate data;
A CMOS-LVDS level translator is connected with arbitrary data output end of two-way distributor, and the CMOS level of importing is carried out level conversion, output Low Voltage Differential Signal LVDS.
2. high-speed a/d converter Qatput mode circuit according to claim 1, it is characterized in that described two-way distributor circuit is formed by connecting by two cmos transmission gates and a CMOS inverter, its data input pin and two data output ends are located on the cmos transmission gate, its control level input one tunnel directly is connected with one group of grid of two cmos transmission gates, and the CMOS inverter of leading up to is connected with another group grid of two cmos transmission gates.
3. high-speed a/d converter Qatput mode circuit according to claim 1, it is identical to it is characterized in that described formation CMOS and line output and CMOS replace the circuit structure of five D type master-slave flip-flops of output circuit, the circuit of its each D type master-slave flip-flop constitutes by connect two CMOS inverters in the output of general CMOS D type master-slave flip-flop, cascade between two CMOS inverters is not established the data output end of D type master-slave flip-flop on the level CMOS inverter.
4. high-speed a/d converter Qatput mode circuit according to claim 1, it is characterized in that described ÷ 2 divider circuits constitute by connect three grades of CMOS inverters in the output of general CMOS D type master-slave flip-flop, the output of an one CMOS inverter is connected with the data input pin of general CMOS D type master-slave flip-flop, behind other two CMOS inverter cascades as the output of ÷ 2 frequency dividers.
5. high-speed a/d converter Qatput mode circuit according to claim 1, it is characterized in that described output timing control circuit comprises three not gates that three CMOS inverters form, a two-way selector, respectively by six CMOS inverters is connected identical with structure of cmos transmission gate and constitute two groups drive delay circuits, after one of them not gate is anti-phase, be divided into three tunnel outputs from the clock signal of ÷ 2 frequency dividers of its input end of clock input, one the tunnel is anti-phase after cmos transmission gate is passed to connected one group of driving delay circuit by a not gate, form one of output of output timing control circuit, one the tunnel directly is connected with an input of two-way selector, one the tunnel is connected with this two-way selector one input after a not gate is anti-phase, the two-way selector is provided with the control level input, height by the input control level is selected this two input, the two-way selector output end is connected with one group of driving delay circuit, forms one of output of output timing control circuit.
6. high-speed a/d converter Qatput mode circuit according to claim 5, it is characterized in that described two-way selector circuit is formed by connecting by two cmos transmission gates and a CMOS inverter, two cmos transmission gate inputs are respectively two inputs of two-way selector, the output of two cmos transmission gates is the output of two-way selector, control level input one tunnel directly is connected with one group of grid of two cmos transmission gates, and one the tunnel is connected with another group grid of two cmos transmission gates after the CMOS inverter is anti-phase.
7. high-speed a/d converter Qatput mode circuit according to claim 1, it is characterized in that described CMOS-LVDS level converter circuit is by three CMOS inverters, a cmos transmission gate, differential amplifier, level conversion unit and biasing circuit are formed by connecting, cascade between three CMOS inverters, establish CMOS level translator input on the first order CMOS inverter gate, second level CMOS inverter output is connected with the cmos transmission gate input, level CMOS inverter and cmos transmission gate output and differential amplifier not, the level conversion unit input connects, and establishes CMOS-LVDS level translator output on the level conversion unit.
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| CNB2006100542227A CN100435484C (en) | 2006-04-18 | 2006-04-18 | Qatput mode circuit of high speed A/D converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100542227A CN100435484C (en) | 2006-04-18 | 2006-04-18 | Qatput mode circuit of high speed A/D converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1859011A CN1859011A (en) | 2006-11-08 |
| CN100435484C true CN100435484C (en) | 2008-11-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100542227A Expired - Fee Related CN100435484C (en) | 2006-04-18 | 2006-04-18 | Qatput mode circuit of high speed A/D converter |
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| Country | Link |
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| CN (1) | CN100435484C (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5036219A (en) * | 1989-05-31 | 1991-07-30 | Harris Corporation | Precise, high speed CMOS track (sample)/hold circuits |
| CN1232321A (en) * | 1998-04-13 | 1999-10-20 | 中国科学院半导体研究所 | High speed and high-accuracy A/D converter |
-
2006
- 2006-04-18 CN CNB2006100542227A patent/CN100435484C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5036219A (en) * | 1989-05-31 | 1991-07-30 | Harris Corporation | Precise, high speed CMOS track (sample)/hold circuits |
| CN1232321A (en) * | 1998-04-13 | 1999-10-20 | 中国科学院半导体研究所 | High speed and high-accuracy A/D converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1859011A (en) | 2006-11-08 |
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