CN100430901C - BIOS debug method assisted by CMOS memory - Google Patents

BIOS debug method assisted by CMOS memory Download PDF

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Publication number
CN100430901C
CN100430901C CNB2005101376639A CN200510137663A CN100430901C CN 100430901 C CN100430901 C CN 100430901C CN B2005101376639 A CNB2005101376639 A CN B2005101376639A CN 200510137663 A CN200510137663 A CN 200510137663A CN 100430901 C CN100430901 C CN 100430901C
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bios
cmos
motherboard
error code
debug
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CN1996260A (en
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柯建兴
萧家一
林忠建
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Jiaxing Jinxu Medical Technology Co., Ltd.
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Inventec Corp
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Abstract

An error elimination method based on CMOS memory assistance for the BIOS, uses the CMOS storing on the main board the error clearing code generated by the, referring to a battery of the main board to maintain the power supply for storable document, extracting last stored error clearing code when the testing staff turns the machine again, avoiding the disappearance of error clearing code due to abnormal shut down off the machine.

Description

Method with the auxiliary BIOS debug of CMOS memory body
Technical field
The present invention relates to the method for a kind of auxiliary Basic Input or Output System (BIOS) (BIOS) debug, particularly relate to a kind of auxiliary BIOS Debug Card of complementary metal oxide semiconductor (CMOS) (Complementary Metal-OxideSemiconductor Random Access Memory) memory body that utilizes to apply to the method with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body of BIOS debug.
Background technology
In existing known skill, BIOS development most common form promptly is a BIOS Debug Card to be assigned on motherboard remove error code to show, if test period generation problem, the research staff can may originate the core place of further tracing with what understand problem by removing error code.
See also shown in Figure 1ly, it is the process flow diagram of previous BIOS debug, and it may further comprise the steps:
One motherboard (step S101) is provided, and its motherboard has a memory cell, and this memory cell is to be the erasable memory body of a programmable, as: the erasable ROM (Electrically﹠amp that stylizes of an electronics; Erasable Programmable Read Only Memory; EEPROM) or an erasable ROM that stylizes (Erasable Programmable Read Only Memory; EPROM);
One BIOS Debug Card is provided, assigns on motherboard (step S102), its BIOS Debug Card has a display unit and a test BIOS, can write the memory cell of motherboard after start; And
Carry out a start-up phase job and show and remove error code (step S103), write the test usefulness BIOS to memory cell, the BIOS that is written into memory cell can export one and remove error code to BIOS Debug Card and show with display unit, and carry out with except that the corresponding start-up phase work of error code, make the tester understand present test case.
Judge whether to finish start-up phase work (step S104), if yes, then finish BIOS debug work (step S105), if not, then get back to the start-up phase work of execution and show and remove error code step (step S103), so that repeat to show the pairing error code of removing of start-up phase work of mistake, make the tester understand the problem place.
But, if unusual condition takes place when carrying out start-up phase work, as: when machine so that need manually start again, automatically shutdown or situation generation such as start again automatically, can be eliminated and can't make the tester know that wrong source can't understand the key point of its problem to such an extent as to remove error code, and then increase the complexity of BIOS debug flow process.
This shows that the method for above-mentioned existing Basic Input or Output System (BIOS) (BIOS) debug obviously still has inconvenience and defective, and demands urgently further being improved in method and use.The problem that exists for the method that solves Basic Input or Output System (BIOS) (BIOS) debug, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and conventional method does not have appropriate method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new method, just become the current industry utmost point to need improved target with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body.
Because the defective that the method for above-mentioned existing Basic Input or Output System (BIOS) (BIOS) debug exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new method with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, can improve the method for general existing Basic Input or Output System (BIOS) (BIOS) debug, make it have more practicality.Through constantly research, design, and after studying repeatedly and improving, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome the defective of the method existence of existing Basic Input or Output System (BIOS) (BIOS) debug, and a kind of new method with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body is provided, technical matters to be solved is that it can be avoided among BIOS debug flow process, remove error code because of unusual when machine so that need manually start again, automatically shutdown or automatically again situation such as start disappear, and then make the tester can't obtain last time debug flow process except that error code.Whether operate complete for last time starting shooting, whether BIOS can detect start and finish bit and be set when each start, in order to judge whether start last time operates complete, if last time the start running was imperfect, BIOS can deposit the numerical value of instantaneous code field in the error code field, and after start is finished, export the storage values of error code field to the BIOS Debug Card and show with display unit, the problem place of abnormal conditions takes place in start so that the tester can further understand last time, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.Method according to the present invention's proposition with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, it may further comprise the steps: a motherboard with a CMOS memory body is provided, at least comprise an instantaneous code field in this CMOS memory body, bit is finished in an error code field and a start; One BIOS Debug Card is provided, assign on this motherboard, it has a test BIOS, and a memory cell that writes this motherboard when start forms a motherboard BIOS, it is in order to circuit and this CMOS memory body of access of main control system plate, and a display unit; Check that this start finishes bit and whether set, it makes this motherboard BIOS judge last time whether start was finished, if not, this motherboard BIOS can be stored in the numerical value of this instantaneous code field and then remove this start in this error code field and finish bit, if this motherboard BIOS will directly remove this start and finish bit; Store one and remove error code and carry out a start-up phase job, this motherboard BIOS can store this and remove error code in this instantaneous code field, then carries out this start-up phase work; Judge whether to finish this start-up phase work, if not, then carry out this storage remove error code in instantaneous code field step with the numerical value that shows this error code field, numerical value to this BIOS Debug Card that this motherboard BIOS can export this error code field shows with this display unit, if then this motherboard BIOS sets this start and finishes bit.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid method with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, wherein said CMOS memory body is to be a complementary metal oxide semiconductor (CMOS) random access memory (Complementary Metal-Oxide Semiconductor RandomAccess Memory, CMOS RAM).
Aforesaid method with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, wherein said memory cell is the ROM (Electrically﹠amp that stylizes for an electronics is erasable; Erasable Programmable Read Only Memory; EEPROM) or an erasable ROM that stylizes (Erasable Programmable Read Only Memory; EPROM).
Aforesaid method with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, wherein said storage one removes error code and carries out a start-up phase job step and comprises the following steps: that more this motherboard BIOS can this remove error code in this instantaneous code field in storage, should remove error code and export this BIOS Debug Card to this display unit demonstration.
Aforesaid method with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, wherein said display unit is to be a liquid crystal screen or a seven-segment display.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, major technique of the present invention thes contents are as follows:
Based on above-mentioned purpose, the invention provides a kind of method with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, provide a motherboard and a BIOS Debug Card, this motherboard has a memory cell, it is the erasable memory body of a programmable, an and CMOS memory body, it has an instantaneous code field, bit is finished in one an error code field and a start, and the CMOS memory body is to be a complementary metal oxide semiconductor (CMOS) random access memory (CMOS RAM), its utilize motherboard a powered battery so that its shutdown in still can store data, again a BIOS Debug Card is assigned on motherboard, its BIOS Debug Card has a display unit and a test BIOS, the memory cell that this test can the time write motherboard earlier in start with BIOS is to form a motherboard BIOS, and it is in order to the circuit and the access CMOS memory body of main control system plate.
Motherboard BIOS is carrying out can carrying out a start-up phase job among the debug process, and one of corresponding start-up phase work is removed error code before carrying out start-up phase work, be stored in the instantaneous code field and export the BIOS Debug Card to and show that with display unit it removes error code, make the tester understand the start-up phase work of now being carried out, and after start-up phase work is finished, set start and finish bit, there is no abnormal conditions and take place with expression start running normal termination.If when start-up phase work generation unusual condition such as BIOS data design mistake, then start is finished bit and can be set with the expression not entire run of starting shooting, and can repeat to show corresponding with it except that error code.Yet, even if take place relatively serious situation as when machine so that need manually start again, unusual automatic shutdown or situation such as start again automatically, because of utilizing the data storage characteristic of CMOS memory body, except that error code can not disappear along with shutdown.
No matter last time whether start operated complete, whether BIOS can detect start and finish bit and be set during each start, it is in order to judge whether start last time operates complete, if last time the start running was imperfect, BIOS can deposit the numerical value of instantaneous code field in the error code field, and after start is finished, export the storage values of error code field to the BIOS Debug Card and show with display unit, so that the tester can further understand the problem place that abnormal conditions take place in last time start.
Via as can be known above-mentioned, the invention relates to a kind of method with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, be utilize one be arranged on a CMOS memory body on the motherboard store produced in the BIOS debug flow process one remove error code, an and battery that the utilizes motherboard power supply of keeping the CMOS memory body characteristic that it still can be stored data when shutdown, make the tester when starting shooting once more, still can obtain last time the finally stored error code of removing during the start from the CMOS memory body, the error code of removing of avoiding BIOS debug flow process to be produced disappears because of unusual shutdown, make the tester can't understand problematic source, and then increase the complexity of debug.
By technique scheme, the present invention has following advantage at least with the method for auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body:
The characteristic that the present invention utilizes this CMOS memory body still can store data in shutdown, even there is abnormal automatic shutdown situation to take place in the BIOS debug flow process, therefore the data that is stored in the CMOS memory body can not disappear, the tester can obtain last time the error code of removing of start starting shooting once more via the CMOS memory body, significantly reduce the complexity of BIOS debug.
In sum, the method that the present invention is special with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, it has above-mentioned many advantages and practical value, and in class methods, do not see have similar design to publish or use and really genus innovation, no matter it is all having bigger improvement on method or on the function, have large improvement technically, and produced handy and practical effect, and the method for more existing Basic Input or Output System (BIOS) (BIOS) debug has the multinomial effect of enhancement, thereby being suitable for practicality more, really is a novelty, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the process flow diagram of previous BIOS debug.
Fig. 2 is the synoptic diagram that concerns for BIOS Debug Card of the present invention and CMOS memory body.
Fig. 3 is the process flow diagram of BIOS debug of the present invention.
The 100:BIOS Debug Card
110: test BIOS
120: display unit
200: motherboard
210: memory cell
The 220:CMOS memory body
221: the instantaneous code field
222: the error code field
223: bit is finished in start
Step S101 a: motherboard is provided
Step S102: a BIOS Debug Card is provided, assigns on motherboard
Step S103: carry out a start-up phase job and show and remove error code
Step S104: judge whether to finish start-up phase work
Step S105: finish BIOS debug work
Step S301 a: motherboard with a CMOS memory body is provided
Step S302: a BIOS Debug Card is provided, assigns on motherboard
Step S303: whether the inspection start is finished bit and is set
Step S304: the numerical value of instantaneous code field is stored in the error code field
Step S305: remove start and finish bit
Step S306: store one and remove error code and carry out a start-up phase job
Step S307: judge whether to finish start-up phase work
Step S308: set start and finish bit
Step S309: the numerical value that shows the error code field
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of method, method, step, feature and the effect thereof that foundation the present invention proposes with auxiliary Basic Input or Output System (BIOS) (BIOS) debug of complementary metal oxide semiconductor (CMOS) (CMOS) memory body, describe in detail as after.
See also shown in Figure 2, it is the synoptic diagram that concerns of BIOS Debug Card of the present invention and CMOS memory body, it comprises a motherboard 200, it has a CMOS memory body 220 and a memory cell 210, this CMOS memory body has an instantaneous code field 221, remove error code in order in BIOS debug flow process, to store one, bit 223 is finished in one start, last time whether start was successful in order to judgement in BIOS debug flow process, and an error code field 222, a numerical value of storage instantaneous code field when last time start is unsuccessful; And a BIOS Debug Card 100, this BIOS Debug Card 100 is assigned on motherboard 200, and it comprises a test with a BIOS110 and a display unit 120, and it removes error code in order to show.
Wherein, test can write memory cell 210 earlier with BIOS110 when the debug flow process begins, circuit and access CMOS memory body 220 with main control system plate 200, this CMOS memory body 220 is to be a complementary metal oxide semiconductor (CMOS) random access memory (Complementary Metal-OxideSemiconductor Random Access Memory, CMOS RAM), it is to utilize a powered battery of motherboard 200 to keep an a small amount of memory cell of data storage; And memory cell 210 is to be the erasable ROM that stylizes of an electronics (Electrically﹠amp; ErasableProgrammable Read Only Memory, EEPROM) or an erasable ROM that stylizes (Erasable Programmable Read Only Memory, EPROM), and display unit be to be a liquid crystal screen or seven-segment display.
See also shown in Figure 3ly, it is to be BIOS debug process flow diagram of the present invention, and it may further comprise the steps:
One motherboard (step S301) with a CMOS memory body is provided, provide a motherboard 200, it has a CMOS memory body 220, and this CMOS memory body 220 has a plurality of data fields, at least comprise that an instantaneous code field 221, one error code fields 222 and a start finish bit 223.
One BIOS Debug Card is provided, assign on motherboard (step S302), one BIOS Debug Card 100 is assigned on motherboard 200, this BIOS Debug Card 100 has a display unit 120 and a test BIOS110, this test can write memory cell 210 earlier to form a motherboard BIOS, in order to the circuit and the access CMOS memory body 220 of main control system plate 200 with the data of BIOS110.
The inspection start is finished bit and whether is set (step S303), motherboard BIOS can be via checking that setting that bit is finished in start whether, judge last time whether start was finished, if not, be that motherboard BIOS can be stored in the numerical value of instantaneous code field 221 in the error code field 222 (step S304) and then removes start and finish bit (step S305), if yes, then motherboard BIOS directly removes start and finishes bit (step S305).
Storing one removes error code and carries out a start-up phase job (step S306), motherboard BIOS can carry out start-up phase work earlier, and before its start-up phase work is carried out, what store corresponding start-up phase work earlier removes error code in instantaneous code field 221, exports BIOS Debug Card 100 simultaneously to and shows that with display unit 120 it removes error code.
Judge whether to finish start-up phase work (step S307), after finishing start-up phase work, motherboard BIOS can judge the end of run that start-up phase work is whether complete; If not, then store one and remove error code and carry out a start-up phase job step (step S306), show the pairing error code of removing of wrong start-up phase work, make the tester understand the problem place; If yes, then set start and finish bit (step S308), then do not had the generation mistake by complete operation with the work of expression start-up phase.
At last, the numerical value (step S309) that shows the error code field, the numerical value of motherboard BIOS meeting output error sign indicating number field 222 is to BIOS Debug Card 100, and with display unit 120 demonstrations, the numerical value of this error code field 222 is last time boot failure or finally stored except that error code when machine.
From the above, the tester can directly obtain except that error code from the display unit of BIOS Debug Card in BIOS debug flow process immediately, even in the debug flow process, take place unusual when machine or shutdown automatically, the characteristic that still can utilize the CMOS memory body to store data obtains the finally stored error code of removing when last time starting shooting after starting shooting once more, make the tester know the place that unusual condition takes place, and then trace the place, source of problem.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.

Claims (5)

1, a kind of method with the auxiliary Basic Input or Output System (BIOS) debug of complementary metal oxide semiconductor (CMOS) memory body is characterized in that it may further comprise the steps:
One motherboard with a CMOS memory body is provided, comprises an instantaneous code field in this CMOS memory body at least, bit is finished in an error code field and a start;
One BIOS Debug Card is provided, assign on this motherboard, it has a test BIOS, and a memory cell that writes this motherboard when start forms a motherboard BIOS, it is in order to circuit and this CMOS memory body of access of main control system plate, and a display unit;
Check that this start finishes bit and whether set, it makes this motherboard BIOS judge last time whether start was finished, if not, this motherboard BIOS can be stored in the numerical value of this instantaneous code field and then remove this start in this error code field and finish bit, if this motherboard BIOS will directly remove this start and finish bit;
Store one and remove error code and carry out a start-up phase job, this motherboard BIOS can store this and remove error code in this instantaneous code field, then carries out this start-up phase work; And
Judge whether to finish this start-up phase work, if not, then carry out this storage and remove error code in instantaneous code field step and the numerical value that shows this error code field, numerical value to this BIOS Debug Card that this motherboard BIOS can export this error code field shows with this display unit, if then this motherboard BIOS sets this start and finishes bit.
2, the method with the auxiliary Basic Input or Output System (BIOS) debug of complementary metal oxide semiconductor (CMOS) memory body according to claim 1 is characterized in that wherein said CMOS memory body is to be a complementary metal oxide semiconductor (CMOS) random access memory.
3, the method with the auxiliary Basic Input or Output System (BIOS) debug of complementary metal oxide semiconductor (CMOS) memory body according to claim 1 is characterized in that wherein said memory cell is stylize for an electronics is erasable a ROM or an erasable ROM that stylizes.
4, the method with the auxiliary Basic Input or Output System (BIOS) debug of complementary metal oxide semiconductor (CMOS) memory body according to claim 1 is characterized in that wherein said storage one removes error code and carries out a start-up phase job step more to comprise the following steps:
This motherboard BIOS can this remove error code in this instantaneous code field in storage, should remove error code and export this BIOS Debug Card to this display unit demonstration.
5, the method with the auxiliary Basic Input or Output System (BIOS) debug of complementary metal oxide semiconductor (CMOS) memory body according to claim 1 is characterized in that wherein said display unit is to be a liquid crystal screen or a seven-segment display.
CNB2005101376639A 2005-12-31 2005-12-31 BIOS debug method assisted by CMOS memory Expired - Fee Related CN100430901C (en)

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US8312256B2 (en) 2010-02-24 2012-11-13 Hewlett-Packard Development Company, L.P. Display of a basic input/output system (BIOS) productivity display
TWI470420B (en) * 2011-04-27 2015-01-21 Wistron Corp Dubugging method and computer system using the smae

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1368677A (en) * 2001-02-01 2002-09-11 宏碁电脑股份有限公司 Information processing system with debug function on initializing and its method
US20020169997A1 (en) * 2001-02-01 2002-11-14 Song-Bor Chen BIOS debug method
CN1455342A (en) * 2003-05-23 2003-11-12 威盛电子股份有限公司 Method of setting BIOS of CMOS for back-up computer system on DMI segment
CN1506821A (en) * 2002-12-11 2004-06-23 联想(北京)有限公司 Detection and display method and device for computer self-test information
US20050039081A1 (en) * 2003-05-20 2005-02-17 Wei-Han Chang Method of backing up BIOS settings

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1368677A (en) * 2001-02-01 2002-09-11 宏碁电脑股份有限公司 Information processing system with debug function on initializing and its method
US20020169997A1 (en) * 2001-02-01 2002-11-14 Song-Bor Chen BIOS debug method
CN1506821A (en) * 2002-12-11 2004-06-23 联想(北京)有限公司 Detection and display method and device for computer self-test information
US20050039081A1 (en) * 2003-05-20 2005-02-17 Wei-Han Chang Method of backing up BIOS settings
CN1455342A (en) * 2003-05-23 2003-11-12 威盛电子股份有限公司 Method of setting BIOS of CMOS for back-up computer system on DMI segment

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