CN100424998C - Single-bit error correction and form-checking method based on CRC and its circuit - Google Patents
Single-bit error correction and form-checking method based on CRC and its circuit Download PDFInfo
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Abstract
The present invention relates to a single-bit error correcting and table looking-up method based on cyclic redundancy codes and a circuit of the method, which belong to the technical field of digital communication. Cyclic redundancy codes of a data segment are checked to obtain a row vector. If the row vector is not zero, p-pit elements are extracted from the row vector according to a subspace to obtain a row vector Rp, and the rest part forms a row vector Rq. The row vector Rp is used as address information, and matching information corresponding to the address and single-bit error position information are obtained from a lookup table. A single-bit error correction indication is obtained according to the coincident state of the matching information and the row vector Rq, and single-bit error correction is carried out. The circuit of the present invention comprises a checker, a selector, a memory comparer and a single-bit error corrector. The method and the circuit of the present invention have the advantages that address information is controlled optimally, an address space occupied by the lookup table is reduced, the capacitance of a memory unit is decreased, the information of the lookup table is easy to display, the circuit is easy to realize, the integral circuit module is clear, the structure is regular, the execution speed is high, and the present invention is easy to integrate.
Description
Technical field
The present invention relates to a kind of monobit errro correction look-up method and circuit thereof, belong to digital communication technology field based on cyclic redundancy code.
Background technology
Cyclic redundancy code (hereinafter to be referred as CRC) calibration technology, because its realization is simple, efficient, the resource that takies software or hardware is few, has obtained using widely in the error-detection error-correction field of digital communication.At present, the most widely used CRC check of digital communicating field mainly is that generator polynomial is x in the world
16+ x
12+ x
5+ 1 CRC-16 and x
32+ x
26+ x
23+ x
22+
X16+X
12+ x
11+ x
10+ x
8+ x
7+ x
5+ x
4+ x
2The CRC-32 of+x+1.In existing most communication systems, the CRC part just realizes often not carrying out correction process by simple error detection function usually.Utilized the monobit errro correction ability of CRC in some communication systems, realized recovery, increased the reliability of communication the single-bit error of critical field.
Typical application of CRC check is in Generic Framing Procedure (being called for short GFP) agreement.This agreement is indicated (being called for short PLI) in payload length, the payload type zone, and it is x that three critical fielies such as expansion type zone have all adopted generator polynomial
16+ x
12+ x
5The error detection of+1 CRC-16 and monobit errro correction.The information field length of this CRC protection is 16 bits, and check digit own is 16 bits, and therefore total data segment, length is 32 bits.At the receiving terminal of GFP, need to correct the single-bit error of the shielded information field of preceding 16 bits of this data segment, the single-bit error of back 16 bit check digit is not needed correction.
CRC monobit errro correction method normally adopts look-up table, every kind of corresponding unique verification pattern of error pattern that single-bit error occurs.Therefore, utilize the message part and the CRC check part that receive, carry out CRC again at receiving terminal and calculate, judge whether wrong; If single-bit error is arranged, utilize the result of calculation of CRC to table look-up and to determine the position that this is wrong.No matter this method is to realize with software or hardware, all compares standard and simple on the algorithm, is easy to integrated and multiplexing.But, the core technology of error correction method is the generation of verification pattern look-up table because single-bit is tabled look-up, and existing various algorithm is relatively more random in the generation of look-up table, utilized some particularity or self-defining pre-computation to generate look-up table, therefore each algorithm is very big to the utilization variance of resource, some algorithms are wherein realized comparatively complexity simultaneously, and are higher to the circuit requirement except that the look-up table part.
Look-up table takies the size of resource, depends primarily on the size of address space; Whether the outer complex circuit designs degree of look-up table part, it is simple, regular to depend primarily on structure.Utilize some features of CRC check itself, can carry out optimality analysis, a kind ofly look-up table is taken up room minimize, make simple method for designing of overall structure and circuit simultaneously thereby find to the size of address space.Therefore the information field of supposing CRC check is k bits, and the CRC check field is n-k bits, and the data segment length overall that sends is the n bit, can represent with multinomial v (x) (its high reps be n-1).The error pattern of introducing in the transmission course can remember and be e (x) (high reps be n-1) that nonzero term is wherein represented the position that mistake takes place.So, the multinomial that receives is r (x)=v (x)+e (x).The multinomial that receives is carried out the computing of the CRC identical with transmitting terminal again, following result is arranged:
CRC (r (x))=CRC (v (x)+e (x))=CRC (v (x))+CRC (e (x))=Constant+CRC (e (x)), the addition in the equation is a modular two addition.CRC wherein (v (x)) is no matter why the v (x) that sends is worth, and the result is a constant sequence, and this constant is zero in most CRC check.Therefore, the pattern of the r that receives (x) after the CRC computing depends on the CRC operation result of the error pattern in the transport process.Utilize this conclusion, we can carry out optimized analysis and design to look-up table with more efficiently method, generate the core look-up table of monobit errro correction with minimum address space.
Summary of the invention
The objective of the invention is to propose a kind of monobit errro correction look-up method and circuit thereof based on cyclic redundancy code, based on the common thought of tabling look-up, pass through optimization procedure, realize the core look-up table of monobit errro correction with as far as possible little address space, reduce taking greatly to resource, make the overall structure of circuit more effective and regular simultaneously, to be more suitable for the integrated and multiplexing of intellectual property in the application-specific integrated circuit (ASIC) (being called for short ASIC) (abbreviation IP) nuclear.
The monobit errro correction look-up method based on cyclic redundancy code that the present invention proposes comprises the steps:
(1) be that the data segment of n bit carries out that the check digit position is long to be the CRC of m to the length that receives, obtain the check results that length is the m bit, if wherein the highest check digit corresponding sequence number is 1, minimum check digit corresponding sequence number is m, from 1 to m check digit sequence number, extract subspace I, I=i
1, i
2, i
3..., i
p, wherein 1≤p≤m, and i
1, i
2, i
3..., i
p∈ 1,2 ..., m};
(2) set up the look-up table T that address information and content information shine upon one by one;
(3) data segment that is the n bit with the above-mentioned length that receives carries out that the check digit position is long to be the CRC of m, obtain with the 1 * m capable vector R of bit as basic element, if this row vector R is a null vector, then the data of Jie Shouing are correct, if non-vanishing, then carry out following steps;
(4) from above line vector R, extract the p bit elements, obtain the vectorial R of row of 1 * p by subspace I
p, remainder constitutes the vectorial R of row of 1 * q
q
(5) with above line vector R
pAs an address information to be found from above-mentioned look-up table T, according to this address information, obtain and the corresponding content information in this address, before this content information comprises the match information of q bit and after
The single-bit error positional information of bit;
(6) match information of q bit and above line vector R before above-mentioned
qWhen matching, if carry out the monobit errro correction of information bit and check digit, then export the monobit errro correction indication, if only carry out the monobit errro correction of information bit, then when the highest order of above-mentioned single-bit error positional information is " 1 ", the indication of output monobit errro correction during for " 0 ", is not exported the monobit errro correction indication; The match information of q bit and above line vector R before above-mentioned
qWhen misfitting, finish error correction procedure;
(7) according to the indication of above-mentioned single-bit error positional information and above-mentioned monobit errro correction, to the bit that is in errors present carry out inversion operation or with " 1 " XOR, carry out monobit errro correction;
(8) error correction that all receive data segment is finished in repeating step (3)～(7).
In the said method, from 1 to m check digit sequence number, extract the process of subspace I, may further comprise the steps:
(1) all the single-bit error pattern e (x) in the data transmission procedure is carried out respectively the check digit position is long to be the CRC of m, obtain the check results of single-bit error pattern respectively, the length of check results is respectively the m bit, with all check results by rows, with the basic element of bit as matrix, the corresponding sequence number of the highest check digit is 1, the corresponding sequence number of minimum check digit is m, with the sequence number of check digit as matrix column number, constitute the check matrix A of a n * m, wherein n is the length of single-bit error pattern e (x);
(2) element number of establishing subspace I to be extracted is p, and the initial value of getting p is
(3) from above-mentioned matrix A, get the p row arbitrarily, constitute n * p matrix, total C
m pPlant the matrix combination, to C
MpThe combination of kind of matrix travels through search, and until finding any two provisional capitals matrix inequality, each in this matrix is listed in the element value that row in the former A matrix number are subspace I; If do not find any two provisional capitals matrix inequality, then carry out step (4);
(4) the element number p to subspace I composes with new value, p=p+1, and repeating step (2) and (3) are until finding any two provisional capitals matrix inequality, to obtain subspace I.
In the said method, set up the process of the look-up table T that address information and content information shine upon one by one, may further comprise the steps:
(1) all the single-bit error pattern e (x) in the data transmission procedure is carried out respectively the check digit position is long to be the CRC of m, obtain the check results of single-bit error pattern respectively, the length of check results is respectively the m bit, with all check results by rows, with the basic element of bit as matrix, the corresponding sequence number of the highest check digit is 1, the corresponding sequence number of minimum check digit is m, with the sequence number of check digit as matrix column number, constitute the check matrix A of a n * m, wherein n is the length of single-bit error pattern e (x);
(2) from above-mentioned matrix A, with the element value among the above-mentioned subspace I as this matrix column number, extract p row bit, obtain the submatrix B of n * p, as the address information among the look-up table T, the remainder of A matrix constitutes n * q submatrix C, as the match information in the content information undetermined of look-up table T, m=p+q;
(3) according to the check results order by rows of above-mentioned single-bit error pattern, make up
Matrix D as the single-bit error positional information in the content information undetermined of look-up table T, and merges E=[C, D with above-mentioned submatrix C], constitute
Matrix E, as the content information of look-up table T;
(4) with the delegation in the above-mentioned matrix B as the address in the look-up table, among the matrix E corresponding row as and the corresponding content in this address, constitute look-up table T.
Wherein make up the process of matrix D, comprising: the size that (1) establishes matrix D is
Wherein n is for receiving the length of data segment; (2) will with above-mentioned check matrix A each the row corresponding single-bit error pattern in " 1 " residing position, the number of times that is nonzero term in e (x) multinomial is mapped to binary code, as the row in the matrix D, its row number is this single-bit error pattern pairing row number in check matrix A, is built into matrix D.The method that wherein number of times of nonzero term in e (x) multinomial is mapped to binary code is: if carry out the monobit errro correction of information bit and check digit, then the number of times with nonzero term in pairing e (x) multinomial is mapped directly to binary code; If only carry out the monobit errro correction of information bit, when " 1 " residing position was in information bit in the single-bit error pattern, the value that then the polynomial number of times of the pairing e in this position (x) is deducted behind the m was mapped to binary code, and its length is
Bit, and before this binary code, fill " 1 ", as highest order, formation length is
Binary code, when " 1 " residing position is in check digit in the single-bit error pattern, then the polynomial number of times of the pairing e in this position (x) is mapped directly to " 0 " binary code entirely.
The monobit errro correction lookup table circuit based on cyclic redundancy code that the present invention proposes comprises:
(1) the check digit position is long is the CRC device of m, and being used for the length that receives is that the data segment of n bit carries out verification, obtains the check results of m bit, is input to selector, and verifier is connected with selector;
(2) selector is used for selecting the p bit from above-mentioned check results by subspace I, is input to memory as address information, and residue q bit is input to comparator as information to be compared, and selector is connected with comparator with memory respectively;
(3) memory is used for store look-up tables T, and according to the address information of above-mentioned input, the content information in being shown accordingly, comprising the match information of q bit and
The single-bit error positional information of bit, memory is connected with comparator;
(4) comparator, whether the match information that is used for comparison foregoing information is identical with information to be compared, and to obtain the monobit errro correction indication, comparator is connected with the monobit errro correction device;
(5) monobit errro correction device is used for finishing monobit errro correction according to above-mentioned single-bit error positional information and monobit errro correction indication.
Comparator in the foregoing circuit comprises: q bit sequence comparator, whether the match information of q bit that is used for comparison foregoing information identical with information to be compared, identical output " 1 ", output inequality " 0 ", q bit sequence comparator be connected with door; Or q bit sequence comparator reaches and door, the output of above-mentioned q bit sequence comparator is directly indicated as monobit errro correction, if only carry out the monobit errro correction of information bit, then with the highest order of the output of above-mentioned q bit sequence comparator and above-mentioned single-bit error positional information with the result indicate as monobit errro correction.
Monobit errro correction device in the foregoing circuit comprises:
(1) shift unit is used for according to above-mentioned single-bit error positional information, and " 1 " is moved on to the position at errors present bit place, and other positions are " 0 ", and shift unit is connected with the XOR device;
(2) XOR device according to monobit errro correction indication, when this is designated as " 1 ", carries out xor operation with the data that receive and the output of shift unit, finishes monobit errro correction, during for " 0 ", does not carry out xor operation.
Monobit errro correction look-up method and circuit thereof that the present invention proposes based on cyclic redundancy code, the method of employing look-up table is carried out the location of single-bit error, the feature of error pattern decision operation result when on the structure of look-up table, having utilized the CRC computing, adopted optimized analytical method, what guaranteed that look-up table takes up room minimizes, and peripheric circuit structure is simple simultaneously, thereby it is as far as possible little to have realized taking resource, simple in structure, efficient, be easy to integrated error correction method and circuit.One of advantage of the present invention is in the building process of look-up table, address information is carried out optimization control, realize that its expression figure place minimizes, and has reduced the shared address space of look-up table greatly, reduced the capacity of memory cell, reduced more than 1 times than traditional method for customizing.Two of advantage is that match information and errors present information representation are simple, does not need through calculating, and information is passed through simply relatively, displacement is promptly available, has guaranteed the simple realization of circuit.Three of advantage is that the integrated circuit module is clear, compound with regular structure, and execution speed is fast, is easy to integratedly, is highly suitable for the application in the integrated circuit.
Description of drawings
Fig. 1 is the FB(flow block) of the inventive method.
Fig. 2 is the preparation method schematic diagram of the subspace I in the inventive method.
Fig. 3 is the generation method schematic diagram of the monobit errro correction look-up table T in the inventive method.
Fig. 4 is the structural representation of the monobit errro correction look-up table T in the inventive method.
Fig. 5 is the building process schematic diagram of the single-bit error positional information matrix D in the inventive method.
Fig. 6 is the mapping method of binary code in the building process of single-bit error positional information matrix D of the inventive method.
Fig. 6 (a) is used to correct information bit and check digit single-bit error, and Fig. 6 (b) is used for only correcting the information bit single-bit error.
Fig. 7 is the monobit errro correction lookup table circuit schematic diagram that the present invention proposes.
Fig. 8 is the circuit diagram of the comparator among the present invention, and wherein Fig. 8 (a) is used to correct information bit and check digit single-bit error, and Fig. 8 (b) is used for only correcting the information bit single-bit error.
Fig. 9 is the circuit diagram of the monobit errro correction device among the present invention.
Embodiment
The monobit errro correction look-up method that the present invention proposes based on cyclic redundancy code, its FB(flow block) as shown in Figure 1, be that the data segment of n bit carries out that the check digit position is long to be the CRC of m at first to the length that receives, obtain the check results that length is the m bit, if wherein the highest check digit corresponding sequence number is 1, minimum check digit corresponding sequence number is m, extracts subspace I, I=i from 1 to m check digit sequence number
1, i
2, i
3..., i
p, wherein 1≤p≤m, and i
1, i
2, i
3..., i
p∈ 1,2 ..., m}; Set up the look-up table T that address information and content information shine upon one by one; With the length that receives is that the data segment of n bit carries out that the check digit position is long to be the CRC of m, obtain with the 1 * m capable vector R of bit as basic element, if this row vector R is a null vector, then the data of Jie Shouing are correct, if non-vanishing, then carry out following steps; From the vectorial R of row, extract the p bit elements, obtain the vectorial R of row of 1 * p by subspace I
p, remainder constitutes the vectorial R of row of 1 * q
qTo go vectorial R
pAs an address information to be found from above-mentioned look-up table T, according to this address information, obtain and the corresponding content information in this address, before this content information comprises the match information of q bit and after
The single-bit error positional information of bit; The match information of current q bit and above line vector R
qWhen matching, if carry out the monobit errro correction of information bit and check digit, then export the monobit errro correction indication, if only carry out the monobit errro correction of information bit, then when the highest order of above-mentioned single-bit error positional information is " 1 ", the indication of output monobit errro correction during for " 0 ", is not exported the monobit errro correction indication; The match information of q bit and above line vector R before above-mentioned
qWhen misfitting, finish error correction procedure; According to the indication of single-bit error positional information and above-mentioned monobit errro correction, to the bit that is in errors present carry out inversion operation or with " 1 " XOR, carry out monobit errro correction; Repeat said process, finish the error correction that all receive data segment.
In the said method, from 1 to m check digit sequence number, extract the process block diagram of subspace I, as shown in Figure 2, at first all the single-bit error pattern e (x) in the data transmission procedure are carried out respectively that the check digit position is long to be the CRC of m, obtain the check results of single-bit error pattern respectively, the length of check results is respectively the m bit, with all check results by rows, with the basic element of bit as matrix, the corresponding sequence number of the highest check digit is 1, and the corresponding sequence number of minimum check digit is m, with the sequence number of check digit as matrix column number, constitute the check matrix A of a n * m, wherein n is the length of single-bit error pattern e (x); If the element number of subspace I to be extracted is p, the initial value of getting p is
From matrix A, get the p row arbitrarily, constitute n * p matrix, total C
m pPlant the matrix combination, to C
m pThe combination of kind of matrix travels through search, and until finding any two provisional capitals matrix inequality, each in this matrix is listed in the element value that row in the former A matrix number are subspace I; If do not find any two provisional capitals matrix inequality, then the element number p to subspace I composes with new value, and p=p+1 repeats said process, until finding any two provisional capitals matrix inequality, to obtain subspace I.
In the said method, the structure of the look-up table T that address information of setting up and content information shine upon one by one as shown in Figure 4, it sets up process as shown in Figure 3, at first all the single-bit error pattern e (x) in the data transmission procedure are carried out respectively that the check digit position is long to be the CRC of m, obtain the check results of single-bit error pattern respectively, the length of check results is respectively the m bit, with all check results by rows, with the basic element of bit as matrix, the corresponding sequence number of the highest check digit is 1, the corresponding sequence number of minimum check digit is m, with the sequence number of check digit as matrix column number, constitute the check matrix A of a n * m, wherein n is the length of single-bit error pattern e (x); From matrix A, with the element value among the above-mentioned subspace I as this matrix column number, extract p row bit, obtain the submatrix B of n * p, as the address information among the look-up table T, the remainder of A matrix constitutes n * q submatrix C, as the match information in the content information undetermined of look-up table T, m=p+q; Check results order by rows according to the single-bit error pattern makes up
Matrix D as the single-bit error positional information in the content information undetermined of look-up table T, and merges E=[C, D with above-mentioned submatrix C], constitute
Matrix E, as the content information of look-up table T; As the address in the look-up table, corresponding row conduct and the corresponding content in this address constitute look-up table T among the matrix E with the delegation in the matrix B.Wherein make up the process of matrix D, as shown in Figure 5, comprising: the size that (1) establishes matrix D is
Wherein n is for receiving the length of data segment; (2) will with above-mentioned check matrix A each the row corresponding single-bit error pattern in " 1 " residing position, the number of times that is nonzero term in e (x) multinomial is mapped to binary code, as the row in the matrix D, its row number is this single-bit error pattern pairing row number in check matrix A, is built into matrix D.The method that wherein number of times of nonzero term in e (x) multinomial is mapped to binary code is: if carry out the monobit errro correction of information bit and check digit, then the number of times with nonzero term in pairing e (x) multinomial is mapped directly to binary code, shown in Fig. 6 (a); If only carry out the monobit errro correction of information bit, when " 1 " residing position was in information bit in the single-bit error pattern, the value that then the polynomial number of times of the pairing e in this position (x) is deducted behind the m was mapped to binary code, and its length is
Bit, and before this binary code, fill " 1 ", as highest order, formation length is
Binary code, when " 1 " residing position is in check digit in the single-bit error pattern, then the polynomial number of times of the pairing e in this position (x) is mapped directly to " 0 " binary code entirely, shown in Fig. 6 (b).
The monobit errro correction lookup table circuit schematic diagram that the present invention proposes based on cyclic redundancy code, as shown in Figure 7, comprise: the check digit position is long to be the CRC device of m, being used for the length that receives is that the data segment of n bit carries out verification, obtain the check results of m bit, be input to selector, verifier is connected with selector; Selector is used for selecting the p bit from check results by subspace I, is input to memory as address information, and residue q bit is input to comparator as information to be compared, and selector is connected with comparator with memory respectively; Memory is used for store look-up tables T, and according to the address information of above-mentioned input, the content information in being shown accordingly, comprising the match information of q bit and
The single-bit error positional information of bit, memory is connected with comparator; Comparator, whether the match information that is used for the comparison content information is identical with information to be compared, and to obtain the monobit errro correction indication, comparator is connected with the monobit errro correction device; The monobit errro correction device is used for finishing monobit errro correction according to above-mentioned single-bit error positional information and monobit errro correction indication.
Comparator in the foregoing circuit comprises: q bit sequence comparator, and whether the match information of q bit that is used for comparison foregoing information is identical with information to be compared, identical output " 1 ", output inequality " 0 ", q bit sequence comparator be connected with door, shown in Fig. 8 (a); Or q bit sequence comparator reaches and door, this device is an option, if carry out the monobit errro correction of information bit and check digit, without this device, then the output of above-mentioned q bit sequence comparator is directly indicated as monobit errro correction, if only carry out the monobit errro correction of information bit, then with the highest order of the output of above-mentioned q bit sequence comparator and above-mentioned single-bit error positional information with the result indicate as monobit errro correction, shown in Fig. 8 (b).
Monobit errro correction device in the foregoing circuit as shown in Figure 9, comprising: shift unit, be used for according to above-mentioned single-bit error positional information, and " 1 " is moved on to the position at errors present bit place, other positions are " 0 ", shift unit is connected with the XOR device; The XOR device according to monobit errro correction indication, when this is designated as " 1 ", carries out xor operation with the data that receive and the output of shift unit, finishes monobit errro correction, during for " 0 ", does not carry out xor operation.
Monobit errro correction look-up method and circuit thereof that the present invention proposes based on CRC, core concept is by optimality analysis, subspace, all possible address under the traversal single-bit error situation, find minimum subspace, address, make up the address and represent the look-up table that figure place is as far as possible little, the operation principle of this method and circuit thereof is as follows:
The data that receive are carried out the check digit position is long to be the cyclic redundancy check (CRC) of m, obtain the check results of m bit.
If check results is a null vector, the data check of reception is correct, does not need to carry out monobit errro correction, otherwise this result is adjusted, and by optimized extraction subspace I, therefrom extracts the address information of p bit, and remainder constitutes the information to be compared of q bit.The process of optimized extraction subspace I is one of emphasis of the present invention from 1 to m check digit sequence number.This process need is considered optimized constraint, the one, the element number that the subspace is extracted in requirement is as much as possible little, and just the p value is minimum, and look-up table corresponding address space is minimized, the 2nd, the result that requirement is extracted by this subspace is unequal in twos, guarantees the uniqueness of address space.From the check matrix of a n * m, get the p row arbitrarily, constitute the matrix of n * p, total C
m pPlant combination.By adjusting the value of p, can be when p be more than or equal to certain value, in these matrix combinations of extraction, exist at least one matrix to satisfy its any two provisional capitals condition inequality.This value is exactly the last value of p, and just the subspace is in the minimum value that satisfies the p under the optimization constraints; Element value among the corresponding optimization subspace I is under this p value situation, satisfies in the set of matrices inequality of any two provisional capitals, and each in a certain matrix is listed in the row number in the former verification A matrix.This optimized method can allow the p value of presentation address space figure place reach minimum, thereby make the operation of addressing simple as far as possible under the uniqueness prerequisite that guarantees address information, and the address space that the while look-up table takies reaches minimum.
Utilize the address information of above-mentioned p bit, in the optimized look-up table T that generates in advance, search, obtain the pairing content information in this address.The generation of optimization look-up table T is two of an emphasis of the present invention.The generation of look-up table T has utilized the data segment that receives directly to depend on this conclusion of CRC operation result of the error pattern in the transport process in the CRC calculated result, according to might single-bit error pattern e (x) carry out the long check matrix A that obtains for the cyclic redundancy check (CRC) of m in check digit position, according to optimized subspace I, extraction obtains representing the address information matrix of figure place minimum, and the remainder that extracts back A matrix constitutes the match information matrix.All possible single-bit error pattern e (x) is carried out the long CRC for m in check digit position with the process that obtains check matrix A in, known the pairing single-bit error positional information of every row, this information is handled, be mapped to binary code by certain rule, make up single-bit error positional information matrix.The address of address information matrix as look-up table, match information matrix and single-bit error positional information matrix merge the content information of conduct and the corresponding look-up table of address information, constitute the minimum and the least possible look-up table of content space of shared address space.
The match information of the preceding q bit in the above-mentioned content information and the information to be compared of q bit are compared, and according to whether correcting the single-bit error of check digit, after in the content information
The highest order of the single-bit error positional information of bit is to obtain the monobit errro correction indication.When both match, if carry out the monobit errro correction of information bit and check digit, then export the monobit errro correction indication, if only carry out the monobit errro correction of information bit, then when the highest order of above-mentioned single-bit error positional information is " 1 ", the indication of output monobit errro correction during for " 0 ", is not exported the monobit errro correction indication; When both misfit, mean multi-bit errors has taken place, can't carry out the error correction of single-bit, so error correction procedure finishes.The main body of this part is the comparison of two q bit long sequences, and this is highly susceptible to realizing in digital circuit.
According to the indication of the monobit errro correction of above-mentioned single-bit error positional information and output, to the bit that is in errors present carry out inversion operation or with " 1 " XOR, carry out monobit errro correction.Generally, communication system only need be carried out error correction to the single-bit error of information bit, and the single-bit error of check digit does not need to correct.
The monobit errro correction lookup table circuit that the present invention proposes based on CRC:
Check digit position wherein is long to be the CRC device of m, in the application-specific integrated circuit (ASIC) design, utilize common CRC check unit, the source code of its Hardware Description Language VHDL or Verilog can obtain from a lot of approach, comprise the automatic Core Generator that number of site provides, online open IP storehouse, some semiconductor manufacturers are the hard IP kernel that provides of Cadence company etc. for example.
Selector wherein according to the element value among the subspace I that determines after the optimization, is directly realized the p bit of m Bit data and the division of q bit with hardwired.
Memory wherein.Realize with common general RAM or ROM, in advance the optimized look-up table T of memory address space.The address information of the corresponding look-up table T in the address of memory, the memory contents of the address correspondence of memory corresponds to the content information of look-up table T, and the memory contents of idle address space correspondence is changed to " 1 " or complete " 0 " entirely in the memory.
Comparator wherein, its main part realizes the mutual comparison of the sequence of two q bit long with the comparator of general q bit long sequence.According to whether correcting the single-bit error of check digit, whether decision will add and door.
Monobit errro correction device wherein utilizes the simple combination of shift unit and XOR device, according to single-bit error positional information and monobit errro correction indication, finishes monobit errro correction.
Below long with check digit position in the general frame forming standard be that 16 cyclic redundancy code monobit errro correction is tabled look-up and is example, introduce one embodiment of the present of invention:
To length is that to carry out the check digit position long be 16 CRC for the data of 32 bits, obtain the check results that length is 16 bits, establishing wherein the highest check digit corresponding sequence number is 1, and minimum check digit corresponding sequence number is 16, extract subspace I, I=i from 1 to 16 the check digit sequence number
1, i
2, i
3..., i
p=2,3,4,5,6,7,11, p=7 wherein.
The process of said extracted subspace I is: carrying out the check digit position respectively all the single-bit error pattern e (x) in the data transmission procedure long is 16 CRC, obtain the check results of single-bit error pattern respectively, the length of check results is respectively 16 bits, with all check results by rows, with the basic element of bit as matrix, the corresponding sequence number of the highest check digit is 1, the corresponding sequence number of minimum check digit is 16, as matrix column number, constitute the check matrix A of a n * m with the sequence number of check digit; If the element number of subspace I to be extracted is p, the initial value of getting p is 5; From above-mentioned matrix A, get the p row arbitrarily, constitute 32 * p matrix, total G
16 pPlant combination, the matrix combination is to C
16 pThe combination of kind of matrix travels through search, and until finding any two provisional capitals matrix inequality, each in this matrix is listed in the element value that row in the former A matrix number are subspace I; If do not find any two provisional capitals matrix inequality, then the element number p of subspace I composes with new value, and p=p+1 repeats said process, until finding any two provisional capitals matrix inequality, and to obtain subspace I, p=7 at this moment, I=2,3,4,5,6,7,11.
Set up the look-up table T that address information and content information shine upon one by one, its process is: carrying out the check digit position respectively all the single-bit error pattern e (x) in the data transmission procedure long is 16 CRC, obtain the check results of single-bit error pattern respectively, the length of check results is respectively 16 bits, with all check results by rows, with the basic element of bit as matrix, the corresponding sequence number of the highest check digit is 1, the corresponding sequence number of minimum check digit is 16, as matrix column number, constitute the check matrix A of a n * m with the sequence number of check digit; From matrix A, the element value among the I of subspace as this matrix column number, is extracted 7 row bits, obtain 32 * 7 submatrix B, as the address information among the look-up table T, the remainder of A matrix constitutes 32 * 9 submatrix C, as the match information in the content information of look-up table T; Check results order by rows according to the single-bit error pattern makes up 32 * 5 matrix D, as the single-bit error positional information in the content information of look-up table T, and merge E=[C, D] with submatrix C, constitute 32 * 14 matrix E, as the content information of look-up table T; As the address in the look-up table, corresponding row conduct and the corresponding content in this address constitute look-up table T among the matrix E with the delegation in the matrix B.
The process that wherein makes up matrix D is: the size of establishing matrix D is 32 * 5, and wherein 32 for receiving the length of data segment; Each row of check matrix A is corresponding corresponding separately single-bit error pattern, with " 1 " residing position in each single-bit error pattern, the number of times that is nonzero term in e (x) multinomial is mapped to binary code by certain rule, as the row in the matrix D, its row number is this single-bit error pattern pairing row number in check matrix A, is built into matrix D.When " 1 " residing position is in information bit in the single-bit error pattern, then the value that the polynomial number of times of the pairing e in this position (x) is deducted after 16 is mapped to binary code, its length is 4 bits, before this binary code, fill again " 1 ", as highest order, formation length is 5 new binary code, when " 1 " residing position is in check digit in the single-bit error pattern, then the polynomial number of times of the pairing e in this position (x) is mapped directly to " 0 " binary code entirely.
With the length that receives is that the data segment of n bit carries out that the check digit position is long to be the CRC of m, obtains with 1 * 16 row vectorial R of bit as basic element; If above-mentioned R is a null vector, then the data of Jie Shouing are correct, if non-vanishing, then extract 7 bit elements by subspace I from vectorial R, obtain 1 * 7 the vectorial R of row
p, remainder constitutes 1 * 9 the vectorial R of row
q
To go vectorial R
pAs an address information to be found from above-mentioned look-up table T, according to this address information, obtain and the corresponding content information in this address, this content information comprises the match information of preceding 7 bits and the single-bit error positional information of back 5 bits; The match information of current 7 bits and above line vector R
qWhen matching, if when the highest order of single-bit error positional information be " 1 ", the indication of output monobit errro correction during for " 0 ", is not exported monobit errro correction and is indicated; The match information of q bit and above line vector R before above-mentioned
qWhen misfitting, finish error correction procedure; According to the indication of above-mentioned single-bit error positional information and above-mentioned monobit errro correction, to the bit that is in errors present carry out inversion operation or with " 1 " XOR, carry out monobit errro correction.
Except subspace I and look-up table T make up once when process begins, repeat said process, finish the error correction that all receive data segments.
Claims (7)
1. the monobit errro correction look-up method based on cyclic redundancy code comprises the steps:
(1) be that the data segment of n bit carries out that the check digit position is long to be the CRC of m to the length that receives, obtain the check results that length is the m bit, if wherein the highest check digit corresponding sequence number is 1, minimum check digit corresponding sequence number is m, from 1 to m check digit sequence number, extract subspace I, I=i
1, i
2, i
3..., i
p, wherein 1≤p≤m, and i
1, i
2, i
3..., i
p∈ 1,2 ..., m}, the process of extraction subspace I may further comprise the steps:
(1-1) all the single-bit error pattern e (x) in the data transmission procedure are carried out respectively the check digit position is long to be the CRC of m, obtain the check results of single-bit error pattern respectively, the length of check results is respectively the m bit, with all check results by rows, with the basic element of bit as matrix, the corresponding sequence number of the highest check digit is 1, the corresponding sequence number of minimum check digit is m, with the sequence number of check digit as matrix column number, constitute the check matrix A of a n * m, wherein n is the length of single-bit error pattern e (x);
(1-2) element number of establishing subspace I to be extracted is p, and the initial value of getting p is
(1-3) from above-mentioned matrix A, get the p row arbitrarily, constitute n * p matrix, total C
m pPlant the matrix combination, to C
m pThe combination of kind of matrix travels through search, and until finding any two provisional capitals matrix inequality, each in this matrix is listed in the element value that row in the former A matrix number are subspace I; If do not find any two provisional capitals matrix inequality, then carry out step (4);
(1-4) the element number p to subspace I composes with new value, p=p+1, and repeating step (2) and (3) are until finding any two provisional capitals matrix inequality, to obtain subspace I;
(2) set up the look-up table T that address information and content information shine upon one by one, set up the process of look-up table T, may further comprise the steps:
(2-1) all the single-bit error pattern e (x) in the data transmission procedure are carried out respectively the check digit position is long to be the CRC of m, obtain the check results of single-bit error pattern respectively, the length of check results is respectively the m bit, with all check results by rows, with the basic element of bit as matrix, the corresponding sequence number of the highest check digit is 1, the corresponding sequence number of minimum check digit is m, with the sequence number of check digit as matrix column number, constitute the check matrix A of a n * m, wherein n is the length of single-bit error pattern e (x):
(2-2) from above-mentioned matrix A, with the element value among the above-mentioned subspace I as this matrix column number, extract p row bit, obtain the submatrix B of n * p, as the address information among the look-up table T, the remainder of A matrix constitutes n * q submatrix C, as the match information in the content information undetermined of look-up table T, m=p+q;
(2-3), make up according to the check results order by rows of above-mentioned single-bit error pattern
Matrix D as the single-bit error positional information in the content information undetermined of look-up table T, and merges E=[C, D with above-mentioned submatrix C], constitute
Matrix E, as the content information of look-up table T;
(2-4) with the delegation in the above-mentioned matrix B as the address in the look-up table, among the matrix E corresponding row as and the corresponding content in this address, constitute look-up table T;
(3) data segment that is the n bit with the above-mentioned length that receives carries out that the check digit position is long to be the CRC of m, obtain with the 1 * m capable vector R of bit as basic element, if this row vector R is a null vector, then the data of Jie Shouing are correct, if non-vanishing, then carry out following steps;
(4) from above line vector R, extract the p bit elements, obtain the vectorial R of row of 1 * p by subspace I
p, remainder constitutes the vectorial R of row of 1 * q
q
(5) with above line vector R
pAs an address information to be found from above-mentioned look-up table T, according to this address information, obtain and the corresponding content information in this address, before this content information comprises the match information of q bit and after
The single-bit error positional information of bit;
(6) match information of q bit and above line vector R before above-mentioned
qWhen matching, if carry out the monobit errro correction of information bit and check digit, then export the monobit errro correction indication, if only carry out the monobit errro correction of information bit, then when the highest order of above-mentioned single-bit error positional information is " 1 ", the indication of output monobit errro correction during for " 0 ", is not exported the monobit errro correction indication; The match information of q bit and above line vector R before above-mentioned
qWhen misfitting, finish error correction procedure;
(7) according to the indication of above-mentioned single-bit error positional information and above-mentioned monobit errro correction, to the bit that is in errors present carry out inversion operation or with " 1 " XOR, carry out monobit errro correction;
(8) error correction that all receive data segment is finished in repeating step (3)～(7).
2. the method for claim 1 is characterized in that the wherein said data length that receives is 32 bits, and wherein the check digit position is long is 16, and the subspace I of extraction is: I=i
1, i
2, i
3..., i
p=2,3,4,5,6,7,11, p=7 wherein.
3. the method for claim 1 is characterized in that wherein setting up the process that makes up matrix D in the process of look-up table T, may further comprise the steps:
(1) size of establishing matrix D is
Wherein n is for receiving the length of data segment;
(2) will with above-mentioned check matrix A each the row corresponding single-bit error pattern in " 1 " residing position, the number of times that is nonzero term in e (x) multinomial is mapped to binary code, as the row in the matrix D, its row number is this single-bit error pattern pairing row number in check matrix A, is built into matrix D.
4. method as claimed in claim 3, it is characterized in that the method that wherein said number of times with nonzero term in e (x) multinomial is mapped to binary code is: if carry out the monobit errro correction of information bit and check digit, then the number of times with nonzero term in pairing e (x) multinomial is mapped directly to binary code; If only carry out the monobit errro correction of information bit, when " 1 " residing position was in information bit in the single-bit error pattern, the value that then the polynomial number of times of the pairing e in this position (x) is deducted behind the m was mapped to binary code, and its length is
Bit, and before this binary code, fill " 1 ", as highest order, formation length is
Binary code, when " 1 " residing position is in check digit in the single-bit error pattern, then the polynomial number of times of the pairing e in this position (x) is mapped directly to " 0 " binary code entirely.
5. monobit errro correction lookup table circuit based on cyclic redundancy code is characterized in that this circuit comprises:
(1) the check digit position is long is the CRC device of m, and being used for the length that receives is that the data segment of n bit carries out verification, obtains the check results of m bit, is input to selector, and the CRC device is connected with selector;
(2) selector is used for selecting the p bit from above-mentioned check results by subspace I, is input to memory as address information, residue q bit is as information to be compared, be input to comparator, selector is connected with comparator with memory respectively, wherein said subspace I=i
1, i
2, i
3..., i
p, wherein 1≤p≤m, and i
1, i
2, i
3..., i
p∈ 1,2 ..., m}, m are minimum check digit corresponding sequence number, 1 is the highest check digit corresponding sequence number;
(3) memory is used for store look-up tables T, and according to the address information of above-mentioned input, the content information in being shown accordingly, comprising the match information of q bit and
The single-bit error positional information of bit, memory is connected with comparator, and wherein said store look-up tables T is address information and content information mapping table;
(4) comparator, whether the match information that is used for comparison foregoing information is identical with information to be compared, and to obtain the monobit errro correction indication, comparator is connected with the monobit errro correction device;
(5) monobit errro correction device is used for finishing monobit errro correction according to above-mentioned single-bit error positional information and monobit errro correction indication.
6. circuit as claimed in claim 5, it is characterized in that wherein said comparator comprises: q bit sequence comparator, whether the match information of q bit that is used for comparison foregoing information is identical with information to be compared, identical output " 1 ", output inequality " 0 ", q bit sequence comparator be connected with door; Or q bit sequence comparator reaches and door, the output of above-mentioned q bit sequence comparator is directly indicated as monobit errro correction, if only carry out the monobit errro correction of information bit, then with the highest order of the output of above-mentioned q bit sequence comparator and above-mentioned single-bit error positional information with the result indicate as monobit errro correction.
7. circuit as claimed in claim 5 is characterized in that wherein said monobit errro correction device comprises:
(1) shift unit is used for according to above-mentioned single-bit error positional information, and " 1 " is moved on to the position at errors present bit place, and other positions are " 0 ", and shift unit is connected with the XOR device;
(2) XOR device according to monobit errro correction indication, when this is designated as " 1 ", carries out xor operation with the data that receive and the output of shift unit, finishes monobit errro correction, during for " 0 ", does not carry out xor operation.
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| CN102612173B (en) * | 2011-01-21 | 2016-08-10 | 芯讯通无线科技（上海）有限公司 | The means of communication between multi mode terminal and communication module thereof |
| CN113708779A (en) * | 2015-12-28 | 2021-11-26 | 北京忆芯科技有限公司 | Matrix and vector multiplication operation unit |
| CN108958963A (en) * | 2018-06-01 | 2018-12-07 | 杭州电子科技大学 | A kind of NAND FLASH error control method based on LDPC and cyclic redundancy check code |
| CN112622448B (en) * | 2020-12-17 | 2021-08-13 | 上海坚芯电子科技有限公司 | Method and system for designing ink box chip supporting circular ink adding |
| CN113162728B (en) * | 2021-03-25 | 2022-11-04 | 展讯半导体(南京)有限公司 | Polarized Polar coding method and device, electronic equipment and storage medium |
| CN113050519B (en) * | 2021-03-31 | 2022-04-12 | 山东商业职业技术学院 | CRC 16-based single-bit error correction FPGA implementation method |
| CN114942861A (en) * | 2022-03-22 | 2022-08-26 | 安吉芥子科技有限公司 | CRC calculation method, device, computer equipment and storage medium |
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| CN1238075A (en) * | 1996-09-27 | 1999-12-08 | 艾利森公司 | Error detection scheme for ARQ systems |
| WO2003100987A1 (en) * | 2002-05-24 | 2003-12-04 | Nokia Corporatoin | Crc-based error correction |
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| CN1238075A (en) * | 1996-09-27 | 1999-12-08 | 艾利森公司 | Error detection scheme for ARQ systems |
| WO2003100987A1 (en) * | 2002-05-24 | 2003-12-04 | Nokia Corporatoin | Crc-based error correction |
| CN1571284A (en) * | 2003-07-14 | 2005-01-26 | 北京大学 | A fast circulating CRC verification method used for correcting error bits in data frame |
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