CN100424841C - Method for mfg. semiconductor device and method for removing gap wall - Google Patents
Method for mfg. semiconductor device and method for removing gap wall Download PDFInfo
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- CN100424841C CN100424841C CNB2005101067989A CN200510106798A CN100424841C CN 100424841 C CN100424841 C CN 100424841C CN B2005101067989 A CNB2005101067989 A CN B2005101067989A CN 200510106798 A CN200510106798 A CN 200510106798A CN 100424841 C CN100424841 C CN 100424841C
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Abstract
The invention discloses a semiconductor device manufacturing method, comprising defining an electrode on a semiconductor substrate; forming a gap wall on at least a side wall of the electrode; making a process operation on the semiconductor substrate, using the gap wall as mask and producing a matter layer on the semiconductor substrate and the top or surface of the electrode; and removing the gap wall, where the step of removing the gap wall comprises using phosphoric acid-containing acidic solution as etching solution to make wet etching process on the gap wall at 100DEG C-150DEG C. On the other hand, it also reveals a method of removing gap wall in semiconductor process, using phosphoric acid-containing acidic solution as etching solution to make wet etching process on the gap wall in semiconductor process at 100DEG C-150DEG C.
Description
Technical field
The present invention relates to a kind of semiconductor device technology, relate in particular to removing for clearance wall in the semiconductor device technology.
Background technology
Size of semiconductor device acutely reduces before than many decades.At present, manufacturer can make the semiconductor device with 0.35 μ m, 90nm even 65nm or littler live width.Along with size is dwindled, semiconductor making method also often needs to improve.
The manufacturing of existing MOS (metal-oxide-semiconductor) device utilizes and builds the technology of putting clearance wall is injected MOS with help control and definition dopant source area and drain region.Fig. 1 shows the schematic diagram of an existing NMOS semiconductor device.Existing nmos pass transistor device 10 comprises semi-conductive substrate usually.This Semiconductor substrate contains a silicon layer 16, the drain electrode 20 that is formed with source electrode 18 and separates mutually by channel region 22 with source electrode 18 in silicon layer 16.Usually, semiconductor N MOS transistor element 10 also has extension 17 of shallow junction source electrode and shallow junction drain electrode to extend 19, respectively with source area 18 and 20 adjacent boundaries, drain region.Be formed with a gate dielectric 14 on channel region 22, then be formed with grid 12 on gate dielectric 14, wherein grid 12 generally includes polysilicon.Gate dielectric 14 isolated gates 12 and channel region 22.The source electrode 18 of semiconductor N MOS transistor element 10 and 20 the N+ doped regions that drain for injection arsenic, antimony or phosphorus.22 P type doped regions of the channel region of semiconductor N MOS transistor element 10 for injection boron.On the sidewall of grid 12, be formed with silicon nitride gap wall 32.Between the sidewall of silicon nitride gap wall 32 and grid 12 is laying 30, it typically is silicon dioxide and constitutes.The bare silicon surfaces of semiconductor N MOS transistor element 10 comprises drain/source and grid, then forms self-aligned metal silicate layer 42.At present, utilize self-aligned metal silicate (self-aligned silicide, salicide) technology forms metal silicide layer; That is after forming source/drain regions, utilize sputter or deposition process, form a cobalt (Co), titanium (Ti) or nickel metal levels such as (Ni) again and be covered in source/drain regions and grid structure top, carry out a quick high-temp then and handle (rapid thermal process, RTP) make pasc reaction in metal and grid structure, the source/drain regions, form the sheet resistance (sheet resistance) that metal silicide reduces source/drain regions.
In existing MOS manufacturing technology, often when making LDD (lightly doped drain) district, use clearance wall to reach the doping of source/drain regions and LDD district variable concentrations.Can drive circulation and control LDD district with heat by the width of clearance wall.The injection degree of depth of LDD district and source/drain can be independently of one another and irrelevant.In the technology of 65nm or smaller szie, channel mobility needs to strengthen, this can be further by after removing clearance wall, reaching in the dielectric layer of semiconductor substrate surface height of deposition strain.Yet, remove clearance wall, especially silicon nitride gap wall is crucial, may damage contiguous structure because this removes, for example: metal silicide layer, grid, and under silicon substrate.
The existing hot phosphoric acid (H that uses 160 ℃
3PO
4) technology removes silicon nitride gap wall, shown in the step 100 of Fig. 2.But this causes the corrosion of NiSi substrate and NiSi metal silicide layer in PMOS and the nmos area territory usually.Yet at low temperatures, phosphoric acid is etching of silicon nitride significantly, and higher temperature can quicken the attack to silica, but reduces the etch-rate to silicon nitride.And under 160 ℃ high temperature, the NiSi layer is very easily corroded.So, use the phosphoric acid etch silicon nitride structure to have difficulty.
Therefore, still need a kind of preferred methods removing the clearance wall that forms in the semiconductor technology, and do not damage the self-aligned metal silicate layer.
Summary of the invention
The purpose of this invention is to provide a kind of method and a kind of method that in semiconductor technology, removes clearance wall of making semiconductor device, do not damage near the structure it to remove clearance wall.
According to the method for manufacturing semiconductor device of the present invention, be included in definition one electrode on the semi-conductive substrate; On at least one sidewall of electrode, form a clearance wall; Carry out a technological operation on Semiconductor substrate, technological operation uses clearance wall to produce a material layer as mask and in the top or the surface of Semiconductor substrate and electrode; And the step that removes clearance wall.Wherein, the step that removes clearance wall comprises uses the acid solution that contains phosphoric acid as etching solution, under 100 ℃ to 150 ℃ first temperature clearance wall is carried out wet etch process.
According to the method that removes clearance wall of the present invention, comprise a substrate is provided that wherein, substrate has an electrode, has a clearance wall at least one sidewall of electrode, and the top or the surface of substrate and electrode have a material layer; And use the acid solution that contains phosphoric acid as etching solution, under 100 ℃ to 150 ℃ first temperature, clearance wall is carried out wet etch process.
According to one embodiment of the invention, the acid solution that contains phosphoric acid can give Ageing Treatment (seasoning) with silicide, and reach saturation point, with the usefulness of supply etching before use earlier through preliminary treatment under one second temperature.Perhaps, after reaching saturation point, further make the acid solution that contains phosphoric acid of gained under one the 3rd temperature, leave standstill a period of time, supply the usefulness of etching again.
In the present invention, removing of clearance wall is the acid solution that contains phosphoric acid that utilizes lower temperature as the wet etch process of etching solution and finishes, this acid solution that contains phosphoric acid is through preliminary treatment, can under the condition of relative low temperature, remove clearance wall, but can not damage self-aligned metal silicate (salicide) layer.
Description of drawings
What Fig. 1 illustrated is the schematic cross-section of conventional semiconductor MOS transistor element;
Fig. 2 shows the step of existing removal silicon nitride gap wall;
What Fig. 3 to Fig. 6 illustrated is the method generalized section that the preferred embodiment of the present invention is made the semiconductor MOS element;
Fig. 7 shows the etching solution pretreatment process according to one embodiment of the invention;
Fig. 8 shows the etching solution pretreatment process according to another embodiment of the present invention;
Fig. 9 shows according to the present invention and removes behind the clearance wall further semiconductor technology.
The main element symbol description
10 MOS transistor elements
12 grids
14 gate dielectrics
16 silicon layers
17 shallow junction source electrodes extend
18 source electrodes
The drain electrode of 19 shallow junctions is extended
20 drain electrodes
22 channel regions
30 layings
32 silicon nitride gap walls
42 metal silicide layers
46 silicon nitride cap rocks
100,200,202,204 steps
Embodiment
See also Fig. 3 to Fig. 6, its demonstration be the generalized section that the preferred embodiment of the present invention is made the method for semiconductor MOS transistor unit 10, wherein components identical or position are still continued to use identical Reference numeral and are represented.Be noted that accompanying drawing only for the purpose of description, do not map according to life size.
The invention relates to a kind of method of making NMOS, PMOS transistor unit or cmos element in the integrated circuit.As shown in Figure 3, prepare semi-conductive substrate, it generally comprises silicon layer 16.Aforesaid Semiconductor substrate can be silicon substrate or silicon-coated insulated (silicon-on-insulator, SOI) substrate.Definition one electrode, for example a grid 12 on Semiconductor substrate.Can form extension 17 of shallow junction source electrode and shallow junction drain electrode extension 19 in silicon layer 16, extension 17 of shallow junction source electrode and shallow junction drain between the extension 19 across a raceway groove 22.
Can on raceway groove 22, form a grid oxic horizon 14, to separate grid 12 and raceway groove 22.Grid 12 generally includes polysilicon.Grid oxic horizon 14 can be made of silicon dioxide.Yet in another embodiment of the present invention, grid oxic horizon 14 also can be made of high-k (high-k) material.Subsequently, on the sidewall of grid 12, form silicon nitride gap wall 32.Between grid 12 and silicon nitride gap wall 32 laying 30 can be arranged in addition, aforesaid laying can be silica and constitutes.Laying 30 is generally L type and thickness between 30 to 120 dusts.Laying 30 can have a skew clearance wall (offset spacer) in addition, and it is known to those skilled in the art, and is therefore also not shown.
As shown in Figure 4, after forming silicon nitride gap wall 32, can further carry out an ion implantation technology, with N type dopant, for example arsenic, antimony or phosphorus etc. inject silicon layer 16, or with P type dopant, for example boron etc. injects silicon layer 16, forms the source area 18 and the drain region 20 of NMOS or PMOS element 10 by this.After the doping of finishing drain-source, Semiconductor substrate can be carried out the heat treatment an of annealing (annealing) or activation (activation) dopant usually, and this step also is well known to those skilled in the art, and is no longer stated.
As shown in Figure 5, on grid 12, the source area 18 that exposes and the drain region 20 of exposing, form a material layer, for example a metal silicide layer (metal silicide layer) 42.Utilize self-aligned metal silicate (self-aligned silicide, salicide) technology forms metal silicide layer; That is after forming source/drain regions, utilize sputter or deposition process, form one again and comprise that the metal level of nickel is covered in source/drain regions and grid structure top, carrying out a quick high-temp then handles (RTP) and makes pasc reaction in metal and grid structure, the source/drain regions, formation nickel silicide.The RTP temperature can be between 700 ℃ to 1000 ℃.
Then, as shown in Figure 6, silicon nitride gap wall 32 is removed, stayed laying 30 on the sidewall of grid 12.In the present invention, removing of silicon nitride gap wall 32 is to utilize wet etch process to carry out, and can not damage metal silicide layer 42.According to embodiments of the invention, use the acid solution that contains phosphoric acid as etching solution, first temperature in 100 ℃ to 150 ℃ is preferably 140 ℃, removes silicon nitride gap wall 32.This acid solution that contains phosphoric acid can be the phosphate aqueous solution of any concentration, as long as clearance wall is had etch capabilities.Be preferably, phosphoric acid concentration is different according to etch temperature, the scope about 50% to about 100%, and as under 140 ℃ etch temperature, more preferably 79.5%.The acid solution that contains phosphoric acid can optionally contain other additives, for example buffer and/or other acids, for example fluoboric acid (fluoboric acid) and sulfuric acid.For reaching under 150 ℃ or lower temperature, the acid solution that contains phosphoric acid is the effective purpose of etched gap wall still, needs before use, carry out preliminary treatment to it.
See also Fig. 7, its demonstration contains the pre-treatment step of the acid solution of phosphoric acid.Shown in step 200, make the acid solution that contains phosphoric acid under one second temperature, through silicide Ageing Treatment (seasoning), and reach saturation point." saturation point " of the alleged herein acid solution that contains phosphoric acid is meant that this acid solution that contains phosphoric acid is carrying out Ageing Treatment after a period of time with silicide, causes nickel silicide can't be contained the etched time point of acid solution of phosphoric acid by this.Second temperature can be for example temperature between 100 ℃ to 180 ℃, is preferably 160 ℃.Carrying out Ageing Treatment with after reaching saturation point, can directly carry out step 204, the usefulness of the wet etching process of supply clearance wall, or can further carry out step 202 shown in Figure 8, make this acid solution that contains phosphoric acid under one the 3rd temperature, leave standstill a period of time.This 3rd temperature is 100 ℃ to 150 ℃, is preferably 140 ℃.The purpose that leaves standstill, can make the acid solution that contains phosphoric acid be issued to stable azeotropic point in this 3rd temperature, the 3rd temperature can be above-mentioned first temperature, then carry out step 204 again, for the usefulness of wet etching process, make for silicon nitride and metal silicide to have excellent etching selectivity, removable silicon nitride layer, and do not damage metal silicide layer.
Aforesaid Ageing Treatment, can one or the dummy wafer (dummywafer) of multi-disc top layer with silicide layer be soaked in this and contain the acid solution of phosphoric acid and reach, but be not limited thereto mode, any mode that can provide silicide to be dissolved in wherein to the acid solution that contains phosphoric acid all can.Silicide can be exemplified as silicon nitride, but is not limited thereto.
As shown in Figure 6, remove clearance wall 32 after, only on gate lateral wall, stay the laying of the rough L of being type.Laying not necessarily is the L type, also can carry out a relatively mild etch process, omits the microetch laying, to reduce its thickness.In other embodiments, laying can be removed fully.The thickness of laying can be rough between 0 to 500 dust.After removing clearance wall, can carry out next technology according to need, for example, the making of strained silicon or the carrying out of other semiconductor process techniques.As shown in Figure 9, can be on Semiconductor substrate uniform deposition one silicon nitride cap rock 46, its thickness is preferably between 30 to 2000 dusts.Laying 30 on grid 12 sidewalls of silicon nitride cap rock 46 and MOS transistor element 10 is directly bordered on.Silicon nitride cap rock 46 is set earlier when deposition (for example be deposited on a compressing stress state,-0.1Gpa is between-the 3Gpa, for NMOS) or a tensile stress state is (for example, 0.1Gpa between 3Gpa, for PMOS), so, make channel region 22 have corresponding elongation strain or compression strain, can improve mobility of charge carrier rate in the raceway groove at channel direction.The change of silicon nitride cap rock 46 stress states can utilize germanium ion to inject or other existing methods are carried out.
Contain the preliminary treatment of the acid solution of phosphoric acid among following example explanation the present invention, and comparative example only supplies than than usefulness.
Example
Embodiment 1
Make the acid solution (H that contains phosphoric acid
3PO
4Concentration is 79.5%) in etching bath, be heated to 160 ℃, placing 50 surface depositions has the dummy wafer of SiN layer so far to contain in the acid solution of phosphoric acid to carry out Ageing Treatment, the dummy wafer test of NiSi layer is arranged with surface deposition, when this acid solution that contains phosphoric acid no longer corrodes the NiSi layer, then for reaching saturation point.This acid solution that contains phosphoric acid is cooled to 140 ℃, left standstill 48 hours.Afterwards, provide this acid solution that contains phosphoric acid as the etching solution that removes SiN clearance wall on the Semiconductor substrate.This Semiconductor substrate still has an electrode and is positioned at the source/drain regions of electrode both sides, and clearance wall is positioned on the electrode sidewall, between clearance wall and the electrode laying is arranged, and the source/drain regions surface has the NiSi layer with top of electrodes.As a result, clearance wall is removed, and the NiSi layer on the Semiconductor substrate is not caused damage, and obtains good etch effect.
Comparative example 1
Make the acid solution (H that contains phosphoric acid
3PO
4Concentration is 79.5%) in etching bath, be heated to 120 ℃, placing 50 surface depositions has the dummy wafer of SiN layer so far to contain in the acid solution of phosphoric acid carrying out Ageing Treatment, with surface deposition the dummy wafer test of NiSi layer is arranged, and does not reach saturation point.This acid solution that contains phosphoric acid is warming up to 140 ℃, left standstill 12 hours.Afterwards, provide this acid solution that contains phosphoric acid as the etching solution that removes SiN clearance wall on the Semiconductor substrate.This Semiconductor substrate is as described in the embodiment.As a result, clearance wall is removed, however the NiSi layer on the Semiconductor substrate also remove, can't obtain good etch effect.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. method of making semiconductor device may further comprise the steps:
Definition one electrode on semi-conductive substrate;
Form a clearance wall at least one sidewall of this electrode, this clearance wall comprises silicon nitride;
Carry out a technological operation on this Semiconductor substrate, this technological operation uses this clearance wall to produce a material layer as mask and in the top or the surface of this Semiconductor substrate and this electrode; And
Remove this clearance wall, the step that wherein removes this clearance wall comprises:
Use an acid solution that contains phosphoric acid under 140 ℃ first temperature, this clearance wall to be carried out a wet etch process as etching solution,
Wherein this acid solution that contains phosphoric acid is to pass through the silicide Ageing Treatment before carrying out this wet etch process under second temperature prior to 160 ℃, and reaches saturation point.
2. the method for claim 1, wherein this material layer comprises nickel silicide.
3. the method for claim 1 after this Ageing Treatment, also comprises the step that this acid solution that contains phosphoric acid is left standstill under one the 3rd temperature.
4. method as claimed in claim 3, wherein the 3rd temperature is first temperature.
5. the method for claim 1, wherein this silicide Ageing Treatment is to be soaked in this with silicide layer to contain the acid solution of phosphoric acid and carry out.
6. method as claimed in claim 5, wherein this silicide layer comprises silicon nitride.
7. method that removes clearance wall may further comprise the steps:
One substrate is provided, and wherein, this substrate has an electrode, has a clearance wall at least one sidewall of this electrode, and this clearance wall comprises silicon nitride, and the top of this substrate and this electrode or surface have a material layer; And
Use an acid solution that contains phosphoric acid under 140 ℃ first temperature, this clearance wall to be carried out a wet etch process as etching solution,
Wherein this acid solution that contains phosphoric acid is to pass through the silicide Ageing Treatment before carrying out this wet etch process under second temperature prior to 160 ℃, and reaches saturation point.
8. method as claimed in claim 7, wherein this material layer comprises nickel silicide.
9. method as claimed in claim 7 after this Ageing Treatment, also comprises the step that this acid solution that contains phosphoric acid is left standstill under one the 3rd temperature.
10. method as claimed in claim 9, wherein the 3rd temperature is 100 ℃ to 150 ℃.
11. method as claimed in claim 7, wherein this silicide Ageing Treatment is to be soaked in this with silicide layer to contain the acid solution of phosphoric acid and carry out.
12. method as claimed in claim 11, wherein this silicide layer comprises silicon nitride.
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| CN101197264B (en) * | 2007-12-25 | 2013-01-09 | 上海集成电路研发中心有限公司 | Forming method of L-shaped side wall |
| TWI811513B (en) * | 2019-03-20 | 2023-08-11 | 日商東芝股份有限公司 | Semiconductor wafer and semiconductor device manufacturing method |
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