CN100414518C - Improved virtual address conversion and converter thereof - Google Patents
Improved virtual address conversion and converter thereof Download PDFInfo
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- CN100414518C CN100414518C CNB2004100913779A CN200410091377A CN100414518C CN 100414518 C CN100414518 C CN 100414518C CN B2004100913779 A CNB2004100913779 A CN B2004100913779A CN 200410091377 A CN200410091377 A CN 200410091377A CN 100414518 C CN100414518 C CN 100414518C
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention discloses an improved virtual address conversion method and a converter thereof. The method comprises that by using the data locality, a virtual address which needs converting into a physical address is compared with a virtual address which is converted last time, if the two virtual addresses belong to the same virtual page table, a random access memory (RAM) part of a translation look-aside buffer (TLB) is not accessed, the address of the physical page table, which is obtained by the last conversion, is directly used, and the access times of the random access memory in the translation look-aside buffer is reduced; an instruction translation look-aside buffer (ITLB) and a data translation look-aside buffer (DTLB) share a random access memory with a single read port; the physical page table address output by the random access memory is deferred, the selecting operation of using the physical page table address last time is saved., and thus, the effect of reducing partial power consumption and area of the translation look-aside buffer can be achieved, and simultaneously, the performance of the processor can not be lowered, and the circuit delay can not be increased.
Description
Technical field
The present invention relates to the micro-processor architecture technical field, particularly being responsible for virtual address translation in the processor is the method for designing of the translation look aside buffer (TLB, Translation Lookaside Buffer) of physical address.
Background technology
In virtual storage system, must be physical address with virtual address translation, translation look aside buffer in the memory management unit of processor designs in order to quicken this address translation, the list item of each logical page address of storage and physical page address in the translation look aside buffer, and set up both mapping relations, at the inner mapping process that just can finish from the virtual address to the physical address of processor, quicken the conversion from the virtual address to the physical address like this.
Translation look aside buffer is made up of two parts usually, a part is a storing virtual address page list item, be used for carrying out linking to each other full content comparators (CAM) relatively with the virtual address of visit, another part is a storage physical address page table entry, by the random access memory (RAM) of index search.When a memory access address visit translation look aside buffer, in content comparators, search earlier virtual page list item concurrently with the memory access matching addresses, after finding,, obtain the residing Physical Page list item of reference address physical address corresponding according to the index accesses random access memory of finding the position.
Because processor has instruction fetch and two parallel processes of data memory access, and no matter instruction fetch still is the data memory access, all need to visit the translation look aside buffer parts, carry out virtual address translation is the process of physical address, traditional translation look aside buffer implementation method has two kinds: a kind ofly be to use two translation look aside buffers, that is: instruction translation lookaside buffer (ITLB, Instruction Translation Lookaside Buffer) and data translation lookaside buffer (DTLB, Data Translation Lookaside Buffer), handle instruction fetch and data accessing operation respectively; Another kind is to use a shared translation look aside buffer, promptly accepts the visit of instruction fetch, accepts the visit of data memory access again.The shortcoming of first method is that circuit area is very big in the traditional design, power consumption is also very high, and being performance of processors, the shortcoming of second method of traditional design can be subjected to negative effect, because when occurring instruction fetch and data memory access simultaneously, can't handle simultaneously, must postpone the processing of one of them visit, if second method adopts the content comparators of dual-port and the random access memory of dual-port, can cause circuit area to increase again, the shortcoming that power consumption increases.
Summary of the invention
The objective of the invention is to overcome the defective of prior art; The conversion process of improvement from the virtual address to the physical address, reduce the area and the power consumption of translation look aside buffer circuit, also do not influence performance of processors and circuit sequence simultaneously, thus the device that a kind of improved virtual address translation method is provided and realizes this method.
In order to solve the problems of the technologies described above, the invention provides a kind of improved virtual address translation method, promptly, may further comprise the steps from the method for virtual address to the physical address conversion:
A) compare in instruction translation lookaside buffer and data translation lookaside buffer virtual address/data virtual address that finger is got with the last time in this virtual address of getting finger/data;
B) judge whether symbolic animal of the birth year with page table or direct mapping space, if, execution in step g), if not, carry out next step;
C) the shared single read port random access memory of instruction translation lookaside buffer and data translation lookaside buffer is accepted the inquiry to physical address;
D) instruction translation lookaside buffer and data translation lookaside buffer are preserved the physical address that conversion obtains in register, and postpone respectively with the Physical Page table address of random access memory output and do selection;
Respectively simultaneously with the physical address in these two sources (this conversion and last transform), produce two echo signals respectively when e) instruction translation lookaside buffer and/or data translation lookaside buffer use;
F) two echo signals that respectively step e) produced are selected, the consequential signal that output needs;
G) do not visit random access memory, use the address of the last transform of preserving, execution in step e).
In such scheme, in described step a), b) and g), following two kinds of situations are arranged, virtual address translation is not visited the random access memory of translation look aside buffer during to physical address, a kind of be will get to refer to that address that needs that operation causes carry out conversion was got with the last time to refer to that the address of finishing conversion that operation causes compares at every turn, if dropped in the same virtual page list item with last address, then do not visit again random access memory, and the Physical Page table address result who directly utilizes last conversion to obtain, the address mapping that the data memory access causes also uses with getting and guides the identical processing procedure of sending out of address mapping, another kind of situation is, the virtual address that causes for instruction fetch and data accessing operation is to the conversion of physical address, if the residing address space of virtual address is direct mapping space, do not need to search the map addresses that the mapping relations list item of translation look aside buffer just can be finished, do not visit the random access memory of translation look aside buffer.
In such scheme, at described step d) and e) in, if next time during address mapping virtual address with this virtual address in same page table, then use the physical address of preserving in the register, otherwise the random access memory of query translation lookaside buffer, the Physical Page table address that uses random access memory to export.
A kind of device of implementing improved virtual address translation method provided by the invention, comprise the content comparators circuit and the random access memory circuit of depositing the physics page table address that are used to deposit and compare the virtual page table address, instruction fetch and data memory access have content comparators circuit separately, be first content comparator circuit and second content comparator circuit, and the first alternative circuit that the index that these described two content comparators circuit are relatively exported is selected, and the shared random access memory circuit that has only a read port of instruction fetch and data memory access, also comprise this time get the virtual address that refers to conversion and got last time compare between the virtual address that refers to conversion judge get refer to the virtual address whether symbolic animal of the birth year with page table or directly first comparator circuit and first decision circuitry of mapping space, second comparator circuit between the virtual address of the virtual address of this secondary data memory access conversion and last secondary data memory access conversion and second decision circuitry, second registers group that preservation is got first registers group of the Physical Page table address that obtains behind the finger last transform and preserved the Physical Page table address that obtains behind the data memory access last transform, and described first registers group is through the second alternative circuit of Physical Page table address between 1 consequential signal of the 4th comparator circuit output of 1 consequential signal of the 3rd comparator circuit output and random access memory circuit output, and described second registers group is through the three alternative circuit of Physical Page table address between 1 consequential signal of the 5th comparator circuit output of 1 consequential signal of the 6th comparator circuit output and random access memory circuit output, the consequential signal that described second alternative circuit of process and the output of described the 3rd alternative circuit need.
In such scheme, mark (TAG) comparator circuit that described the 3rd comparator circuit is instruction cache (CACHE) is used for the mark value of comparison order high-speed cache and the content of described first registers group, exports 1 consequential signal.
In such scheme, described the 4th comparator circuit is the mark comparator circuit of instruction cache, is used for the mark value of comparison order high-speed cache and the content of the Physical Page table address that random access memory is exported, and exports 1 consequential signal.
In such scheme, described the 5th comparator circuit is the mark comparator circuit of data cache, is used for the mark value of comparing data high-speed cache and the content of the Physical Page table address that random access memory is exported, and exports 1 consequential signal.
In such scheme, described the 6th comparator circuit is the mark comparator circuit of data cache, is used for the mark value of comparing data high-speed cache and the content of second registers group, exports 1 consequential signal.
In such scheme, described single read port random access memory circuit, be used to keep the random access memory of Physical Page table address and associated control signal, the shared described single read port random access memory circuit of instruction translation lookaside buffer and data translation lookaside buffer, described single read port random access memory circuit priority processing are got the address mapping visit of finger.
In such scheme, described single read port random access memory circuit is replaceable to be single read port register file circuit.
In such scheme, described first comparator circuit and first decision circuitry are used to generate the enable signal of visiting random access memory, if the address of twice conversion in front and back is not at same page table, and the address of conversion does not this time belong to directly mapping space, just visits random access memory.
In such scheme, described second comparator circuit and second decision circuitry are used to generate the enable signal of visiting random access memory, if the address of twice conversion in front and back is not at same page table, and the address of conversion does not this time belong to directly mapping space, just visits random access memory.
In such scheme, the described second alternative circuit uses 1 output result of the 4th comparator circuit after instruction lookaside buffer visit random access memory, otherwise selects 1 output result of the 3rd comparator circuit; Described the 3rd alternative circuit uses 1 output result of the 5th comparator circuit after data lookaside buffer visit random access memory, otherwise selects 1 output result of the 6th comparator circuit.
As from the foregoing, the present invention is by innovative design, utilize data locality, the virtual address that needs is transformed into physical address is compared with the virtual address of conversion last time, if belong to a virtual page table together, then do not visit the random access memory part of translation look aside buffer, and the Physical Page table address that directly utilizes last transform to obtain, to reduce access times to random access memory in the translation look aside buffer; And instruction translation lookaside buffer and the shared single read port random access memory of data translation lookaside buffer; And the selection operation of the Physical Page table address of the Physical Page table address of postponement random access memory output and use last time of preservation, can reach the power consumption of reduction translation look aside buffer part and the effect of area like this, can not reduce the delay of performance of processors and increase circuit simultaneously again.
Description of drawings
Fig. 1 is of the present invention from the process flow diagram of virtual address to the method embodiment of physical address conversion;
Fig. 2 is the embodiment schematic block diagram that the improved virtual address translation device of the present invention is formed.
Embodiment
Describe technical scheme of the present invention with reference to the accompanying drawings in detail, the applicant has applied for also that on the same day another denomination of invention is: the patent of " a kind of from method and the device thereof of virtual address to the physical address conversion " is incorporated herein by reference.
The objective of the invention is to improve the conversion process from the virtual address to the physical address, reduce the area and the power consumption of translation look aside buffer circuit, also do not influence performance of processors and circuit sequence simultaneously.
Referring to Fig. 1, a kind of improved virtual address translation method may further comprise the steps:
Does step 110 judge whether that symbolic animal of the birth year is with page table or direct mapping space? if execution in step 160 if not, is carried out next step;
In step 130---in the step 150, after the shared random access memory of instruction translation lookaside buffer and data translation lookaside buffer, instruction translation lookaside buffer and data translation lookaside buffer need respectively with register the physical address separately that each address mapping obtains to be preserved, if next time during address mapping virtual address with this virtual address in same page table, then use the physical address of preserving in the register, otherwise the random access memory of query translation lookaside buffer, use the Physical Page table address of random access memory output, this selects the source of Physical Page table address with regard to needing the alternative circuit, in order to avoid increasing the delay of circuit as far as possible, directly the register of preservation Physical Page table address and the output of random access memory are not selected, but need to use in the circuit of physical address in the back, use the physical address in these two sources simultaneously, after producing two echo signals, again this two root objects signal is selected, thereby avoided, when the Physical Page table address of tens bit wides and associated control signal are selected, the load of increase and strong the driving.
Describe in detail from the device of virtual address below in conjunction with Fig. 2 to the physical address conversion.
With reference to figure 2, make the device of an improved virtual address translation, comprise first comparator circuit 10, second comparator circuit 13, the 3rd comparator circuit 20, the four comparator circuits 21, the five comparator circuits 22, the 6th comparator circuit 23, first content comparator circuit 11, second content comparator circuit 12, the first decision circuitry 14, second decision circuitry 15, the first alternative circuit, 16, the second alternative circuit, 24, the three alternative circuit 25, first registers group, 18, the second registers group 19 and single read port random access memory circuit 17.
Refer to be example to get, when getting finger Address requests access instruction translation look aside buffer for one, at first virtual address is carried out content relatively with the content comparators of preserving virtual page table address item, virtual address with process translation look aside buffer conversion last time in history compares simultaneously, and judge whether this virtual address belongs to direct mapping address space, if the virtual address of conversion this time belongs to a virtual page table together with the virtual address of conversion last time, or the virtual address of conversion this time belongs to direct mapping address space, then generate and enable control signal, do not allow the random access memory of this conversion visit translation look aside buffer, otherwise, if this conversion and last transform do not belong to same virtual page table, and the address of conversion does not this time belong to direct mapping space, then use the random access memory of the index accesses translation look aside buffer that the query contents comparer obtains, to obtain corresponding Physical Page table address.Translation look aside buffer has only the random access memory that is used to keep Physical Page table address and associated control signal of a single port, certainly, also can the mask register heap etc. storage mode, if instruction translation lookaside buffer and data translation lookaside buffer will be visited this random access memory simultaneously, will produce access conflict, at this moment can be according to the Effect on Performance situation, priority processing is got finger/or the address mapping visit of data memory access.
The shared random access memory of instruction translation lookaside buffer and data translation lookaside buffer, this requires the content of every storage in instruction translation lookaside buffer and the data translation lookaside buffer identical, or one of them page table address that comprises mapping item is the subclass of another page table address that comprises mapping item, simultaneously, because the random access memory of shared single port, the Physical Page table address content that obtains when also requiring instruction translation lookaside buffer and data translation lookaside buffer respectively to have one group of register to keep separately last transform in history, if what this time address mapping used is the Physical Page table address of last transform, do not visit random access memory, then select to use the Physical Page table address content that keeps in the register, otherwise, if visited random access memory, then use the Physical Page table address of random access memory output.But it should be noted that, not directly to select to use, but will select to postpone, for example in high-speed cache, use of the mark part comparison of Physical Page table address with high-speed cache, so that determine whether cache hit, then in realization of the present invention, just allow two sources above-mentioned the Physical Page table address simultaneously and the mark of high-speed cache relatively, obtain the result whether two one expression hits, select to use which result according to whether having visited random access memory in the translation look aside buffer again.This installs used circuit and can obtain from the standard cell lib that each chip foundries (as " SMIC ", " Taiwan Semiconductor Manufacturing Co. ") openly provides.
From the above, advantage of the present invention is power consumption and the area that effectively reduces translation look aside buffer, avoided processor performance again simultaneously, and the influence of side circuit delay.The method of using among the present invention can obviously reduce instruction translation lookaside buffer and the data translation lookaside buffer visit capacity to random access memory, thereby significantly reduced the conflict that instruction translation lookaside buffer and data translation lookaside buffer are visited random access memory simultaneously, this makes instruction translation lookaside buffer and the shared single port random access memory of data translation lookaside buffer also can not influence performance of processors, has reduced the power consumption and the area of translation look aside buffer simultaneously again.In addition, the particular design of introducing thus to selecting circuit has also avoided increasing the delay of circuit.
It should be noted that at last: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to the foregoing description, those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention, and not breaking away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (9)
1. an improved virtual address translation method is characterized in that, may further comprise the steps:
A) instruction translation lookaside buffer and data translation lookaside buffer are got finger/data memory access virtual address with this and are got finger/data memory access virtual address with the last time and compare;
B) judge whether that symbolic animal of the birth year is with page table or direct mapping space? if, execution in step g), if not, carry out next step;
C) the shared single read port random access memory of instruction translation lookaside buffer and data translation lookaside buffer is accepted the inquiry to physical address;
D) instruction translation lookaside buffer and data translation lookaside buffer are preserved the physical address that conversion obtains in register;
E) instruction translation lookaside buffer and/or data translation lookaside buffer are selected two sources of the physical address of this conversion and last transform, produce two echo signals respectively;
F) two echo signals that respectively step e) produced are selected, the consequential signal that output needs;
G) do not visit random access memory, use the physical address of the last transform of preserving, execution in step e).
2. improved virtual address translation method as claimed in claim 1, it is characterized in that, in described step a), b) and g), following two kinds of situations are arranged, virtual address translation is not visited the random access memory of translation look aside buffer during to physical address, a kind of be will get to refer to that virtual address that needs that operation causes carry out conversion was got with the last time to refer to that the virtual address of finishing conversion that operation causes compares at every turn, if dropped in the same virtual page list item with last virtual address, then do not visit again random access memory, and the physical address result who directly utilizes last conversion to obtain, the virtual address translation that the data memory access causes also uses with getting and guides the identical processing procedure of sending out of virtual address translation, another kind of situation is, the virtual address that causes for instruction fetch and data accessing operation is to the conversion of physical address, if the residing address space of virtual address is direct mapping space, do not need to search the map addresses that the mapping relations list item of translation look aside buffer just can be finished, do not visit the random access memory of translation look aside buffer.
3. improved virtual address translation method as claimed in claim 1, it is characterized in that, at described step d) and e) in, if next time during address mapping the virtual address of virtual address less important conversion herewith in same page table, then use the physical address of preserving in the register, otherwise the random access memory of query translation lookaside buffer, the physical address that uses random access memory to export.
4. the device of an improved virtual address translation, comprise: the content comparators circuit and the random access memory circuit of depositing physical address that are used to deposit and compare virtual address, it is characterized in that, instruction fetch and data memory access have content comparators circuit separately, be first content comparator circuit and second content comparator circuit, and, reach instruction fetch and the shared random access memory circuit that has only a read port of data memory access to the first alternative circuit that the index that these described two content comparators circuit are relatively exported is selected; Also comprise this time get the virtual address that refers to conversion and got last time compare between the virtual address that refers to conversion judge get refer to the virtual address whether symbolic animal of the birth year with page table or directly first comparator circuit and first decision circuitry of mapping space, and compare between the virtual address of the virtual address of this secondary data memory access conversion and last secondary data memory access conversion judgment data memory access virtual address whether symbolic animal of the birth year with page table or directly second comparator circuit and second decision circuitry of mapping space; Also comprise second registers group of preserving first registers group of getting the physical address that obtains behind the finger last transform and preserving the physical address that obtains behind the data memory access last transform; The mark value that also comprises described first registers group and instruction cache is through the physical address of 1 consequential signal of the 3rd comparator circuit output and random access memory circuit output and the second alternative circuit of mark value between 1 consequential signal of the 4th comparator circuit output of instruction cache, and the mark value of described second registers group and data cache is through the physical address of 1 consequential signal of the 6th comparator circuit output and random access memory circuit output and the three alternative circuit of mark value between 1 consequential signal of the 5th comparator circuit output of data cache;
For described first relatively and first decision circuitry, if relatively judged result be very, then do not visit random access memory circuit, otherwise visit random access memory circuit; For described second relatively and second decision circuitry, if relatively judged result be very, then do not visit random access memory circuit, otherwise visit random access memory circuit; For the second alternative circuit, if first relatively and the result of first decision circuitry be very, the result who then selects the 3rd comparator circuit is as output, otherwise selects the result of the 4th comparator circuit; For the 3rd alternative circuit, if second relatively and the result of second decision circuitry be very, the result who then selects the 6th comparator circuit is as output, otherwise selects the result of the 5th comparator circuit.
5. the device of improved virtual address translation as claimed in claim 4, it is characterized in that, described single read port random access memory circuit, it is the random access memory that is used to keep physical address and associated control signal, the shared described single read port random access memory circuit of instruction translation lookaside buffer and data translation lookaside buffer, described single read port random access memory circuit priority processing are got the address mapping visit of finger or the address mapping visit of priority processing memory access.
6. the device of improved virtual address translation as claimed in claim 6 is characterized in that, described single read port random access memory circuit replaces with single read port register file circuit.
7. the device of improved virtual address translation as claimed in claim 4, it is characterized in that, described first comparator circuit and first decision circuitry, be used to generate the enable signal of visit random access memory, if front and back are got the virtual address of finger address mapping for twice not at same page table, and this time get the virtual address that refers to address mapping and do not belong to directly mapping space, just visit random access memory.
8. the device of improved virtual address translation as claimed in claim 4, it is characterized in that, described second comparator circuit and second decision circuitry, be used to generate the enable signal of visit random access memory, if front and back are carried out the virtual address of data memory access address mapping for twice not at same page table, and the virtual address of this time carrying out data memory access address mapping does not belong to directly mapping space, just visits random access memory.
9. the device of improved virtual address translation as claimed in claim 4, it is characterized in that, the described second alternative circuit uses 1 output result of the 4th comparator circuit after instruction lookaside buffer visit random access memory, otherwise selects 1 output result of the 3rd comparator circuit; Described the 3rd alternative circuit uses 1 output result of the 5th comparator circuit after data lookaside buffer visit random access memory, otherwise selects 1 output result of the 6th comparator circuit.
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| US10621090B2 (en) | 2017-01-12 | 2020-04-14 | International Business Machines Corporation | Facility for extending exclusive hold of a cache line in private cache |
| US10956337B2 (en) | 2017-01-12 | 2021-03-23 | International Business Machines Corporation | Temporarily suppressing processing of a restrained storage operand request |
| US11366759B2 (en) | 2017-01-12 | 2022-06-21 | International Business Machines Corporation | Temporarily suppressing processing of a restrained storage operand request |
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