CN100413031C - Preparing technology of metal grid/high K-grid medium and preparation method of bimetal grid CMOS - Google Patents
Preparing technology of metal grid/high K-grid medium and preparation method of bimetal grid CMOS Download PDFInfo
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- CN100413031C CN100413031C CNB2006100113683A CN200610011368A CN100413031C CN 100413031 C CN100413031 C CN 100413031C CN B2006100113683 A CNB2006100113683 A CN B2006100113683A CN 200610011368 A CN200610011368 A CN 200610011368A CN 100413031 C CN100413031 C CN 100413031C
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Abstract
The present invention provides a preparation method for metal gate/ high K gate medium, which belongs to the technical field of semiconductor integrated circuits and the manufacture thereof. The present invention has the steps that a substrate is carried out for a pre-grating processing; then, MOCVD or ALD technique is used for depositing Hf high heat K grate medium; HfN and TaN covering layers are orderly deposited on the deposited hafnium high heat K grating medium layer by utilizing a PVD or CVD method; next, high temperature anneal is carried out on TaN/HfN/Hf high heat K grate medium structures by utilizing a rapid thermal anneal method. The TaN/HfN structures and a high temperature process can obtain high reliability under the ensured condition of low ETO (which is smaller than 1 nm); subsequently, the TaN and the HfN covering layers in the TaN/HfN/Hf high heat K gate medium structures are removed by utilizing wet processing; a metal gate electrode layer with appropriate work functions is prepared on the Hf high heat K gate medium layer with removed TaN/HfN covering layers; finally, a metal gate/ high K gate medium structure with adjustable metal gate work functions, high mobility, high reliability and ECO which is smaller than 1 nm is formed.
Description
Technical field
The invention belongs to semiconductor integrated circuit and manufacturing technology field thereof, relate to the high K dielectric material of metal gate and Hf base as the CMOS transistor of grid and the manufacture method of integrated circuit thereof.
Background technology
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide-semiconductor field effect transistor (metal oxide semiconductor field effect transistor is called for short MOS transistor).Since MOS transistor was invented, its physical dimension was constantly being dwindled always, and its characteristic size has entered inferior 50 nanometer range at present.Under this yardstick, various reality and basic restriction and technological challenge begin to occur, and further dwindling of device size just becomes more and more difficult.Wherein, in the preparation of MOS transistor device and circuit, tool is challenging be the traditional cmos device in the process of dwindling because polysilicon/SiO
2Or the SiON gate oxide dielectric thickness high grid leakage current that reduces to bring.For this reason, the solution that has proposed is to adopt metal gate and high-K gate dielectric to substitute traditional heavily doped polysilicon grid and SiO
2(or SiON) gate medium.According to integrated circuit technique development course figure, the practical application of metal gate, high-K gate dielectric will be after inferior 65nm technology.And the equivalent oxide thickness (EOT) of inferior 65nm specification requirement gate oxide is less than 1nm.But in the integrated technical scheme of the present relevant metal gate that proposes and high-K gate dielectric and CMOS, can satisfy the requirement of the technical indicator of high-performance, high reliability and EOT＜1nm simultaneously, also have certain difficulty.Specifically, on the one hand, if will obtain high reliability and high-performance, usually need to experience a high-temperature technology engineering after the high-K gate dielectric layer deposit, but the high-temperature technology process tends to cause the remarkable increase of EOT value, and this makes the equivalent oxide thickness (EOT) of MOS device be difficult to satisfy the index request of EOT＜1nm; On the other hand, after the high-K gate dielectric layer deposit, avoid the high-temperature technology process, before the deposit high-K gate dielectric layer, adopt the interface engineering technology simultaneously, can satisfy the performance requirement of EOT＜1nm and high mobility simultaneously, but reliability performance is difficult to satisfy the technology demands of applications.Therefore, prior art can't satisfy the demand of low pressure, low-power consumption body silicon CMOS device and circuit application.
Summary of the invention
The preparation method who the purpose of this invention is to provide a kind of metal gate/high-K gate dielectric technical module can satisfy the demand of low pressure, low-power consumption body silicon CMOS device and circuit application.
The preparation method of a kind of metal gate/high-K gate dielectric structure, its step comprises:
1) deposit high-K gate dielectric layer promptly carries out pre-grid technique to substrate and handles, and utilizes MOCVD or ALD deposition techniques Hf base high-K gate dielectric then;
2) form TaN/HfN/Hf base high-K gate dielectric structure, promptly on the Hf of deposit base high-K gate dielectric layer, utilize PVD or CVD method sequential deposit HfN, TaN cover layer;
3) utilize the rapid thermal annealing method that TaN/HfN/Hf base high-K gate dielectric structure is carried out high annealing; The temperature range of TaN/HfN/Hf base high-K gate dielectric structure being carried out high annealing is: 900 ℃-1100 ℃.
4) at the base of the TaN/HfN/Hf behind high annealing high-K gate dielectric structure, in order to NH
4OH solution is that the solution wet method of main body is removed TaN cover layer wherein, removes wherein HfN cover layer with dilution HF solution wet method, obtains Hf base high-K gate dielectric layer;
5) in the above-mentioned suitable metal gate electrode layer of preparation work function on the tectal Hf base of the TaN/HfN high-K gate dielectric layer, the formation metal gate/high-K gate dielectric structure got rid of.
In the step 4) in order to NH
4OH solution is that the solution wet method of main body is removed TaN cover layer wherein, specifically adopt 120 ℃-180 ℃ with NH
4OH solution is that the hot solution of main body was boiled 1～10 minute, etches away the TaN cover layer in the TaN/HfN/Hf base high-K gate dielectric structure.
Remove wherein HfN cover layer with dilution HF solution wet method in the step 4), specifically adopt at HF: H
2O=1: soaked in the dilute hydrofluoric acid of 100 (volume ratios) 1～10 minute, and removed the HfN cover layer in the HfN/Hf base high-K gate dielectric structure.
The preparation method of a kind of bimetal gate CMOS, its step comprises:
1) adopts standard CMOS process to prepare in the dual gate CMOS device technology process, utilize SiO
2Or SiON gate dielectric layer and polysilicon electrode sacrificial layer technology prepare high-K gate dielectric layer, promptly finishes SiO
2After the grid structure preparation that gate dielectric layer and polysilicon electrode are formed, etching is removed the structural SiO of COMS grid
2Or sacrifice layers such as SiON gate dielectric layer and polysilicon electrode, the Si substrate is carried out pre-grid technique handle, and then utilize MOCVD or ALD deposition techniques Hf base high-K gate dielectric;
2) form TaN/HfN/Hf base high-K gate dielectric structure, promptly on the Hf of deposit base high-K gate dielectric layer, utilize PVD or CVD method sequential deposit HfN, TaN cover layer;
3) utilize the rapid thermal annealing method that TaN/HfN/Hf base high-K gate dielectric structure is carried out high annealing; The temperature range of TaN/HfN/Hf base high-K gate dielectric structure being carried out high annealing is: 900 ℃-1100 ℃.
4) at the base of the TaN/HfN/Hf behind high annealing high-K gate dielectric structure, in order to NH
4OH solution is that the solution wet method of main body is removed TaN cover layer wherein, removes wherein HfN cover layer with dilution HF solution wet method, obtains Hf base high-K gate dielectric layer;
5) in the above-mentioned suitable dual-metal gate electrode layer of preparation work function on the tectal Hf base of the TaN/HfN high-K gate dielectric layer, the formation bimetal gate/high-K gate dielectric structure got rid of;
6) enter conventional CMOS later process, make bimetal gate/high-K gate dielectric CMOS.
Technique effect of the present invention: the present invention utilizes the CVD technology to prepare Hf base high-K gate dielectric layer; At deposit TaN/HfN cover layer on Hf base high-K gate dielectric layer again after the deposit of Hf base high-K gate dielectric layer; Utilize rapid thermal annealing (RapidThermal Anneal, RTP) technology is carried out high temperature (900 ℃-1100 ℃) heat treatment to being stamped the tectal Hf base of TaN/HfN high-K gate dielectric, because the tectal effect of TaN/HfN, this pyroprocess can guarantee that low EOT (under＜1nm) the condition, obtains high reliability; Then, utilize harmless wet-etching technology to remove the TaN/HfN cover layer of deposit on the Hf base high-K gate dielectric layer; Utilize the adjustable bimetal gate preparation technology of work function, behind the new metal gate electrode layer of deposit, form finally that the metal gate work function can be modulated, EOT＜1nm, have the metal gate/high-K gate dielectric structure of high mobility and high reliability.
The present invention is when satisfying high-performance, high reliability, work function and performance index such as can modulating, both can adopt CMOS process compatible with traditional PN junction source/drain structure, also can with the CMOS process compatible that adopts novel schottky junction source/drain structure, flexibility with bigger process choice.
Description of drawings
Below in conjunction with accompanying drawing, the present invention is made detailed description.
Fig. 1 is the cross-sectional view of bimetal gate/high-K gate dielectric of the present invention;
The processing step schematic diagram that Fig. 2 determines for active area by injecting N type impurity P or As at the N well region, forms the N trap;
Fig. 3 is the processing step schematic diagram that sacrifice layer grid structure forms, at the SiO of Si substrate difference deposit as sacrifice layer
2Behind dielectric layer and the polysilicon electrode layer, photoetching forms sacrifice layer grid structure polysilicon/SiO as shown in the figure
2
Fig. 4, Fig. 5 are respectively NMOS and the PMOS source-and-drain junction injects the processing step schematic diagram that forms, and wherein PR is the photoresist mask, and the source-and-drain junction of NMOS is by N type impurity such as P or As injection formation, and the source-and-drain junction of PMOS injects by p type impurity such as B and forms;
Fig. 6 is the cmos device structural representation that utilizes after traditional cmos process prepares finish grid and source-and-drain junction;
Fig. 7 removes SiO on the cmos device grid structure for etching
2The processing step schematic diagram of sacrifice layer such as gate dielectric layer and polysilicon electrode;
Fig. 8 is the processing step schematic diagram of Hf base high-K gate dielectric layer and HfN, TaN blanket deposition;
Fig. 9 is for through behind the high-temperature annealing process, utilizes wet processing to remove the tectal processing step schematic diagram of HfN, TaN on the Hf base high-K gate dielectric layer;
Figure 10 is the processing step schematic diagram of dual-metal gate electrode layer technology of preparing;
Figure 11 is the processing step schematic diagram of conventional cmos later process.
Wherein, 1, the source-and-drain junction of 2-NMOS; The channel region of 3-NMOS; 4, the source-and-drain junction of 5-PMOS; The channel region of 6-PMOS; The gate dielectric layer of 7-NMOS and PMOS; The side wall of the gate dielectric layer structure of 9-NMOS and PMOS; 8, the gate electrode layer of 10-NMOS and PMOS; The grid of 11-NMOS and PMOS and source drain contact through hole and local interconnecting parts; A 12-oxygen isolated area; 13-polysilicon/SiO
2
Embodiment
The profile of bimetal gate proposed by the invention/high-K gate dielectric cmos device as shown in Figure 1.Comprise: the source-drain area 1,4 of NMOSFET and PMOSFET; Shallow junction region 2,5 is leaked in the source of NMOSFET and PMOSFET; The gate dielectric layer 7 of NMOSFET and PMOSFET; The gate electrode layer 8,10 of NMOSFET and PMOSFET; The side wall separator 9 of NMOSFET and PMOSFET and an oxygen separator 12.
Metal gate of the present invention/high-K gate dielectric preparation technology's concrete steps are as follows:
At first be Semiconductor substrate to be carried out pre-grid clean, utilize CVD (comprising MOCVD and ALD) technology to prepare Hf base high-K gate dielectric layer then; At deposit TaN/HfN cover layer on Hf base high-K gate dielectric layer again after the deposit of Hf base high-K gate dielectric layer; Utilize rapid thermal annealing (Rapid Thermal Anneal, RTP) technology is carried out the processing of high temperature (＞900 ℃) to being stamped the tectal Hf base of TaN/HfN high-K gate dielectric, then, utilize harmless wet-etching technology to remove the TaN/HfN cover layer of deposit on the Hf base high-K gate dielectric layer; Utilize the adjustable bimetal gate preparation technology of work function, behind the new metal gate electrode layer of deposit, form finally that the metal gate work function can be modulated, EOT＜1nm, have the metal gate/high-K gate dielectric structure of high mobility and high reliability.
Described Semiconductor substrate can be traditional body Si substrate, also can be SOI (semiconductor on insulator) substrate.
Before the deposit of Hf base gate dielectric layer, with adopt dilution HF last soak pre-grid cleaning or other novel pre-grid clean process Si substrates, but do not adopt the surfaces nitrided technology of Si that can not cause that the channel carrier mobility significantly descends.
Hf base gate dielectric layer need adopt the CVD method that has developed to comprise MOCVD and the preparation of ALD method, and the TaN/HfN cover layer can adopt the CVD or the PVD method that have developed to form, and wherein HfN and TaN layer thickness are respectively at 50～100nm and 100～200nm.
The optimal process that TaN/HfN/Hf base high-K gate dielectric structure is carried out high annealing utilizes the RTP method at 950～1100 ℃ of rapid thermal anneal process that carry out 1～30 second.
Utilize wet processing remove the tectal chemical solution of TaN preferably adopt be heated to 120 ℃-180 ℃ with NH
4OH solution is the SCl solution of main body, and wet processing is removed the tectal chemical solution of HfN and preferably adopted HF: H
2O=1: the method that the HF solution of 100 (volume ratios) dilution removes HfN.
The metal gate deposit can be selected the technology of sputter, CVD and FUSI process deposit simple metal, metal nitride and metal silicide.
Be applicable to that with metal gate/high-K gate dielectric process technology scheme back grid (Gate-Last) CMOS technology is an example, its preparation CMOS transistor reaches the specific implementation method by its integrated circuit that constitutes, and, be may further comprise the steps to shown in Figure 11 by Fig. 2:
The used substrate of the present invention is a body Si material, adopts single trap (N trap) prepared, as shown in Figure 2;
Of the present invention next step as shown in Figure 3, adopt conventional cmos technology (photoetching/etching or LOCOS technology) to make device active region, and growth sacrifice layer gate oxide and sacrifice layer polygate electrodes layer.Wherein, the sacrifice layer gate oxide is silicon dioxide or SiON, and its thickness is 20～50 dusts, and the sacrifice layer polysilicon is the polysilicon of LPCVD, and its thickness is 200nm～400nm;
Utilize the photoetching and the etching technics of the CMOS technology of standard, form gate figure;
Of the present invention next step as shown in Figure 4, in the P district, the source that utilizes ion implantation technique to carry out NMOS leak to mix is injected;
In the N district, the source that utilizes ion implantation technique to carry out PMOS is leaked to mix and is injected, as shown in Figure 5;
Of the present invention next step as shown in Figure 6, with the side wall medium layer silicon nitride of LPCVD deposit 400～800 dusts, then using back quarter (etch-back) technology is the silicon nitride side wall of 350～750 dusts at gate electrode both sides formation width;
Of the present invention next step as shown in Figure 7, utilize wet processing, remove sacrifice layer polysilicon electrode layer and SiO
2Or SiON dielectric layer;
As shown in Figure 8, utilize pre-grid cleaning to clean after, utilize CVD prepared Hf base high-K gate dielectric layer after, utilize CVD or PVD process sequence deposit HfN/TaN electrode layer again.Then carry out 900 ℃-1100 ℃ high annealing, improve the quality of high-K gate dielectric layer;
As shown in Figure 9, utilize wet processing that TaN and HfN layer are etched away respectively respectively; Promptly utilize wet processing remove the tectal chemical solution of TaN preferably adopt be heated to 120 ℃-180 ℃ with NH
4OH solution is the SCl solution of main body, and wet processing is removed the tectal chemical solution of HfN and preferably adopted HF: H
2O=1: the method that the HF solution of 100 (volume ratios) dilution removes HfN.
Of the present invention next step as shown in figure 10, utilize bimetal gate preparation technology, respectively at NMOS and PMOS zone deposit N type and P type metal gate electrode layer; Utilize photoetching and etching technics or CMP technology to form the bimetal gate graphic structure;
As shown in figure 11, adopt the processing step of CMOS later process, comprise deposit passivation layer, opening contact hole and metallization etc., carry out through hole and local interconnection process, those of ordinary skill in the art are very familiar to this, are common process.So far, finished the embodiment of the invention the institute in steps.
Above-mentioned is detailed description for most preferred embodiment processing step of the present invention; but obviously; the skilled person in the technology of the present invention field can make the change of form and content aspect unsubstantiality and not depart from the scope that institute of the present invention essence is protected according to above-mentioned step; therefore, the present invention is not limited to above-mentioned concrete form and details.
Claims (4)
1. the preparation method of metal gate/high-K gate dielectric structure, its step comprises:
1), promptly substrate is carried out utilizing MOCVD or ALD deposition techniques Hf base high-K gate dielectric layer after pre-grid technique handles at substrate deposit high-K gate dielectric layer;
2) form TaN/HfN/Hf base high-K gate dielectric structure, promptly on the Hf of deposit base high-K gate dielectric layer, utilize PVD or CVD method sequential deposit HfN, TaN cover layer;
3) utilize the rapid thermal annealing method that TaN/HfN/Hf base high-K gate dielectric structure is carried out high annealing, the temperature range of above-mentioned high annealing is 900 ℃-1100 ℃;
4) at the base of the TaN/HfN/Hf behind high annealing high-K gate dielectric structure, in order to NH
4OH solution is that the solution wet method of main body is removed TaN cover layer wherein, removes wherein HfN cover layer with dilution HF solution wet method, obtains Hf base high-K gate dielectric layer;
5) in the above-mentioned suitable metal gate electrode layer of preparation work function on the tectal Hf base of the TaN/HfN high-K gate dielectric layer, the formation metal gate/high-K gate dielectric structure got rid of.
2. the preparation method of metal gate as claimed in claim 1/high-K gate dielectric structure is characterized in that: in the step 4) in order to NH
4OH solution is that the solution wet method of main body is removed TaN cover layer wherein, specifically adopt 120 ℃-180 ℃ with NH
4OH solution is that the hot solution of main body was boiled 1～10 minute, etches away the TaN cover layer in the TaN/HfN/Hf base high-K gate dielectric structure.
3. the preparation method of metal gate as claimed in claim 1 or 2/high-K gate dielectric structure is characterized in that: remove wherein HfN cover layer with dilution HF solution wet method in the step 4), specifically adopt at volume ratio HF: H
2O=1: soaked in 100 the dilute hydrofluoric acid 1～10 minute, and removed the HfN cover layer in the HfN/Hf base high-K gate dielectric structure.
4. the preparation method of a bimetal gate CMOS, its step comprises:
1) adopts standard CMOS process to prepare in the dual gate CMOS device technology process, utilize SiO
2Or SiON gate dielectric layer and polysilicon electrode sacrificial layer technology prepare high-K gate dielectric layer, promptly finishes SiO
2After the grid structure preparation that gate dielectric layer and polysilicon electrode are formed, etching is removed the structural SiO of CMOS grid
2Or sacrifice layers such as SiON gate dielectric layer and polysilicon electrode, substrate is carried out pre-grid technique handle, and then utilize MOCVD or ALD deposition techniques Hf base high-K gate dielectric;
2) form TaN/HfN/Hf base high-K gate dielectric structure, promptly on the Hf of deposit base high-K gate dielectric layer, utilize PVD or CVD method sequential deposit HfN, TaN cover layer;
3) utilize the rapid thermal annealing method that TaN/HfN/Hf base high-K gate dielectric structure is carried out high annealing, the temperature range of above-mentioned high annealing is 900 ℃-1100 ℃;
4) at the base of the TaN/HfN/Hf behind high annealing high-K gate dielectric structure, in order to NH
4OH solution is that the solution wet method of main body is removed TaN cover layer wherein, removes wherein HfN cover layer with dilution HF solution wet method, obtains Hf base high-K gate dielectric layer;
5) in the above-mentioned suitable dual-metal gate electrode layer of preparation work function on the tectal Hf base of the TaN/HfN high-K gate dielectric layer, the formation bimetal gate/high-K gate dielectric structure got rid of;
6) enter conventional CMOS later process, make bimetal gate/high-K gate dielectric CMOS.
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| CN101800196B (en) * | 2009-02-09 | 2012-01-25 | 中国科学院微电子研究所 | Method for adjusting work function of double metal gate |
| CN101656208B (en) * | 2009-09-25 | 2011-11-16 | 中国科学院微电子研究所 | Method for selectively removing TaN metal gate electrode layer |
| CN102074469B (en) * | 2009-11-25 | 2012-04-11 | 中国科学院微电子研究所 | Method for adjusting work function of metal gate of PMOS (P-channel metal oxide semiconductor) device |
| CN102280376B (en) | 2010-06-08 | 2013-01-02 | 中国科学院微电子研究所 | Method for integrating double metal gate double high dielectric for CMOS device |
| CN102468221B (en) * | 2010-11-11 | 2014-10-22 | 中国科学院微电子研究所 | Method for preparing contact hole in CMOS device by adopting gate-last process |
| CN102064103A (en) * | 2010-12-02 | 2011-05-18 | 上海集成电路研发中心有限公司 | High-k gate dielectric layer manufacture method |
| CN103137460B (en) * | 2011-11-23 | 2016-02-10 | 中国科学院微电子研究所 | Molecular scale interface SiO2Forming and controlling method |
| CN105206523A (en) * | 2015-10-14 | 2015-12-30 | 上海华力微电子有限公司 | Method for manufacturing high-K dielectric layer |
| CN112420502A (en) * | 2020-11-18 | 2021-02-26 | 上海华力集成电路制造有限公司 | Method for manufacturing high-dielectric-constant metal gate MOS transistor |
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