CN100410748C - Liquid crystal display - Google Patents
Liquid crystal display Download PDFInfo
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- CN100410748C CN100410748C CNB2006101317921A CN200610131792A CN100410748C CN 100410748 C CN100410748 C CN 100410748C CN B2006101317921 A CNB2006101317921 A CN B2006101317921A CN 200610131792 A CN200610131792 A CN 200610131792A CN 100410748 C CN100410748 C CN 100410748C
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- source electrode
- driver
- electrode driver
- lcd
- clock controller
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Abstract
The invention relates to the liquid crystal display which includes one base plate, one circuit board, one clock controller, one liquid crystal display area, one control circuit, and many source electrode drivers. The clock controller is set on the circuit board to supply one clock signal impulse. The control circuit is used to generate one selective signal. The many source electrode drivers are used to transmit one data signal to the liquid crystal display area according to the clock signal impulse. One of them is joint coupling with the clock controller and the control circuit to input clock signal impulse generated by the clock controller or the one outputted by the previous source electrode driver according to the selective signal.
Description
Technical field
The present invention relates to a kind of LCD, especially refer to a kind of LCD of adjusting the clock signal pulse source of source electrode driver.
Background technology
Function advanced person's display gradually becomes the valuable feature of consumption electronic product now, and wherein LCD has become the display that various electronic equipments such as mobile phone, PDA(Personal Digital Assistant), digital camera, computer screen or the widespread use of mobile computer screen institute have the high-definition color screen gradually.
See also Fig. 1, Fig. 1 is the synoptic diagram of prior art LCD 10.LCD 10 comprises a substrate 12, multiple source driver 16, a plurality of gate drivers 18 and a liquid crystal display district 20.Source electrode driver 16a-16h, gate drivers 18 and liquid crystal display district 20 are all and are arranged on the substrate 12, and printed circuit board (PCB) 22 is provided with clock controller 14.Multiple source driver 16a-16h is serial connection (cascade connection), and wherein first order source electrode driver 16a is for being coupled to clock controller 14.When the clock signal pulse that clock controller 14 produces is sent to a plurality of gate drivers 18, a plurality of gate drivers 18 can produce sweep signal to liquid crystal display district 20, at the same time, 14 of clock controllers can send clock signal pulse to first order source electrode driver 16a, and the digital data signal that first order source electrode driver 16a will receive clock controller 14 be transmitted, and clock signal pulse is reached the source electrode driver 16b of next stage.Similarly, the digital data signal that next stage source electrode driver 16b meeting receive clock controller 14 is transmitted is sent to clock signal pulse next stage source electrode driver 16c again, and same way is sent to afterbody source electrode driver 16h up to clock signal pulse.When liquid crystal display district 20 receives sweep signal, will be according to the digital data signal display image of source electrode driver 16a-16h.
See also Fig. 2, Fig. 2 is the source electrode driver 26a-26h of LCD of another prior art and the synoptic diagram of clock controller 24.The LCD that is different from Fig. 1, the clock controller 24 of the LCD of Fig. 2 directly and each source electrode driver 26a-26h couple, so the time of the digital data signal that each source electrode driver 26a-26h receive clock controller 24 produces is directly to be controlled by clock controller 24, but not transmits clock signal pulse successively by source electrode driver 26a-26h.But such configuration certainly will need to increase extra flexible printed wiring board (flexible printed circuitboard, FPC) come to be electrically connected with the clock controller 24 that is arranged on the printed circuit board (PCB), and printed circuit board (PCB) also must increase length, so will cause complicated conductor configurations and increase production cost.
Summary of the invention
One embodiment of the invention are for providing a kind of LCD, and it comprises a substrate, a circuit board, a clock controller, a liquid crystal display district, a control circuit and multiple source driver.This clock controller is used to provide a clock signal pulse for being arranged on this circuit board.This control circuit is selected signal for being used for producing one.This multiple source driver is to be used for exporting a data-signal to this liquid crystal display district according to the clock signal pulse that this clock controller produces.The one source pole driver of this multiple source driver is coupled to this clock controller and this control circuit, and this one source pole driver selects signal to select the clock signal pulse of this clock controller generation of input or the clock signal pulse of last source electrode driver output according to this.
According to one embodiment of the invention, this multiple source driver is serial connection.
According to another embodiment of the present invention, this multiple source driver comprises one first source electrode driver group and one second source electrode driver group, and the source electrode driver of this first source electrode driver group is serial connection, and the source electrode driver of this second source electrode driver group is serial connection.
Description of drawings
Fig. 1 is the synoptic diagram of prior art LCD.
Fig. 2 is the source electrode driver of LCD of another prior art and the synoptic diagram of clock controller and clock controller.
Fig. 3 A is the synoptic diagram of the LCD of one embodiment of the invention.
Fig. 3 B is the synoptic diagram of the LCD of another embodiment of the present invention
Fig. 4 is the side view of LCD of the present invention.
Fig. 5 is the synoptic diagram of the LCD 200 of another embodiment of the present invention.
The main element symbol description
100,200 LCD, 102,202 substrates
104,204 clock controller 106a-106h source electrode drivers
108,208 gate drivers, 110,210 liquid crystal display districts
226a-226d source electrode driver 112,212a-b control circuit
114,214 circuit boards, 118,218 flexible circuit boards
The 216a-216d source electrode driver
Embodiment
See also Fig. 3 A and Fig. 4.Fig. 3 A is the synoptic diagram of the LCD 100 of one embodiment of the invention, and Fig. 4 is the side view of LCD 100.LCD 100 comprises a substrate 102, a clock controller 104, multiple source driver 106a-106h, a plurality of gate drivers 108, a liquid crystal display district 110 and a control circuit 112.At Fig. 3 A, though only represent eight source electrode driver 106a-106h and four gate drivers 108, the number of source electrode driver and gate drivers can be adjusted according to the size of different LCD.Multiple source driver 106a-106h and a plurality of gate drivers 108 are for being arranged at (Chip on film on the flexible circuit board, COF) 118, or be arranged on the glass substrate 102 (Chip of glass, COG) again by flexible circuit board 118 to be electrically connected with circuit board 114.104 of clock controllers are arranged on the circuit board 114, and clock controller 104 is coupled to source electrode driver 106a-106c and a plurality of gate drivers 108.Liquid crystal display district 110 comprises a plurality of pixels (pixel).As shown in Figure 4.Circuit board 114 and liquid crystal display district 110 be for being arranged at the both sides of substrate 102 respectively, and be arranged at clock controller 104 on the circuit board 114 for to reach the purpose that is electrically connected by flexible circuit board 118 with source electrode driver 106 and gate drivers 108.
In Fig. 3 A, source electrode driver 106a-106h is for becoming serial connection, and only source electrode driver 106a, 160b, 106c are coupled to clock controller 104.That is to say that the source of the clock signal pulse of source electrode driver 106a, 106b, 106c can come from the output of the clock controller 104 or the source electrode driver of previous stage.When the clock signal pulse that clock controller 104 produces is sent to a plurality of gate drivers 108, a plurality of gate drivers 108 can produce sweep signal to liquid crystal display district 110, make the transistor turns of pixel of liquid crystal display district 110 each row, at the same time, 104 of clock controllers can send clock signal pulse to first order source electrode driver 106a, and the digital data signal that first order source electrode driver 106a will receive clock controller 104 be transmitted, and clock signal pulse is reached the source electrode driver 106b of next stage.Similarly, the digital data signal that next stage source electrode driver 106b meeting receive clock controller 104 is transmitted is sent to clock signal pulse next stage source electrode driver 106c again, same way is sent to afterbody source electrode driver 106h up to clock signal pulse, the pixel that final liquid crystal display district 110 receives data-signal to a permutation that source electrode driver 106a-106h exported makes it be charged to required separately voltage, to show different gray scales.
Again, in the utilization of reality, the quantity of the source electrode driver that the number and the control circuit of control circuit connected can be decided according to the actual design demand.That is LCD can be provided with the control circuit more than two, and the quantity of the source electrode driver that control circuit connected also can increase along with the number of control circuit.In addition, control circuit also can be integrated in source electrode driver in, but not be independent of source electrode driver outside.In another embodiment, shown in Fig. 3 B, can not be connected in series between source electrode driver 106a and the 106b, to reduce the cost expenditure.
See also Fig. 5, Fig. 5 is the synoptic diagram of the LCD 200 of another embodiment of the present invention.LCD 200 comprises a substrate 202, a clock controller 204, multiple source driver 216a-216d, 226a-226d, a plurality of gate drivers 208, a liquid crystal display district 210 and a plurality of control circuit 212a, 212b.At Fig. 5, though only represent eight source electrode driver 216a-216d, 226a-226d and four gate drivers 208, the number of source electrode driver and gate drivers can be adjusted according to the size of different LCD.Multiple source driver 216a-216d, 226a-226d and a plurality of gate drivers 208 are for being arranged at (Chip on film on the flexible circuit board, COF), or be arranged on the glass substrate 202 (Chip of glass, COG) again by flexible circuit board to be electrically connected with circuit board 214.Be same as aforesaid embodiment, circuit board 214 is the both sides that are arranged at substrate 202 respectively with liquid crystal display district 210.But, the LCD 200 of present embodiment is with LCD 100 differences of Fig. 1, LCD 200 that is to say that for the mode of adopting the both-end driving drives the multiple source driver multiple source driver is divided into the first source electrode driver group and the second source electrode driver group.The multiple source driver 216a-216d of the first source electrode driver group is serial connection, and the multiple source driver 226a-226d of the second source electrode driver group also is serial connection.Source electrode driver 216a, the 216b of the first source electrode driver group are coupled to clock controller 204, and source electrode driver 226a, the 226b of the second source electrode driver group also are coupled to clock controller 204.The clock signal pulse that clock controller 204 produces is drive source driver 216a, 226a simultaneously, and source electrode driver 216a, 226a are behind the digital data signal that receive clock controller 204 transmits, clock signal pulse can be exported to source electrode driver 216b, the 226b of next stage, after source electrode driver 216b-216d, 226b-226d drive in regular turn again.In addition, control circuit 212a, 212b are for being respectively coupled to source electrode driver 216b, 226b, and it selects signal to source electrode driver 216b, 226b for being used for producing one.Source electrode driver 216b, 226b can select signal deciding to select the clock signal pulse of input clock controller 204 generations or the clock signal pulse that last source electrode driver is exported according to this.For instance, if this selection signal is positioned at high-voltage level, then source electrode driver 216b, 226b only can just understand the digital data signal that receive clock controller 204 is transmitted behind the clock signal pulse that receive clock controller 204 is sent.Relatively, if this selection signal is positioned at low voltage level, then source electrode driver 216b, 226b only can just understand the digital data signal that receive clock controller 204 is transmitted behind the clock signal pulse that reception previous stage source electrode driver 216a, 226a are sent.That is to say that the selection signal of suitably adjusting control circuit 212a, 212b output can be so that source electrode driver 216a, 226a dynamically determine the source of clock signal pulse.
Again, in the utilization of reality, the quantity of the source electrode driver that the number and the control circuit of control circuit connected can be decided according to the actual design demand.One control circuit also can only be set in the first source electrode driver group or the second source electrode driver group; Or in the first source electrode driver group or the second source electrode driver group, more than one control circuit is set respectively, and the quantity of the source electrode driver that control circuit connected also can increase along with the number of control circuit.
Compared to prior art, the invention provides a kind of LCD of adjusting the clock signal pulse source of source electrode driver, make the clock signal pulse that the source electrode driver be connected in control circuit selectively sends in the receive clock controller or the clock signal pulse of previous stage source electrode driver output, just understand the digital data signal that the receive clock controller is transmitted.Such configuration will help the design flexibility of source electrode driver.
Though the present invention with preferred embodiment openly as above; right its is not that any those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention in order to qualification the present invention; can change and modification, so protection scope of the present invention is as the criterion with the claim institute restricted portion that is proposed.
Claims (12)
1. LCD, it comprises:
One substrate;
One circuit board is arranged on this substrate;
One liquid crystal display district is arranged on this substrate;
One clock controller is arranged on this circuit board, is used to provide a clock signal pulse;
One control circuit is used for producing one and selects signal; And
The multiple source driver, be used for exporting a data-signal to this liquid crystal display district, the one source pole driver of this multiple source driver is coupled to this clock controller and this control circuit, and this one source pole driver selects signal to select the clock signal pulse of this clock controller generation of input or the clock signal pulse of last source electrode driver output according to this.
2. LCD as claimed in claim 1, wherein this multiple source driver is for being arranged on the flexible printed wiring board.
3. LCD as claimed in claim 1, wherein this multiple source driver is for being arranged on this substrate.
4. LCD as claimed in claim 3, wherein this multiple source driver is for being electrically connected with this clock controller by a flexible circuit board.
5. LCD as claimed in claim 1, wherein this multiple source driver is serial connection.
6. LCD as claimed in claim 1, wherein this multiple source driver comprises one first source electrode driver group and one second source electrode driver group, the source electrode driver of this first source electrode driver group is serial connection, and the source electrode driver of this second source electrode driver group is serial connection.
7. LCD as claimed in claim 1, it also comprises a plurality of gate drivers, is coupled to this clock controller, is used for producing the one scan signal.
8. LCD as claimed in claim 7, wherein these a plurality of gate drivers are for being arranged on this substrate.
9. LCD as claimed in claim 7, wherein these a plurality of gate drivers are for being electrically connected with this clock controller by a flexible circuit board.
10. LCD as claimed in claim 1, wherein this clock controller is to be used for providing a digital data signal to this source electrode driver when the one source pole driver of this multiple source driver receives the clock signal pulse of this clock controller generation.
11. LCD as claimed in claim 1, wherein this clock controller is to be used for providing a digital data signal to this source electrode driver when the one source pole driver of this multiple source driver receives the clock signal pulse of this last source electrode driver output.
12. LCD as claimed in claim 1, wherein this substrate is a glass material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101317921A CN100410748C (en) | 2006-10-12 | 2006-10-12 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101317921A CN100410748C (en) | 2006-10-12 | 2006-10-12 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1949036A CN1949036A (en) | 2007-04-18 |
| CN100410748C true CN100410748C (en) | 2008-08-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101317921A Expired - Fee Related CN100410748C (en) | 2006-10-12 | 2006-10-12 | Liquid crystal display |
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| Country | Link |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295476B (en) * | 2007-04-25 | 2011-10-12 | 联咏科技股份有限公司 | Panel display equipment and source driver thereof |
| CN103927962B (en) * | 2013-12-31 | 2017-02-08 | 厦门天马微电子有限公司 | Driving circuit and method of display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08305316A (en) * | 1995-05-12 | 1996-11-22 | Sharp Corp | Image display device |
| JPH11202836A (en) * | 1998-01-09 | 1999-07-30 | Seiko Epson Corp | Driving method of electrooptic device, electrooptic device and projection display device |
| JP2001075543A (en) * | 2000-07-18 | 2001-03-23 | Sony Corp | Liquid crystal display |
| CN1652195A (en) * | 2004-01-14 | 2005-08-10 | 三星电子株式会社 | Display device |
| US20060066373A1 (en) * | 2004-09-24 | 2006-03-30 | Chih-Hsiang Yang | Method for reducing electromagnetic interference in a clock generating circuit |
-
2006
- 2006-10-12 CN CNB2006101317921A patent/CN100410748C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08305316A (en) * | 1995-05-12 | 1996-11-22 | Sharp Corp | Image display device |
| JPH11202836A (en) * | 1998-01-09 | 1999-07-30 | Seiko Epson Corp | Driving method of electrooptic device, electrooptic device and projection display device |
| JP2001075543A (en) * | 2000-07-18 | 2001-03-23 | Sony Corp | Liquid crystal display |
| CN1652195A (en) * | 2004-01-14 | 2005-08-10 | 三星电子株式会社 | Display device |
| US20060066373A1 (en) * | 2004-09-24 | 2006-03-30 | Chih-Hsiang Yang | Method for reducing electromagnetic interference in a clock generating circuit |
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|---|---|
| CN1949036A (en) | 2007-04-18 |
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Granted publication date: 20080813 Termination date: 20201012 |