CN100407869C - Apparatus for realizing down idle cycle - Google Patents

Abstract

A device for realizing downlink idle period consists of IPDL insertion module for inserting idle period in data signal of cell circuit according to indication signal, random number generating module for calculating out random number as per random number seed sent from IPDL calculation module and for sending random number back to IPDL calculation module, IPDL calculation module for calculating position of idle period and for outputting indication signal of idle period to IPDL insertion module within idle period.

Description

A kind of device of realizing down idle cycle

Technical field

The present invention relates to the field of locating technology in Wideband Code Division Multiple Access (WCDMA) (WCDMA) system, particularly a kind of device of realizing down idle cycle (IPDL).

Background technology

Down link time of advent to be measured is poor, and (Observed Time Difierence Of Arrival, ODTOA) method is one of localization method of standard in the Wideband Code Division Multiple Access (WCDMA).Down link ODTOA method is based on the localization method of subscriber equipment (UE), its basic principle is utilized the radio wave propagation time deviation that obtains a plurality of base stations (Node B) emission in UE observation exactly, determines the position of object UE in conjunction with the information such as real time deviation of Node B geographical position coordinates, each downstream signal emission of measuring.Adopt the ODTOA method can run into the audibility problem of bringing owing to near-far interference, promptly when UE was very near apart from certain Node B, this UE was difficult to listen to the signal of other Node B, to such an extent as to can't finish location survey.Therefore, in 3rd Generation Partnership Project (3GPP) standard, introduced down idle cycle (IPDL) mechanism, the principle of IPDL mechanism is exactly the emission of closing main plot all channels of NodeB in certain predetermined pseudorandom in the time period, to improve the monitoring ability of UE to other Node B signal, the above-mentioned time period of closing main plot Node B signal emission is exactly idling cycle (idle period).

Idling cycle has two kinds of patterns: burst mode and continuous mode.Burst mode is meant that a plurality of idling cycles are arranged in the form of burst, and each burst comprises enough idling cycles guaranteeing that UE can be that sufficient measurements and calculations are done in the location, is separated with the radio frames that there is not idling cycle in several between between two secondary bursts.Continuous mode is a kind of special case of burst mode, and it as burst length, during this period of time carries out the calculating of idling cycle with whole 4096 radio frames cycle periods always, and under continuous mode, idling cycle will occur once every several radio frames.Need to prove, radio frames in the WCDMA system is with 0～4095 loop coding, the cycle of each radio frames (frame) is 10 milliseconds, be divided into 15 time slots (slot), 38400 chips (chip), and each radio frames can be divided into 150 symbols (symbol).

According to the definition of 3GPP agreement, calculating the IPDL position needs following IPDL parameter: IP_Status, and the indication idling cycle is to arrange with continuous mode or with burst mode; IP_Spaeing represents the number of the radio frames between adjacent two radio frames that contain idling cycle, and it should be noted that to have an idling cycle at most in the radio frames; IP_Length, the length of expression idling cycle is generally represented with the symbolic number of pilot channel (CPICH), i.e. the number of symbols that comprises of idling cycle; IP_Offset is used for synchronous Node B sub-district constant offset in different sectors free cycles; Seed, the seed of pseudo-random sequence generator; Burst_Start, the expression original position of burst for the first time under burst mode is represented the initial radio frame number (SFN) of the 0th secondary burst with 256 * Burst_Start, Burst_Start is fixed as 0 under continuous mode; Burst_Length represents the number that the central idling cycle of a secondary burst occurs; Burst_Freq represents the interval between the start frame of two secondary bursts, represents the interval between the initial radio frames of two secondary bursts with 256 * Burst_Freq.

Under burst mode, the initial radio frame number of the 0th secondary burst is 256 * Burst_Start, the k time (k=0 wherein, 1,2,3...) the initial radio frame number of burst is: SFN=256 * Burst_Start+k * 256 * Burst_Freq.Suppose that IP_Position (x) is x (x=1 in certain secondary burst, 2,3...) position of idling cycle, IP_Position (x) uses from the initial radio frames symbol numbers of CPICH to x the idling cycle radio frames that happens suddenly and represents, the position according to idling cycle in the each burst of 3GPP agreement is so:

IP_Position(x)＝(x×IP_Spacing×150)+(rand(xmod64)mod(150-IP_Length))+IP_Offset (1)

Continuous mode and burst mode use same formula to calculate, and just parameter wherein is different.

Random number rand () is the pseudo random sequence generation by following formula (2) and formula (3) definition in the formula (1):

rand(0)＝Seed (2)

Rand (m)=(106 * rand (m-1)+1283) mod 6075, m=1 wherein, 2,3... (3)

Fig. 1 is the position view of idling cycle under the burst mode, the repeatedly burst of first line display from the bottom up in the radio frames sequence, the 0th secondary burst is since the 256th * Burst_Start radio frames, length is 256 * Burst_Freq radio frames, and the k secondary burst is since the 256th * Burst_Start+k * 256 * Burst_Freq radio frames; Second go the radio frames of having showed each idling cycle place in the secondary burst, the x * IP_Spacing the radio frames of x idling cycle place radio frames from the bottom up for beginning from the initial radio frames of this secondary burst; The third line is the schematic diagram that has the radio frames of x idling cycle from the bottom up, this idling cycle originates in (rand (xmod64) mod (150-IP_Length))+IP_Offset symbol in this radio frames, and idling cycle ends at this radio frames (rand (xmod64) mod (150-IP_Length))+IP_Offset+IP_Length symbol; Top line be in x idling cycle and the place radio frames time slot concern schematic diagram.

Regulation according to above-mentioned 3GPP agreement, prior art adopts structure as shown in Figure 2 to realize IPDL, this structure is by computed in software formula (1), then with the descending modulation chip of IPDL position dispensing that calculates, descending modulation chip punches in corresponding data flow according to described IPDL position, promptly sends data 0.

Adopt the method for computed in software IPDL position, increased the soft or hard interface, need accomplish that the data flow of handling in the descending modulation chip just in time matches when computed in software is come out the descending modulation chip of IPDL position dispensing, but synchronizing information is safeguarded by descending modulation chip oneself, when computed in software, these informational needs are by the interface transmission of chip and software, improved mutual complexity between the two, increase the processing delay of descending modulation chip easily, reduce the real-time that descending modulation chip is handled.In addition, because software is the sequential processes process, the process that increases a calculating IPDL position can increase the load of software, reduces the disposal ability of software.

Summary of the invention

In view of this, the present invention proposes a kind of device with hardware realization down idle cycle, its purpose is, improves the computational speed of IPDL position, reduces the processing delay of descending modulation chip, improves the real-time that descending modulation chip is handled.

According to above-mentioned purpose, the present invention proposes a kind of device of realizing down idle cycle, this device comprises the IPDL insert module of closing insertion idling cycle in the circuit-switched data signal according to the idling cycle index signal in the sub-district at least, this device further comprises random number generation module and IPDL computing module, wherein, described random number generation module is used for the random number seed that sends according to described IPDL computing module, calculate random number, and described random number is returned to the IPDL computing module; Described IPDL computing module is used for the random number that IPDL parameter and described random number generation module according to system configuration return, the position in computation-free cycle, and in idling cycle to described IPDL insert module output idling cycle index signal.

Described IPDL computing module comprises that IPDL burst initial signal circuit and idling cycle index signal produce circuit, wherein, described IPDL burst initial signal circuit, be used for according to described IPDL calculation of parameter IPDL burst start frame, and produce circuit transmission IPDL burst initial signal to described idling cycle index signal at IPDL burst start frame; Described idling cycle index signal produces circuit, be used for the random number returned according to described IPDL parameter, IPDL burst initial signal and random number generation module, the position in computation-free cycle, and in idling cycle, export the idling cycle index signal to described IPDL insert module.

Described IPDL burst initial signal circuit comprises radio frame number SFN counter, first divider, the first remainder judging unit, subtrator, second divider and the second remainder judging unit, wherein, described SFN counter is used for from 0 to 4095 cycle count, and current count value is imported described first divider as the current wireless frame number; Described first divider is used to calculate the current wireless frame number and obtains quotient and the remainder divided by 256, and described quotient and the remainder are imported the described first remainder judging unit; The described first remainder judging unit is used to judge whether the remainder of first divider is zero, and when described remainder is zero, export the merchant of first divider to subtrator, when described remainder is non-vanishing, do not export the merchant of first divider to subtrator; It is poor that the initial radio frame number that the merchant that described subtrator is used for calculating described first divider deducts the burst first time of described IPDL parameter obtains, and described difference is imported second divider; Described second divider is used for calculating the difference that described subtrator obtains and obtains quotient and the remainder divided by the radio frames between the initial radio frames of two secondary bursts of described IPDL parameter, and described quotient and the remainder are imported the second remainder judging unit; The described second remainder judging unit is used to judge whether the remainder of described second divider is zero, and produces IPDL burst initial signal when remainder is zero.

The invention also discloses a kind of device of realizing down idle cycle IPDL, this device comprises the IPDL insert module of closing insertion idling cycle in the circuit-switched data signal according to the idling cycle index signal in the sub-district at least, this device further comprises random number generation module and IPDL computing module, wherein

Described random number generation module is used for the random number seed that sends according to described IPDL computing module, calculates random number, and described random number is returned to the IPDL computing module;

Described IPDL computing module is used for the random number that IPDL parameter and described random number generation module according to system configuration return, the position in computation-free cycle, and in idling cycle to described IPDL insert module output idling cycle index signal;

Described IPDL computing module comprises that IPDL burst initial signal circuit and idling cycle index signal produce circuit, wherein,

Described IPDL burst initial signal circuit is used for according to described IPDL calculation of parameter IPDL burst start frame, and produces circuit transmission IPDL burst initial signal at IPDL burst start frame to described idling cycle index signal;

Described idling cycle index signal produces circuit, be used for the random number returned according to described IPDL parameter, IPDL burst initial signal and random number generation module, the position in computation-free cycle, and in idling cycle, export the idling cycle index signal to described IPDL insert module;

Described idling cycle index signal produces circuit and comprises first d type flip flop, second d type flip flop, first counter, second counter, the 3rd counter and IPDL generation module, wherein, described first d type flip flop is used for producing index signal according to the idling cycle index signal of the signal of first counter output and the output of IPDL generation module, and exports described index signal to described the 3rd counter and random number generation module; Described second d type flip flop is used for producing the effective signal of current burst according to the signal of described IPDL burst initial signal and the output of second counter, and exports the effective signal of the current burst of described expression to first counter and second counter; Described first counter is used for according to the signal of described IPDL burst initial signal and the output of second d type flip flop radio frames being counted, and contains the signal of idling cycle during IP_Spacing in counting down to described IPDL parameter to second counter and first d type flip flop output expression current wireless frame; Described second counter is used for according to the signal of the signal of described first counter output and the output of second d type flip flop signal-count to the output of first counter, and during the Burst_Length when counting down to described IPDL parameter in to the signal of this secondary burst of second d type flip flop output expression end; Described the 3rd counter is used for IP_Length according to the signal of the index signal of described first d type flip flop output, the output of first counter and described IPDL parameter to symbol count, and to the output of IPDL generation module with current count value; Described IPDL generation module obtains idling cycle original position and end position according to the result of described random number generation module output, when the current count value of the 3rd counter is between described idling cycle original position and end position, to described first d type flip flop and IPDL insert module output idling cycle index signal; Described random number generation module is further imported the IPDL generation module according to the index signal of first d type flip flop output with described random number; Wherein, described IP_Spacing represents the number of two radio frames between the radio frames that contains idling cycle; Described Burst_Length represents the number of idling cycle in the burst; Described IP_Length represents the symbolic number that idling cycle comprises.

From such scheme, as can be seen,, improved the computational speed of IPDL position, reduced the processing delay of descending modulation chip, improved the real-time that descending modulation chip is handled because the present invention adopts hardware logic to realize calculating the function of IPDL position.And, because the present invention does not use computed in software IPDL position, reduced descending modulation chip and the outside interface that calculates, simplified the framework of system.

Description of drawings

Fig. 1 is the idling cycle position view;

Fig. 2 is the principle schematic of the structure that prior art adopted;

The hardware configuration schematic diagram that Fig. 3 adopts for the present invention;

Fig. 4 is for calculating the schematic flow sheet of the initial radio frame number of each secondary burst;

Fig. 5 is the principle schematic of IPDL burst initial signal circuit;

Fig. 6 is the principle schematic of ipdl_ind signal generating circuit;

The schematic diagram of Fig. 7 for concerning between burst_state signal and the burst_ready signal;

The schematic diagram of Fig. 8 for concerning between rand_ready signal and the rand_sync signal;

The schematic diagram of Fig. 9 for concerning between burst_state signal and the rand_ready signal;

Figure 10 is the principle schematic of random number generation module;

Figure 11 is for keeping the division arithmetic schematic flow sheet of remainder;

Figure 12 is the workflow schematic diagram of random number generation module;

Figure 13 subtracts each other the schematic flow sheet that carries out modulo operation for adopting displacement;

Figure 14 is the schematic diagram that concerns between x_position, location signal and the ipdl_ind signal.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in more detail by the following examples.

Unlike the prior art be that the present invention adopts hardware to realize the algorithm of IPDL position, and the present invention adopts same set of mechanism to calculate IPDL position under burst mode and the continuous mode.

A kind of special case that continuous mode can be equal to by analysis, burst mode.When the burst length of burst mode be 4096 radio frames and each burst all at first from SFN=0, this burst mode in fact just is equal to continuous mode.

With reference to figure 3, hardware module of the present invention comprises random number generation module, IPDL position computation module and IPDL insert module.Wherein the random number generation module is according to the random number seed rand_seed of system configuration, by the calculating of random number rand (xmod64) in the hardware computing formula (1), and to IPDL position computation module return results rand_data; The IPDL position computation module realizes the calculating of formula (1) according to timing controling signal and the DSP control signaling that Digital Signal Processing (DSP) chip sends by hardware, wherein timing controling signal is used for the starting point of synchronization frame, the DSP signaling comprises each IPDL parameter, after calculating the IPDL position, export idling cycle index signal ipdl_ind to the IPDL insert module, ipdl_ind is that high level is effective in the present embodiment, the position of indication IPDL; The ipdl_ind that the IPDL insert module provides according to the IPDL position computation module closes in the circuit-switched data signal in the sub-district and inserts IPDL, be about to the sub-district and close in the circuit-switched data signal data of corresponding positions and destroy, with 0 generation it.

The specific implementation of each module is described respectively below.

When the IPDL position computation module is calculated the IPDL position, at first will determine the initial radio frame number of each secondary burst, the initial radio frame number of each secondary burst is in the process of one 4096 radio frames circulation:

SFN＝256×Burst_Start+k×256×Burst_Freq (4)

K=0 wherein, 1,2,3... according to the value of the anti-k of release of formula (4) is:

$k=\frac{\frac{\mathrm{SFN}}{256}-\mathrm{Burst}\_\mathrm{Start}}{\mathrm{Burst}\_\mathrm{Freq}}---\left(5\right)$

With reference to formula (5), the present invention determines the initial radio frame number of each secondary burst, and produces the initial pulse signal burst_ready of k secondary burst process by according to flow process shown in Figure 4.With reference to figure 4, begin to carry out following flow process from SFN=0:

Step 401 judges that whether SFN is 256 integral multiple, and promptly whether SFN is 0 divided by the remainder of 256 gained, if then execution in step 402, otherwise execution in step 404.

Step 402 judges to step 403 whether (SFN/256-Burst_Start) is the integral multiple of Burst_Freq, and whether promptly current k is integer, if, then produce the burst_ready signal of a clock cycle, otherwise execution in step 404.

Step 404 adds 1 back execution in step 401 with SFN, equals 4095 until SFN.

The present invention realizes above-mentioned flow process by IPDL burst initial signal circuit as shown in Figure 5, and exports the burst_ready signal in the initial radio frames of each secondary burst, and this burst_ready signal is the initial pulse of k secondary burst process.Comprise radio frame number (SFN) counter, first divider, the first remainder judging unit, subtrator, second divider, the second remainder judging unit with reference to this IPDL burst initial signal circuit of Fig. 5.SFN counter from 0 to 4095 cycle count wherein, and to first divider input current wireless frame number SFN; First divider is calculated current wireless frame number SFN divided by 256 according to current wireless frame number SFN and coefficient 256, and to first remainder judging unit output result, comprises quotient and the remainder; The first remainder judging unit judges that according to the result whether remainder is zero, and promptly whether SFN is 256 integral multiple, if then the result with first divider imports subtrator, otherwise the merchant of first divider is not imported subtrator; Subtrator calculates SFN/256 and deducts Burst_Start according to the result and the B parameter urst_Start of first divider, and to the output of second divider result of calculation, the i.e. value of SFN/256-Burst_Start; Second divider is calculated SFN/256-Burst_Start divided by Burst_Freq according to the result of calculation SFN/256-Burst_Start and the B parameter urst_Freq of subtrator input, and promptly the numerical value of k is imported quotient and the remainder the second remainder judging unit then; Whether the second remainder judgment unit judges remainder is zero, and promptly whether SFN/256-Burst_Start is the integral multiple of Burst_Freq, if then produce the burst_ready signal, otherwise do not produce the burst_ready signal.As previously described, import the IPDL parameter of this circuit,, all export from dsp chip as Burst_Start, Burst_Freq etc.

After the initial radio frame number of determining certain secondary burst, the present invention determines radio frames and the primary sign number of IPDL in described radio frames that IPDL will occur in the secondary burst by ipdl_ind signal generating circuit as shown in Figure 6, thereby obtain original position and the end position of IPDL, and output ipdl_ind signal.The end position of described IPDL and the end position of IPDL differ IP_Length symbol.

Ipdl_ind signal generating circuit shown in Figure 6, according to burst_ready signal of importing from IPDL burst initial signal circuit and IP_Spacing, Burst_Length, the IPDL parameters of importing from dsp chip such as rand_seed, IP_Length, produce the ipdl_ind signal of indication IPDL position, for convenience, the random number generation module that in this circuit, drawn simultaneously.

As shown in Figure 6, this ipdl_ind signal generating circuit comprises first d type flip flop, second d type flip flop, first counter (counter1), second counter (counter2), the 3rd counter (counter3) and IPDL generation module.Wherein first d type flip flop is used for according to the rand_sync signal of counter1 output output being put 1, and will export zero clearing according to the ipdl_ind signal of IPDL generation module output, thereby produce signal rand_ready, and input random number generation module and counter3; Second d type flip flop puts 1 according to burst_ready with output, and according to the signal zero clearing of counter2 output, thereby produce the burst_state signal, and input counter1, burst_state represents that current burst is effective; Random number generation module among the figure will calculate rand_data input IPDL generation module according to rand_ready; Counter1 begins radio frames is counted from the burst_ready signal, when counter1 equals IP_Spacing, send a rand_sync signal to first d type flip flop, counter2 and counter3, be illustrated in this radio frames and IPDL will occur; Counter2 adds 1 according to the rand_sync signal, when counter2 count down to Burst_Length, represents that this secondary burst finishes, and sends signal to second d type flip flop, and second d type flip flop is with the zero clearing of burst_state signal; Counter3 to symbol count, and sends to the IPDL generation module with current count value according to rand_ready signal, IP_Length parameter and rand_sync signal; The IPDL generation module receives the rand_data of random number generation module and the signal of counter3, obtain the original position x_position and the end position location of idling cycle according to rand_data, location equals x_position+IP_Length, the IPDL generation module is compared the count value of counter3 with x_position and location, when the count value of counter3 equals x_position, output ipdl_ind signal is 1, when the count value of counter3 equaled location, output ipdl_ind signal was 0.

Specify principle and the implementation procedure of determining the IPDL position according to above-mentioned ipdl_ind signal generating circuit below.

Because the position of IPDL is to represent with the symbol of pilot channel CPICH, and the radio frames of pilot channel CPICH includes 150 symbols.Observe first (x * IP_Spacing * 150) in the formula (1), what wherein in fact x * IP_Spacing calculated as can be seen is a radio frame number, this radio frame number correspondence be exactly that frame from the burst start frame begins to count, an x IPDL is about to appearance.Therefore,, carry out the counting of mould IP_Spacing, promptly whenever count down to IP_Spacing and count again, when counter1 count down to IP_Spacing, just show that an IPDL can appear in the current wireless frame with regard to zero clearing by counter1 from the burst_ready signal.

Because the total length of each burst is a Burst_Length * IP_Spacing radio frames, therefore by when counter1 equals IP_Spacing, counter2 being added 1, when counter2 equals Burst_Length, represent that this secondary burst finishes, and will represent the register burst_state signal zero clearing of burst length state then by second d type flip flop.Relation between above-mentioned burst_ready and the burst_state as shown in Figure 7, after a burst_ready signal occurring, indicating this secondary burst original position, the burst_state signal is changed to 1, represent current being in the burst process, after burst finished, the burst_state signal was cleared.

After having determined radio frame number that the IPDL of expression in first of the formula is about to occur, then determine second (rand (xmod64) mod (150-IP_Length)) in the formula (1).When counter1 count down to IP_Spacing-1, counter1 output sync pulse signal rand_sync, expression IPDL will occur in this frame, and start IPDL length status register rand_ready by first d type flip flop by rand_sync, the rand_ready signal is kept high level, is cleared the back zero clearing up to IPDL index signal ipdl_ind.The relation of above-mentioned rand_sync signal and rand_ready signal as shown in Figure 8, above among the figure is the position view of IPDL in the radio frames of its generation, when this radio frames is initial, produce a rand_sync signal, along with the rand_sync signal produces the rand_ready signal, and be maintained to the IPDL end.Fig. 9 has then further provided the schematic diagram that concerns of the register burst_state of expression burst length and rand_ready.

In second (rand (xmod64) mod (150-IP_Length)) of formula (1), the calculating of random number rand (x mod 64) produces by random number generation module as shown in figure 10, and this random number generation module produces the pseudo-random number sequence by formula (2) and formula (3) definition.The random number generation module comprises the addition multiplier and keeps the remainder divider among the figure, wherein the addition multiplier is used for (106 * rand (m-1)+1283) part according to rand_seed computing formula (3), for fear of the multiplication of long number, making binary system into 106 is 106=2 ⁶+ 2 ⁵+ 2 ³+ 2 ¹, (106 * rand (m-1)+1283) just is converted into like this:

rand(m-1)×(2 ⁶+2 ⁵+2 ³+2 ¹)+1283 (6)

Like this, with rand (m-1) * (2 ⁶+ 2 ⁵+ 2 ³+ 2 ¹) multiplication is converted into rand (m-1) * 2 ⁶+ rand (m-1) * 2 ⁵+ rand (m-1) * 2 ³+ rand (m-1) * 2 ¹, addition after soon rand (m-1) will be shifted respectively.And then with the result with 1283 additions, obtain the end product of (106 * rand (m-1)+1283).

The method that reservation remainder divider in the randomizer adopts displacement to subtract each other is calculated the result of (106 * rand (m-1)+1283) mould 6075, and it is a kind of very ripe method that displacement is subtracted each other, and the flow process that adopts this method may further comprise the steps as shown in figure 11:

Step 1101, determine the mould value of control shift operation counter, to calculate (106 * rand (m-1)+1283) mod 6075 is example, because (106 * rand (m-1)+1283) maximum bit wide is 20 bits, 6075 bit wide is 13 bits, computing just can draw desired mould 20-13+1=8 time so at most, and promptly the mould value of above-mentioned counter is 8.Counter is since 1 counting then.

Step 1102, dividend is shifted, each high 13 bits with dividend deduct divisor, judge the sign bit of difference, 1 represent that high 13 bits of dividend remove inadequately if be, dividend is moved to left one, subtract each other with said method and divisor again,, show that high 13 bits of dividend enough remove if the difference sign bit is 0, difference is a remainder just, and the remaining bits of remainder and dividend is lumped together as new dividend.Simultaneously counter is added 1.

Step 1103 judges whether counter equals mould value 8, if execution in step 1104 then, otherwise execution in step 1102.

Step 1104 obtains the difference of step 1102 dividend and divisor, and the numerical value of going out in this difference outside the sign bit is exactly desired mould, thereby obtains (106 * rand (m-1)+1283) mod 6075.

As shown in figure 12, adopt randomizer to calculate rand (x mod64), promptly the process of (106 * rand (m-1)+1283) mod 6075 may further comprise the steps:

Step 1201, the value of judgement x, selected rand (m-1).

Step 1202 by the displacement method of multiplication adder, is calculated rand (m-1) * 2 ⁶, rand (m-1) * 2 ⁵, rand (m-1) * 2 ³, rand (m-1) * 2 ¹

Step 1203, continue by each result's in the multiplication adder calculation procedure 1202 and, and then add 1283, obtain the result of (106 * rand (m-1)+1283).

Step 1204 by keeping the displacement subtractive method of remainder divider, is calculated (106 * rand (m-1)+1283) result to 6075 deliverys.

Step 1205 draws random number rand (xmod64) according to The above results then.

According to said method, the calculating of formula (1) second (rand (xmod64) mod (150-IP_Length)) just is very easy to realize.Wherein x mod 64 can adopt the method realization that displacement is subtracted each other equally, but considers 64=2 ⁶, with the x binary representation, its low 5 are exactly the result of x mod 64.

Rand (x mod64) still can adopt the division that keeps remainder to realize that its implementation procedure is identical with top flow process shown in Figure 11, only because concrete numerical value difference to the calculating of (150-IP_Length) delivery.Wherein, the maximum occurrences of rand (x mod 64) is no more than 6075, so the bit wide of dividend should be 13bit; Divisor (150-IP_Length) is no more than 150, represents with 8bit; The counter mould value of control displacement is (13-8)+1=6 like this.Detailed process may further comprise the steps as shown in figure 13:

Step 1301 determines that the mould value of the counter of control shift operation is 6,, calculates the result of (106 * rand (m-1)+1283) mod 6075 according to the method for step 1201 to step 1205.

Step 1302, enabling counting device, the initial value of counter are 1.

Step 1303 is carried out subtraction and shifting function, and counter is added 1.

Step 1304 judges whether the count value of counter equals 6, if execution in step 1305 then, otherwise execution in step 1303 is proceeded subtraction and shifting function.

Step 1305 draws the result of rand (xmod 64) mod (150-IP_Length).

So far, calculate first and second of formula (1) by hardware, and the 3rd offset parameter IP_Offset of formula (1) is known parameter, and these three additions are just obtained the original position of IPDL, and the original position of establishing this IPDL is x_position.Further, because parameter I P_Length is the length of an idling cycle, x_position+IP_Length just represents the position that idling cycle finishes so, and the position of establishing described IPDL end is location.

Continuation is with reference to Fig. 6, counter3 among the figure is under the control of rand_ready and rand_sync signal, carry out the counting of symbol according to the processing of descending modulation chip other parts, when counter3 count down to x_position, the output signal of IPDL generation module is put height, output signal with the IPDL generation module when counter3 count down to location drags down, thereby has produced idling cycle index signal ipdl_ind.

Figure 14 is the schematic diagram that concerns of counter counter3 count value and idling cycle index signal ipdl_ind.Count down to x_position to counting down between the location at counter3, idling cycle index signal ipdl_ind is a high level, is 1; Outside this, ipdl_ind is that low spot is flat, is 0.Indicate the scope of idling cycle like this by the ipdl_ind signal.

Last IPDL insert module is about to the data of launching on the interface aloft according to described ipdl_ind signal controlling, if ipdl_ind is " 1 ", aloft the data of launching on the interface are 0, if ipdl_ind is " 0 ", aloft the data of launching on the interface are the data that modulated originally.

The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (4)

1. device of realizing down idle cycle IPDL, this device comprises the IPDL insert module of closing insertion idling cycle in the circuit-switched data signal according to the idling cycle index signal in the sub-district at least, it is characterized in that this device further comprises random number generation module and IPDL computing module, wherein

Described random number generation module is used for the random number seed that sends according to described IPDL computing module, calculates random number, and described random number is returned to the IPDL computing module;

Described IPDL computing module is used for the random number that IPDL parameter and described random number generation module according to system configuration return, the position in computation-free cycle, and in idling cycle to described IPDL insert module output idling cycle index signal;

Described IPDL computing module comprises that IPDL burst initial signal circuit and idling cycle index signal produce circuit, wherein,

Described IPDL burst initial signal circuit is used for according to described IPDL calculation of parameter IPDL burst start frame, and produces circuit transmission IPDL burst initial signal at IPDL burst start frame to described idling cycle index signal;

Described idling cycle index signal produces circuit, be used for the random number returned according to described IPDL parameter, IPDL burst initial signal and random number generation module, the position in computation-free cycle, and in idling cycle, export the idling cycle index signal to described IPDL insert module;

Described IPDL burst initial signal circuit comprises radio frame number SFN counter, first divider, the first remainder judging unit, subtrator, second divider and the second remainder judging unit, wherein,

Described SFN counter is used for from 0 to 4095 cycle count, and current count value is imported described first divider as the current wireless frame number;

Described first divider is used to calculate the current wireless frame number and obtains quotient and the remainder divided by 256, and described quotient and the remainder are imported the described first remainder judging unit;

The described first remainder judging unit is used to judge whether the remainder of first divider is zero, and when described remainder is zero, export the merchant of first divider to subtrator, when described remainder is non-vanishing, do not export the merchant of first divider to subtrator;

It is poor that the initial radio frame number that the merchant that described subtrator is used for calculating described first divider deducts the burst first time of described IPDL parameter obtains, and described difference is imported second divider;

Described second divider is used for calculating the difference that described subtrator obtains and obtains quotient and the remainder divided by the radio frames between the initial radio frames of two secondary bursts of described IPDL parameter, and described quotient and the remainder are imported the second remainder judging unit;

The described second remainder judging unit is used to judge whether the remainder of described second divider is zero, and produces IPDL burst initial signal when remainder is zero.

2. device according to claim 1 is characterized in that, described random number generation module comprises multiplication adder and reservation remainder divider,

Wherein, described multiplication adder is used to calculate random number that the random number generation module last time calculates and 106 product, and described product is added that 1283 obtain result of calculation, and described result of calculation is imported described reservation remainder divider;

Described reservation remainder divider, be used for result of calculation according to described multiplication adder, the method that adopts displacement to subtract each other draws the result of the result of calculation of described multiplication adder to 6075 deliverys, and the result of described delivery returned as described random number sends to described IPDL computing module.

3. device of realizing down idle cycle IPDL, this device comprises the IPDL insert module of closing insertion idling cycle in the circuit-switched data signal according to the idling cycle index signal in the sub-district at least, it is characterized in that this device further comprises random number generation module and IPDL computing module, wherein

Described random number generation module is used for the random number seed that sends according to described IPDL computing module, calculates random number, and described random number is returned to the IPDL computing module;

Described IPDL computing module is used for the random number that IPDL parameter and described random number generation module according to system configuration return, the position in computation-free cycle, and in idling cycle to described IPDL insert module output idling cycle index signal;

Described IPDL computing module comprises that IPDL burst initial signal circuit and idling cycle index signal produce circuit, wherein,

Described IPDL burst initial signal circuit is used for according to described IPDL calculation of parameter IPDL burst start frame, and produces circuit transmission IPDL burst initial signal at IPDL burst start frame to described idling cycle index signal;

Described idling cycle index signal produces circuit, be used for the random number returned according to described IPDL parameter, IPDL burst initial signal and random number generation module, the position in computation-free cycle, and in idling cycle, export the idling cycle index signal to described IPDL insert module;

Described idling cycle index signal produces circuit and comprises first d type flip flop, second d type flip flop, first counter, second counter, the 3rd counter and IPDL generation module, wherein,

Described first d type flip flop is used for producing index signal according to the idling cycle index signal of the signal of first counter output and the output of IPDL generation module, and exports described index signal to described the 3rd counter and random number generation module;

Described second d type flip flop is used for producing the effective signal of current burst according to the signal of described IPDL burst initial signal and the output of second counter, and exports the effective signal of the current burst of described expression to first counter and second counter;

Described first counter is used for according to the signal of described IPDL burst initial signal and the output of second d type flip flop radio frames being counted, and contains the signal of idling cycle during IP_Spacing in counting down to described IPDL parameter to second counter and first d type flip flop output expression current wireless frame;

Described second counter is used for according to the signal of the signal of described first counter output and the output of second d type flip flop signal-count to the output of first counter, and during the Burst_Length when counting down to described IPDL parameter in to the signal of this secondary burst of second d type flip flop output expression end;

Described the 3rd counter is used for IP_Length according to the signal of the index signal of described first d type flip flop output, the output of first counter and described IPDL parameter to symbol count, and to the output of IPDL generation module with current count value;

Described IPDL generation module obtains idling cycle original position and end position according to the result of described random number generation module output, when the current count value of the 3rd counter is between described idling cycle original position and end position, to described first d type flip flop and IPDL insert module output idling cycle index signal;

Described random number generation module is further imported the IPDL generation module according to the index signal of first d type flip flop output with described random number;

Wherein, described IP_Spacing represents the number of two radio frames between the radio frames that contains idling cycle; Described Burst_Length represents the number of idling cycle in the burst; Described IP_Length represents the symbolic number that idling cycle comprises.

4. device according to claim 3 is characterized in that, described random number generation module comprises multiplication adder and reservation remainder divider,

Wherein, described multiplication adder is used to calculate random number that the random number generation module last time calculates and 106 product, and described product is added that 1283 obtain result of calculation, and described result of calculation is imported described reservation remainder divider;

Described reservation remainder divider, be used for result of calculation according to described multiplication adder, the method that adopts displacement to subtract each other draws the result of the result of calculation of described multiplication adder to 6075 deliverys, and the result of described delivery returned as described random number sends to described IPDL computing module.

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