CN100405715C - Double pulse width modulation controller for back to back structure voltage type current changing device - Google Patents
Double pulse width modulation controller for back to back structure voltage type current changing device Download PDFInfo
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- CN100405715C CN100405715C CNB2006100170050A CN200610017005A CN100405715C CN 100405715 C CN100405715 C CN 100405715C CN B2006100170050 A CNB2006100170050 A CN B2006100170050A CN 200610017005 A CN200610017005 A CN 200610017005A CN 100405715 C CN100405715 C CN 100405715C
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Abstract
This invention relates to a double-pulse width modulation controller of a back to back structure voltage deflector characterizing in including two sets of same structured digital signal processor circuits and a site programmable gate array circuits, a synchronous unit circuit, an A/D conversion regulation circuit, an overvoltage-overcurrent regulation circuit, a serial communication circuit, a fault, state indication circuit and a control supply circuit, in which, the DSP of the digital signal processor circuit is used for A/D conversion, upper layer control algorithm, pulse width modulation, generation of pulses and serial communication control in the bottom layer control, the two I/O ports of the digital signal processor circuit and the site programmable gate array circuit are connected for the communication of the working state between them and application in different fields by programming not necessary to alter the hardware circuit.
Description
Technical field
The present invention relates to the control technology field, is a kind of double pulse width modulation controller of back to back structure voltage type current changing device.
Background technology
Owing to can produce huge economic benefit, power electronic technology has become a kind of basic technology and has been widely used in various industries.Back to back structure voltage type current changing device can be used in and connects synchronous or asynchronous AC system, realize the active power of two ends AC system and the flexible control of reactive power, thereby obtained extensive use, as HVDC Light system, the THE UPFC UPFC in the electric power transfer field, the frequency conversion speed-adjusting system that electric energy in the industrial energy saving can two-way circulate, AC excitation speed setting controller of the double-fed type induction generator in the variable-speed constant-frequency wind power generation system or the like.
Back to back structure voltage type current changing device is made of double pulse width modulation controller, adopt pulse width modulation (Pulse Width Modulation, be called for short PWM) control method, with the exchange control of active power between the AC system of realization both sides and reactive power, control system is mainly by control of upper strata power and the control of bottom current transformer.Wherein, the task of upper strata control is to determine the reference voltage or the reference current of the output of current transformer needs according to reference power; Bottom control is responsible for generating the control signal of the power electronic device in the convertor circuit, produces the upper strata with the control current transformer and controls determined reference voltage or electric current; In addition, bottom control generally also comprises the functions such as pulse blocking under the states such as overcurrent and overvoltage, in case locking apparatus enters the abnormality operation.Existing Pwm controller uses a digital signal processor DSP to finish upper strata control, the digital circuit that re-uses a DSP and discrete component formation is finished bottom control, peripheral circuits such as external signal collection, state and guard signal processing constitute, its weak point is: need communication between two DSP 1., and need aid in a large amount of peripheral circuits, make the controller architecture complexity; 2. the setting of the inconvenient Control Parameter of digital circuit of discrete component formation open and the isoparametric setting of minimum turn-off time as brachium pontis Dead Time, power electronic device minimum, and set point can produce error with the variation of discrete device parameter.
Summary of the invention
The objective of the invention is: provide a kind of versatility good, control precision height, the double pulse width modulation controller of the back to back structure voltage type current changing device that circuit structure is simple, integrated level is high.
The objective of the invention is to realize: a kind of double pulse width modulation controller of back to back structure voltage type current changing device by following technical scheme, it is characterized in that, it comprises by two nested structures identical, with digital signal processor circuit 1 and field programmable gate array circuit 2 is core control part, and the digital signal processor DSP of digital signal processor circuit 1 is used for that pwm pulses generates and serial communication control in analog-to-digital conversion, upper strata control algolithm, the bottom control; 2 two input and output I/O of digital signal processor circuit 1 and field programmable gate array circuit mouth is connected, and is used for the communication of operating state between digital signal processor circuit 1 and the field programmable gate array circuit 2; Lock unit circuit 3 is used for the synchronous voltage signal after handling sent into and exports digital signal processor circuit 1 to after field programmable gate array circuit 2 is handled, and is used for convertor assembly incoming transport electrical network; Modulus A/D conversion modulate circuit 4 is used for the voltage and current signal is sent into digital signal processor circuit 1, and digital signal processor carries out being used for the upper strata control algolithm after the analog-to-digital conversion; Overvoltage, overcurrent modulate circuit 5 are used for the voltage and current signal is sent into field programmable gate array circuit 2, to the monitoring of convertor assembly and the pulse blocking under the unusual condition; The input of serial communication circuit 6 links to each other with computer, and its input links to each other with field programmable gate array circuit 2, is used for communicating by letter between computer and digital signal processor circuit 1 and the field programmable gate array circuit 2; Fault, condition indication circuit 7 link to each other with field programmable gate array circuit 2, are used to refer to fault, state composition.
Described lock unit circuit 3 is by chip U1S, capacitor C 2S, C3S, the band pass filter that resistance R AXS, RBXS, RCXS, RDXS, REXS form, hysteresis loop comparator U4SB is connected with the monostable trigger-action circuit of being made up of chip U7SA, resistance R 9S, capacitor C 1S and forms.
Described modulus A/D conversion modulate circuit 4 is by amplifier U17ADA and resistance R 147AD, R148AD, R149AD, R171AD, the anti-phase adder that capacitor C 81AD forms, the multiplication factor of being made up of amplifier U17ADB and resistance R 150AD, R151AD, R165AD is 1 inverter, is connected with the interface level clamp circuit of being made up of diode D31AD, D32AD and forms.
Described overvoltage, overcurrent modulate circuit 5 are by diode D12PR, D13PR, resistance R 5PR, R6PR, R8PR, the peak detection circuit that amplifier U4PRA forms, the high-frequency filter circuit of being made up of resistance R 7PR, R9PR and capacitor C 1PR is the voltage comparator composition that is connected with amplifier U9PRA.
Described serial communication circuit 6 is connected with capacitor C 3, C4, C5, C6, C7 by level transferring chip J1 and forms.
The double pulse width modulation controller of back to back structure voltage type current changing device of the present invention, because it is identical with two nested structures, with digital signal processor circuit, field programmable gate array circuit is core control part, and match lock unit circuit, modulus A/D conversion modulate circuit, overvoltage, overcurrent modulate circuit, serial communication circuit, fault, condition indication circuit and control power circuit and formed high performance dipulse width modulator, the beneficial effect that has is embodied in:
1. highly versatile, under the prerequisite that hardware circuit need not to change, those skilled in the art need only can be adapted to different application scenarios by programming;
2. control precision height: use high speed digital signal processor DSP,, improve the dynamic responding speed of control system so that adopt shorter control cycle;
3. integrated level height: the circuit structure of forming double pulse width modulation controller is simple, integrated level is high.
Description of drawings
Fig. 1 is the double pulse width modulation controller schematic block circuit diagram of back to back structure voltage type current changing device.
Fig. 2 is the double pulse width modulation controller circuit connection diagram of back to back structure voltage type current changing device.
Fig. 2-A is an A part schematic diagram among Fig. 2.
Fig. 2-B is a B part schematic diagram among Fig. 2.
Fig. 3 is digital signal processor circuit 1 schematic diagram.
Fig. 3-C is the C partial circuit schematic diagram of digital signal processor circuit 1 among Fig. 3.
Fig. 3-D is the D partial circuit schematic diagram of digital signal processor circuit 1 among Fig. 3.
Fig. 4 is field programmable gate array circuit 2 schematic diagrams.
Fig. 4-E is the E partial circuit schematic diagram of field programmable gate array circuit 2 among Fig. 4.
Fig. 4-F is the F partial circuit schematic diagram of field programmable gate array circuit 2 among Fig. 4.
Fig. 5 is lock unit circuit 3 schematic diagrams.
Fig. 6 is modulus A/D conversion modulate circuit 4 schematic diagrams.
Fig. 7 is overvoltage, overcurrent modulate circuit 5 schematic diagrams.
Fig. 8 is serial communication circuit 6 schematic diagrams.
Fig. 9 is fault, condition indication circuit 7 schematic diagrams.
Figure 10 is control power circuit 8 schematic diagrams.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
With reference to Fig. 1, the double pulse width modulation controller of back to back structure voltage type current changing device has digital signal processor circuit 1, field programmable gate array circuit 2, lock unit circuit 3, modulus A/D changes modulate circuit 4, overvoltage, overcurrent modulate circuit 5, serial communication circuit 6, fault, condition indication circuit 7 and control power circuit 8 are formed.The annexation of signal is represented with line in the drawings between the each several part circuit, and the direction of arrow has shown the transmission direction of signal.In addition, control power circuit 8 provides working power for controller each several part circuit, and wherein output+5V links to each other with the each part mentioned above circuit, and output ± 15V links to each other with lock unit circuit 3, overvoltage, overcurrent modulate circuit 5, modulus A/D conversion modulate circuit 4.
The double pulse width modulation controller of back to back structure voltage type current changing device, identical by two nested structures, with digital signal processor circuit 1 and field programmable gate array circuit 2 is core control part, and the digital signal processor DSP of digital signal processor circuit 1 is used for that pwm pulses generates and serial communication control in analog-to-digital conversion, upper strata control algolithm, the bottom control; 2 two input and output I/O of digital signal processor circuit 1 and field programmable gate array circuit mouth is connected, and is used for the communication of operating state between digital signal processor circuit 1 and the field programmable gate array circuit 2; Lock unit circuit 3 is used for the synchronous voltage signal after handling sent into and exports digital signal processor circuit 1 to after field programmable gate array circuit 2 is handled, and is used for convertor assembly incoming transport electrical network; Modulus A/D conversion modulate circuit 4 is used for the voltage and current signal is sent into digital signal processor circuit 1, and digital signal processor carries out being used for the upper strata control algolithm after the analog-to-digital conversion; Overvoltage, overcurrent modulate circuit 5 are used for the voltage and current signal is sent into field programmable gate array circuit 2, to the monitoring of convertor assembly and the pulse blocking under the unusual condition; The input of serial communication circuit 6 links to each other with computer, and its input links to each other with field programmable gate array circuit 2, is used for communicating by letter between computer and digital signal processor circuit 1 and the field programmable gate array circuit 2; Fault, condition indication circuit 7 link to each other with field programmable gate array circuit 2, are used to refer to fault, state composition.
Wherein: digital signal processor circuit 1 makes double pulse width modulation controller have very strong mathematical operational ability and control ability fast, be used for realizing the generation (for example, having realized that on this hardware circuit basis back to back structure voltage source type convertor assembly adopts the control algolithm and the two level space vector PWM algorithms of feedback linearization) of complicated control algolithm in upper strata and bottom control pulse-width signal; Field programmable gate array circuit 2 can be realized digital signal circuit flexibly by programming, has the integrated level height, revises convenient, advantages such as peripheral circuit is simple, dependable performance; Lock unit circuit 3 makes double pulse width modulation controller have synchronizing function (being used for the incoming transport electrical network), obtain accurate synchronizing signal by lock unit circuit 3, link to each other with interruptive port outside the digital signal processor circuit 1 after field programmable gate array circuit 2 is handled, digital signal processor DSP can be realized the operation of convertor assembly incoming transport synchronized by Interrupt Process.
The digital signal processor DSP that uses in the digital signal processor circuit 1 is the 32-bit microprocessor that 1 operating frequency can reach 150Mhz, model TMS320F2812, the TMS320F2812 chip is integrated with No. 16 analog to digital converters, two pulse-width modulations (PWM) task manager, two functional modules such as serial communication modular, the input and output I/O port high-low level of TMS320F2812 chip is respectively 3V and 0V, can realize the function such as the generation of pulse-width modulation (PWM) signal, serial communication in modulus A/D conversion, upper strata control algolithm, the bottom control after the programming.
The input signal of digital signal processor circuit 1: three-phase alternating current signal, ac voltage signal, direct voltage and the current signal of 4 outputs of modulus A/D conversion modulate circuit, these signals link to each other with the analog-to-digital conversion input port of the TMS320F2812 chip of digital signal processor circuit 1 respectively; The synchronizing signal of field programmable gate array circuit 2 outputs links to each other with the outer interrupting input end mouth of the TMS320F2812 chip of digital signal processor circuit 1; The two-way serial communication received signal of field programmable gate array circuit 2 output receives input ports with two serial ports of the TMS320F2812 chip of digital signal processor circuit 1 respectively and links to each other; The state level signal of one road field programmable gate array circuit 2 output links to each other with 1 basic input port of the TMS320F2812 chip of digital signal processor circuit 1.
The output signal of digital signal processor circuit 1: 12 road pulse-width signals (two level main circuit structures use 6 tunnel) link to each other with 12 input ports of field programmable gate array circuit 2 respectively; The two-way serial communication sends signal, links to each other with 2 input ports of field programmable gate array circuit respectively; The state level signal of one way word signal processor circuit, 1 output links to each other with 1 input port of field programmable gate array circuit 2.
Field programmable gate array circuit 2 has used 2,000,000 field programmable gate array chip FPGA, and model XC2S200, program storage XC18V02 and power circuit are formed, and circuit can be realized digital circuit by programming.The function that has after the programming mainly comprises pulse signal and handles (brachium pontis Dead Time, power electronic device minimum are opened and the minimum turn-off time), synchronizing signal processing, error protection processing generation pulse blocking signal, serial communication level conversion etc.
The signal of input field programmable gate array circuit 2: 12 road pulse-width signals of digital signal processor circuit 1 output link to each other with 12 input ports of field programmable gate array circuit 2 respectively; The synchronizing signal of 3 road lock unit circuit, 3 outputs links to each other with 3 input ports of field programmable gate array circuit 2 respectively; The signal of 8 road modulus A/D conversion modulate circuit, 4 outputs links to each other with 8 input ports of field programmable gate array circuit 2 respectively; The serial communication of 2 way word signal processor circuit, 1 output sends signal, links to each other with 2 input ports of field programmable gate array circuit 2 respectively; The serial ports received signal of 2 road serial communication circuits, 6 outputs links to each other with 2 input ports of field programmable gate array circuit 2 respectively; The state level signal of 1 way word signal processor circuit, 1 output links to each other with 1 input port of field programmable gate array circuit 2.
The signal of field programmable gate array circuit 2 outputs: 6 road pulse-width signals (three-phase two level bridge-type main circuit structures) output offers the power electronic device drive circuit; The output of 1 tunnel synchronizing signal links to each other with the outer interrupting input end mouth of the TMS320F2812 chip of digital signal processor circuit 1; 22 tunnel faults and status signal output link to each other with fault, condition indication circuit 7; 2 road serial ports received signals link to each other with TMS320F2812 chip serial ports receiving port on the digital signal processor circuit 1 respectively; 2 road serial ports send signal output, link to each other with serial communication circuit 6 respectively; The output of 1 line state level signal links to each other with the TMS320F2812 chip 1 basic input port of digital signal processor circuit 1.
With reference to Fig. 2, Fig. 2-A and Fig. 2-B, connector X1, X2 is and the interface of field programmable gate array circuit 2 that connector X1 has by the interface pin sequential signal: PPA1-PPF2 totally 12 road pulse-width signals input, the input of KKRST external reset signal, the input of RST reset signal, KIA-KID totally four passes by the input of stream signal, VDOV and the overvoltage of VDUV direct current and the input of under-voltage signal, K15V+ and the input of K15V-control power supply signal, the output of FPGOK status signal, SYNA1-SYNC1 totally 3 tunnel synchronizing signals input, the output of SXINT synchronizing signal, RS232S enables the rs 232 serial interface signal input, TXD1 and RXD1 are that the serial ports of DSP2812 serial ports 2 sends received signal, SCITXD1 and SCIRXD2 send received signal through the serial ports 2 that field programmable gate array circuit 2 is handled, TXD and RXD are the transmission received signal of DSP2812 serial ports 1, SCITXD and SCIRXD send received signal through the serial ports 1 that FPGA handles.Connector X2 has by the interface pin sequential signal: PA1-PF2 totally 12 road pwm pulses output, FTA-FTF is the arm fault-signal input of totally 3 road and bridge, the output of FDONE pulse control signal, the input of DSPOKDSP status signal, the output of PLOCK pulse blocking index signal, LKIA-LKID totally four the tunnel exchanges overcurrent and the output of direct current overcurrent index signal, LFTA-LFTC is the arm fault indication signal output of totally 3 road and bridge, the output of LK15V control power failure index signal, the output of KFT total failare index signal, the output of SYT field programmable gate array circuit 2 test signals.Connector X3, X4 are and the interface of DSP electronic circuit that connector X3 has by the interface pin sequential signal: the input of FPGOKFPGA status signal, TXD and RXD are that transmission received signal, the input of SXINT synchronizing signal, the PPA1-PPF2 of DSP2812 serial ports 1 is pwm pulse signal output.Connector X4 has by the interface pin sequential signal: TXD1 and RXD1 are that transmission received signal, the VREF of DSP2812 serial ports 2 is digital signal processor circuit 1 analog-to-digital conversion totally four road alternating currents and the signal input to be collected of direct current signal input to be collected, the signal input to be collected of ADUD direct voltage, ADUUV and ADUVW two-way ac line voltage, DSPOK digital signal processor circuit 1 status signal are exported with reference to high level output, ADIA-ADID.JP2 is that serial ports enables wire jumper; JP1 is that pulse blocking control enables wire jumper; XRST terminal, R190, O1 optocoupler, R191 constitute the external reset circuit; R188, O2 optocoupler, R189, XPLK terminal constitute the external blockade indicating circuit; XPOW1 is the control power input terminal; SYNIN is synchronous signal input end; XIA1 is an A cross streams current signal terminal; XIB1 is a B cross streams current signal terminal; XIC1 is a C cross streams current signal terminal; XID is the dc current signal terminal; XUD1 is the d. c. voltage signal terminal; XUVW1, XUVW2 are the ac voltage signal terminal; XDRA1-XDRC2 totally 6 be pwm pulse lead-out terminal and brachium pontis fault inverse signal terminal; RD1-RD4, LVD are the direct voltage sensor circuit; U3, U10, U11 DS75452N chip and R99, R100, R108, R110, R109, R111 constitute the pwm pulse control circuit.
With reference to Fig. 3, Fig. 3-C and Fig. 3-D, digital signal processor U1D (DSP) is the TMS320F2812 chip of TI company, draw required function pin signal and above-mentioned connector X3 and link to each other with signal on the X4 interface, pin uses identical English label to represent the connection of signal in the accompanying drawings.U5D is the active crystal oscillator of 30Mhz in the digital signal processor circuit, and output signal exports TMS320F2812 dsp chip 77 pins to after U4D SN74LVC1G14 level conversion; U3D TPS767D301, U6D TPS3838K33DBV and corresponding resistance capacitance constitute dsp chip working power management circuit, U3D input 5V voltage, output 1.8V links to each other with the working power pin of TMS320F2812DSP chip with the 3.3V direct voltage, and wherein R24D, S1D, C19D constitute the supply voltage reset circuit; U2D IS61LV6416-12T is 256K RAM; The 1.8V that digital signal processor circuit 1 AD conversion unit is used accordingly exports relevant voltage by magnetic bead L2D, L3D and filter capacitor with U3D with 3.3V voltage and links to each other, digitally link to each other by magnetic bead L4D with simulation ground, 3.3V voltage links to each other with TMS320F2812 dsp chip 69 pins by L1D and filter capacitor simultaneously, and embedded Flash operating voltage is provided; JP1D interface, R11D, R12D and corresponding TMS320F2812 dsp chip pin signal constitute the JTAG data communication interface, are used for linking to each other with simulator; JP2D, JP5D, JP6D, JP7D are wire jumper, for multi-functional pin provides high level or low level signal, are used for the selection of the multi-functional pin function of TMS320F2812 dsp chip.
With reference to Fig. 4, Fig. 4-E and Fig. 4-F, the field programmable gate array chip U2FA (FPGA) of field programmable gate array circuit 2 is the XC2S200-5PQ208C chip of Xilinx company, draw required input and output (I/O) signal and link to each other with the X2 interface signal with above-mentioned connector X1, pin uses identical English label to represent the connection of signal in the accompanying drawings.Clock signal is introduced by chip 80 pins; JZ1F is the active crystal oscillator of 50Mhz; VR1F REG1117-3.3 and VR2F REG1117-2.5 are the voltage transitions chip, and input 5V direct voltage is exported 3.3V and 2.5V direct voltage respectively, for U2F provides working power; U1FA is XC18V02 online programmable read-only memory (PROM) chip of Xilinx company, is used to preserve the configuration data of FPGA; JP1F is a jtag interface, is used for linking to each other with the data downloader; JP2F is a jumper terminal, is used to enable PROM.
With reference to Fig. 5, lock unit circuit 3, VINA be ± the 5V AC signal, chip U1SUAF42AP, and capacitor C 2S, C3S, resistance R AXS, RBXS, RCXS, RDXS, REXS form band pass filter, filtering interference signals, output signal is UA7.UA7 signal input in-phase proportion amplifier U4SA, select resistance R 1S, the size decision multiplication factor of R3S, make near the rate of change of signal zero point big like this, have to utilize and obtain the zero crossing pulse, output signal is imported reverse zero passage hysteresis loop comparator U4SB, use the zero passage hysteresis loop comparator to make input signal change slowly or amplitude hour, can eliminate owing to disturb the flutter phenomenon that in output voltage, may occur, resistance R 4S, the numerical value of R6S has determined threshold voltage, the output of hysteresis loop comparator is through resistance R 7S, R8S, it is 0V that the amplitude limiter circuit that diode Z1S forms obtains low level, high level is the zero crossing pulse of the input exchange signal of 5V, this pulse signal input U7SA model 74LS221, the monostable trigger-action circuit that resistance R 9S and diode C1S form, effectively detect the variation of signal rising edge, resistance R 9S, diode C1S has determined the monostable time, and output signal SYNA2 is the zero crossing lock-out pulse of input exchange signal.
With reference to Fig. 6; modulus A/D changes modulate circuit 4; IID is transducer output DC stream signal; signal amplitude is (concrete numerical value is relevant with current sensor circuit) within ± 3V; VREF is the analog-to-digital conversion reference voltage of 3V; amplifier U17ADA and resistance R 147AD; R148AD; R149AD; R171AD; capacitor C 81AD constitutes anti-phase adder; with the anti-phase translation of input signal with dwindle; amplifier U17ADB and resistance R 150AD; R151AD; R165AD formation multiplication factor is 1 inverter; diode D31AD; D32AD is the protection diode, and output ADID is that amplitude satisfies level requirement of TMS320F2812 dsp chip analog-to-digital conversion and the sampled signal consistent with the waveform input signal shape in 3V.
With reference to Fig. 7, overvoltage, overcurrent modulate circuit 5, IID is transducer output DC stream signal, signal amplitude is (concrete numerical value is relevant with current sensor circuit) within ± 3V, diode D12PR, D13PR, resistance R 5PR, R6PR, R8PR, the amplifier U4PRA composition peak detection circuit that is connected, the function of circuit is with the input signal rectification, resistance R 7PR, R9PR and capacitor C 1PR form high-frequency filter circuit, prevent interference signal, amplifier U9PRA is a voltage comparator, and the reference level of negative polarity end is REFIO, when the incoming level of positive ends is higher than REFIO, output KID shows generation direct current over current fault when being high level 5V, show during low level 0V that direct current does not have overcurrent.
With reference to Fig. 8, serial communication circuit 6, RXD1, TXD1 are the receiving and transmitting signal of serial ports 1, RXD2, TXD2 are the receiving and transmitting signal of serial ports 2, form level shifting circuit via chip J1 max232, capacitor C 3, C4, C5, C6, C7, the output signal high-low level is respectively 0V and 5V, and the receiving and transmitting signal of serial ports 1 is respectively SCIRXD, SCITXD, and the receiving and transmitting signal of serial ports 2 is respectively SCIRXD1, SCITXD1.
With reference to Fig. 9, fault, condition indication circuit 7, the fault of field programmable gate array circuit 2 outputs and status signal be totally 23 tunnel output difference series resistor and light-emitting diodes; R1, S1, E1 constitute reset circuit; Capacitor C 29-C70, E2-E10 are power filtering capacitor; VR2, R82, R94-R98, CV1-CV4, RVH1, RVL1, RIO1 are reference level circuit.
With reference to Figure 10, control power circuit 8, PS1 is a 30W 220V-15V AC-DC module; PS2 is 15W 220V-(a 15) V AC-DC module; PS3 is a 15W 220V-5V AC-DC module.
The double pulse width modulation controller of back to back structure voltage type current changing device of the present invention, under the immovable prerequisite of double pulse width modulation controller structure, the software program of double pulse width modulation controller can be according to the target control needs of concrete application scenario, according to automatic control technology and microcomputer data processing establishment, software programming is the technology that those skilled in the art are familiar with.
Claims (5)
1. the double pulse width modulation controller of a back to back structure voltage type current changing device, it is characterized in that: it comprises the circuit that two nested structures are identical, and every cover circuit is made up of digital signal processor circuit (1), field programmable gate array circuit (2), lock unit circuit (3), modulus A/D conversion modulate circuit (4), overvoltage, overcurrent modulate circuit (5) and serial communication circuit (6);
1) digital signal processor circuit (1) is used for that pwm pulses generates and serial communication control in analog-to-digital conversion, upper strata control algolithm, the bottom control, and the model of the digital signal processor DSP of digital signal processor circuit (1) is TMS320F2812;
2) field programmable gate array circuit (2) can be realized digital circuit by programming, the function that has after the programming comprises pulse signal processing, synchronizing signal processing, error protection is handled and produce pulse blocking signal, serial communication level conversion, and the model of the field programmable gate array chip FPGA of field programmable gate array circuit (2) is XC2S200;
3) lock unit circuit (3) is connected to form by band pass filter, hysteresis loop comparator and monostable trigger-action circuit, be used for the synchronous voltage signal after handling sent into and export digital signal processor circuit (1) to after field programmable gate array circuit (2) is handled, be used for convertor assembly incoming transport electrical network;
4) modulus A/D conversion modulate circuit (4) is that 1 inverter and interface level clamp circuit connect to form by anti-phase adder, multiplication factor, be used for the voltage and current signal is sent into digital signal processor circuit (1), digital signal processor carries out being used for the upper strata control algolithm after the analog-to-digital conversion;
5) overvoltage, overcurrent modulate circuit (5) are connected to form by peak detection circuit, high-frequency filter circuit and voltage comparator, be used for the voltage and current signal is sent into field programmable gate array circuit (2), to the monitoring of convertor assembly and the pulse blocking under the unusual condition;
6) input of serial communication circuit (6) links to each other with computer, and its input links to each other with field programmable gate array circuit (2), is used for communicating by letter between computer and digital signal processor circuit (1) and the field programmable gate array circuit (2).
2. the double pulse width modulation controller of back to back structure voltage type current changing device according to claim 1, it is characterized in that: the band pass filter of described lock unit circuit (3) is made up of following components and parts: model is the chip U1S of UAF42AP, be connected resistance R DXS between the pin 12 of signal input part and chip U1S, be connected capacitor C 2S between the pin 7 of chip U1S and the pin 8, be connected capacitor C 3S between chip U1S pin 1 and the pin 14, be connected resistance R AXS between the pin 12 of chip U1S and the pin 13, be connected resistance R BXS between the pin 8 of chip U1S and the pin 13, be connected resistance R CXS between the pin 7 of chip U1S and the pin 14, the pin 3 of chip U1S is connected with earth resistance REXS; The hysteresis loop comparator of described lock unit circuit (3) is made up of following components and parts: proportional amplifier U4SA, be connected resistance R 2S between the positive input terminal of the signal output part of band pass filter and proportional amplifier U4SA, the negative input end of proportional amplifier U4SA is connected with earth resistance R1S, is connected resistance R 3S between the output of proportional amplifier U4SA and its negative input end; Be connected resistance R 5S between the negative input end of the output of proportional amplifier U4SA and reverse zero passage hysteresis loop comparator U4SB, oppositely the positive input terminal of zero passage hysteresis loop comparator U4SB links to each other with earth resistance R4S, is connected resistance R 6S between the positive input terminal of reverse zero passage hysteresis loop comparator U4SB and its output; The monostable trigger-action circuit of described lock unit circuit (3) is made up of following components and parts: model is the chip U7SA of 74LS221, oppositely be connected resistance R 7S between the pin 1 of the output of zero passage hysteresis loop comparator U4SB and chip U7SA, be connected capacitor C 1S between the pin 14 of chip U7SA and the pin 15.
3. the double pulse width modulation controller of back to back structure voltage type current changing device according to claim 1, it is characterized in that: the anti-phase adder of described modulus A/D conversion modulate circuit (4) is made up of following components and parts: amplifier U17ADA, be connected resistance R 147AD between the negative input end of amplifier U17ADA and the input end of analog signal, be connected resistance R 148AD between the negative input end of amplifier U17ADA and the reference voltage input terminal, parallel resistance R171AD and capacitor C 81AD between the output of amplifier U17ADA and its negative input end, the positive input terminal of amplifier U17ADA links to each other with earth resistance R149AD; The multiplication factor of described modulus A/D conversion modulate circuit (4) is that 1 inverter is made up of following components and parts: amplifier U17ADB, be connected resistance R 150AD between the output of the negative input end of amplifier U17ADB and amplifier U17ADA, be connected resistance R 165AD between the negative input end of amplifier U17ADB and its output, the positive input terminal of amplifier U17ADB links to each other with earth resistance R151AD; The interface level clamp circuit of described modulus A/D conversion modulate circuit (4) is connected to form by diode D32AD and diode D31AD.
4. the double pulse width modulation controller of back to back structure voltage type current changing device according to claim 1, it is characterized in that: described overvoltage, the peak detection circuit of overcurrent modulate circuit (5) is made up of following components and parts: amplifier U4PRA, the positive input terminal ground connection of amplifier U4PRA, be connected resistance R 5PR between the negative input end of input end of analog signal and amplifier U4PRA, the negative input end of amplifier U4PRA is connected with resistance R 6PR one end, the resistance R 6PR other end is connected with diode D13PR anode, the output of amplifier U4PRA is connected with resistance R 8PR one end, the resistance R 8PR other end is connected with diode D13PR anode, the negative electrode of diode D13PR is connected with the negative electrode of diode D12PR, input end of analog signal is connected with the anode of diode D12PR, the negative electrode of diode D12PR is connected with resistance R 7PR one end, and the resistance R 7PR other end is connected with the positive input terminal of amplifier U9PRA; The high-frequency filter circuit of described overvoltage, overcurrent modulate circuit (5) is made up of resistance R 9PR between positive input terminal that is parallel to amplifier U9PRA and the ground and capacitor C 1PR; The voltage comparator of described overvoltage, overcurrent modulate circuit (5) is made up of following components and parts: amplifier U9PRA, reference voltage input terminal links to each other with the negative input end of amplifier U9PRA, the output of amplifier U9PRA links to each other with pull-up resistor R10PR one end, the pull-up resistor R10PR other end links to each other with power end, the output of amplifier U9PRA links to each other with resistance R 4PR one end, and the resistance R 4PR other end links to each other with direct-to-ground capacitance C2PR.
5. the double pulse width modulation controller of back to back structure voltage type current changing device according to claim 1, it is characterized in that: described serial communication circuit (6) is made up of following components and parts: model is the chip J1 of MAX232, the pin 1 of chip J1 connects the positive pole of capacitor C 3, the negative pole of capacitor C 3 links to each other with the pin 3 of chip J1, the pin 4 of chip J1 connects the positive pole of capacitor C 4, the negative pole of capacitor C 4 links to each other with the pin 5 of chip J1, the pin 2 of chip J1 links to each other with the positive pole of ground capacity C5, and the pin 6 of chip J1 links to each other with the negative pole of ground capacity C6.
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| CNB2006100170050A CN100405715C (en) | 2006-07-03 | 2006-07-03 | Double pulse width modulation controller for back to back structure voltage type current changing device |
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| CNB2006100170050A CN100405715C (en) | 2006-07-03 | 2006-07-03 | Double pulse width modulation controller for back to back structure voltage type current changing device |
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| CN1901338A CN1901338A (en) | 2007-01-24 |
| CN100405715C true CN100405715C (en) | 2008-07-23 |
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| CN102420566B (en) * | 2011-12-20 | 2014-07-16 | 东北大学 | Control device of brushless doubly-fed machine and control method thereof |
| TWI468710B (en) * | 2013-03-25 | 2015-01-11 | Test Research Inc | Testing apparatus for providing per pin level setting |
| CN104065360B (en) * | 2014-06-19 | 2017-01-04 | 航天科工惯性技术有限公司 | The nearly sinusoidal carrier generator that a kind of wide temperature is applied and frequency stable is controlled |
| CN105446345A (en) * | 2015-07-02 | 2016-03-30 | 浙江大学 | Control system of humanoid biped robot |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1719716A (en) * | 2005-07-08 | 2006-01-11 | 北京航空航天大学 | High-performance integrated magnetic suspension flywheel magnetic bearing digital controller |
| CN1731647A (en) * | 2005-09-01 | 2006-02-08 | 北京金自天正智能控制股份有限公司 | TCR controller |
| CN2781646Y (en) * | 2005-03-15 | 2006-05-17 | 北京华拿东方能源科技有限公司 | Digital intelligent controller for regulating speed of medium voltage motor by low voltage frequency transformer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2781646Y (en) * | 2005-03-15 | 2006-05-17 | 北京华拿东方能源科技有限公司 | Digital intelligent controller for regulating speed of medium voltage motor by low voltage frequency transformer |
| CN1719716A (en) * | 2005-07-08 | 2006-01-11 | 北京航空航天大学 | High-performance integrated magnetic suspension flywheel magnetic bearing digital controller |
| CN1731647A (en) * | 2005-09-01 | 2006-02-08 | 北京金自天正智能控制股份有限公司 | TCR controller |
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