CN100405531C - Method for preparing pitch of semiconductor - Google Patents
Method for preparing pitch of semiconductor Download PDFInfo
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- CN100405531C CN100405531C CNB2003101225678A CN200310122567A CN100405531C CN 100405531 C CN100405531 C CN 100405531C CN B2003101225678 A CNB2003101225678 A CN B2003101225678A CN 200310122567 A CN200310122567 A CN 200310122567A CN 100405531 C CN100405531 C CN 100405531C
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 94
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 37
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims description 305
- 229920005591 polysilicon Polymers 0.000 claims description 91
- 229920002120 photoresistant polymer Polymers 0.000 claims description 50
- 229920000642 polymer Polymers 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 30
- 239000013047 polymeric layer Substances 0.000 claims description 29
- 238000000059 patterning Methods 0.000 claims description 23
- 238000000576 coating method Methods 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 16
- 238000003973 irrigation Methods 0.000 claims description 13
- 230000002262 irrigation Effects 0.000 claims description 13
- 238000013138 pruning Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005137 deposition process Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 5
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 4
- 238000003701 mechanical milling Methods 0.000 claims description 4
- 238000004062 sedimentation Methods 0.000 claims description 4
- 239000002002 slurry Substances 0.000 claims description 4
- 239000006117 anti-reflective coating Substances 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 244000141353 Prunus domestica Species 0.000 description 15
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000009434 installation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 102100022717 Atypical chemokine receptor 1 Human genes 0.000 description 1
- 101000678879 Homo sapiens Atypical chemokine receptor 1 Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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Abstract
The present invention relates to a method for manufacturing a semiconductor pitch. Firstly, a base plate is provided; a brake oxidizing layer, a polycrystalline silicon layer and a patterned silicon nitride layer are orderly formed on the base plate; the patterned silicon nitride layer is provided with a first pitch and a plurality of first openings, and the size of each first opening is one quarter of that of the first pitch. A patterned oxide layer is formed to fill the first openings and cover a part of the patterned silicon nitride layer; the patterned oxide layer is provided with a first pitch and a plurality of second openings, and the second openings are staggered with the first openings of the lower part; the size of the second openings is one quarter of that of the first pitch. The exposed patterned silicon nitride layer is removed, and the other patterned silicon nitride layer is formed. In addition, the patterned silicon nitride layer is provided with a second pitch, a plurality of third openings and the first openings, wherein the second pitch is a half of the first pitch; the first openings are staggered with the third openings; the size of each third opening is a half of that of the second pitch. The patterned oxide layer is removed, the exposed first polycrystalline silicon layer is removed, and a first patterned polycrystalline silicon layer with the second pitch is formed.
Description
[technical field]
The invention relates to the manufacture method of a kind of semiconductor (semiconductor) pitch (pitch), and particularly relevant for a kind of manufacture method of semiconductor junctions distance of the pitch specification less than the step-scan machine.
[background technology]
In the epoch that development in science and technology is now maked rapid progress, electronic installation has become indispensable part in modern's life.Wherein, the reason that electronic installation can operate be its inside be equiped with integrated circuit (integrated circuit, IC), as logic IC and storage IC etc.These IC must be through semiconductor fabrication and finishing, and in the semiconductor fabrication, and little shadow technology has been acknowledged as in the making tool challenge, part that difficulty is also the highest.Along with step-scan machine (scanner) is constantly improved, its exposure wavelength is constantly derived, semiconductor factory is in order to do the manufacturing technology of 0.25-0.18 micron (μ m) at present, and the wavelength of its step-scan machine is 248 nanometers (nm), just can make the pitch of 248 nanometers.Nowadays semiconductor circle all is considered as 0.13 micron manufacturing technology of up-to-date competition target, and the wavelength of the step-scan machine equipment that it is required is then progressive to 193 nanometers (nm), but also can only make the pitch of 193 nanometers.
Please refer to Figure 1A～1C, illustrate the flow process profile of the manufacture method that is traditional semiconductor junctions distance.At first, in Figure 1A, provide a substrate 102,, and form a lock oxide layer 104 on substrate 102 as silicon substrate.Then, form a polysilicon layer 106 on lock oxide layer 104, and form a patterning photoresist layer 112 on polysilicon layer 106, shown in Figure 1B.Patterning photoresist layer 112 has a pitch P1 and several openings 111, and the big or small S1 of opening 111 is 1/2nd of pitch P1, and pitch P1 is the summation of the big or small S1 of live width (linewidth) W1 and opening 211.For example, be the step-scan machine (scanner) of 193 nanometers when carrying out little shadow action with wavelength, pitch P1 will be 200 nanometers, and the big or small S1 of live width W1 and opening 211 is all 100 nanometers.Then, the polysilicon layer 106 of etch exposed, and remove patterning photoresist layer 112, to form a patterned polysilicon layer 106a, shown in Fig. 1 C.Pitch P1 is 200 nanometers still, and the big or small S1 of live width W1 and opening 211 is all 100 nanometers.
Pursue compact and stress under the trend of high speed signal transmission at electronic installation now, semiconductor junctions will be apart from will be also littler than 200 nanometers, even arrive 100 nanometers, cause little shadow technology now will not apply practicality.But if the function of the step-scan machine of will upgrading, the semiconductor industry also will be paid a huge expense.So, how to use existing little shadow technology to obtain the also little semiconductor junctions distance of pitch specification of limiting than step-scan machine, will be the technical task of being badly in need of solution.
[summary of the invention]
In view of this, purpose of the present invention is exactly in the manufacture method that a kind of semiconductor junctions distance is provided, can obtain the semiconductor junctions distance also littler, can promote the drawingdimension of semiconductor junctions distance, and save the upgrade cost of step-scan machine than the gauge specification of step-scan machine.
According to purpose of the present invention, a kind of manufacture method of semiconductor junctions distance is proposed.At first, provide a substrate.Then, form a lock oxide layer on substrate.Then, form first polysilicon layer on the lock oxide layer.Then, form a patterned sin layer on first polysilicon layer, patterned sin layer has first segment distance and several first openings, and the size of each first opening is 1/4th of a first segment distance.Then, form a patterned oxide layer, to fill up the patterned sin layer of first opening and cover part, patterned oxide layer has first segment distance and several second openings, second opening system arranges with first interleaved openings of below, and the size of second opening is 1/4th of a first segment distance.Then, remove the patterned sin layer that exposes, to form another patterned sin layer, this patterned sin layer has second pitch, several the 3rd openings and first opening in addition, second pitch is half of first segment distance, first opening system arranges with the 3rd interleaved openings, and the size of each the 3rd opening is half of second pitch.Then, remove patterned oxide layer.Then, remove first polysilicon layer that exposes, to form the first patterned polysilicon layer, the first patterned polysilicon layer has second pitch.
According to a further object of the present invention, a kind of manufacture method of semiconductor junctions distance is proposed.At first, provide a substrate.Then, form a lock oxide layer on substrate.Then, form a patterned polysilicon layer on the lock oxide layer, the patterned polysilicon layer has first segment distance and several first openings, and the size of each opening is 1/4th of a first segment distance.Then, form the first patterned polymer layer, to fill up the patterned polysilicon layer of first opening and cover part, the first patterned polymer layer has first segment distance and several second openings, second opening system arranges with first interleaved openings of below, and the size of second opening is 1/4th of a first segment distance.Then, remove the patterned polysilicon layer that exposes, to form another patterned polysilicon layer, this patterned polysilicon layer has second pitch, several the 3rd openings and first opening in addition, second pitch is half of first segment distance, first opening system arranges with the 3rd interleaved openings, and the size of the 3rd opening is half of second pitch.
According to another purpose of the present invention, a kind of manufacture method of semiconductor junctions distance is proposed.At first, provide a substrate.Then, form a lock oxide layer on substrate.Then, form a polysilicon layer on the lock oxide layer.Then, form first patterned sin layer on polysilicon layer, first patterned sin layer has first segment distance and several first openings, and the size of first opening is 1/4th of a first segment distance.Then, form the patterned oxide layer and second patterned sin layer, this a little first openings fill up in patterned oxide layer system, and first patterned sin layer of cover part, patterned oxide layer has first segment distance and several second openings, and second opening system arranges with first interleaved openings of below.The size of second opening is that 1/4th, second patterned sin layer system of first segment distance is formed in second opening.Then, remove first patterned sin layer of second patterned sin layer and part, to form the 3rd patterned sin layer, the 3rd patterned sin layer has one second pitch, several the 3rd openings and first opening.Second pitch is that 1/2nd, first opening system of first segment distance arranges with the 3rd interleaved openings, and the size of the 3rd opening is half of this second pitch.Then, remove patterned oxide layer.Then, remove the polysilicon layer that exposes, to form a patterned polysilicon layer, the patterned polysilicon layer has second pitch.
[description of drawings]
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Figure 1A～1C is depicted as the flow process profile of the manufacture method of traditional semiconductor junctions distance;
Fig. 2 A～2L is depicted as the flow process profile according to the manufacture method of the semiconductor junctions distance of embodiments of the invention one;
Fig. 3 A～3J is depicted as the flow process profile according to the manufacture method of the semiconductor junctions distance of embodiments of the invention two;
Fig. 4 A～4K is depicted as the flow process profile according to the manufacture method of the semiconductor junctions distance of embodiments of the invention three.
[embodiment]
Embodiment one
Please refer to Fig. 2 A～2L, it is depicted as the flow process profile according to the manufacture method of the semiconductor of embodiments of the invention one (semiconductor) pitch (pitch).At first, in Fig. 2 A, one substrate 202 is provided, as silicon substrate, and on substrate 202, form a lock oxide (gate oxide) layer 204,1 first polysilicon (poly silicon) layer 206, one silicon nitride (silicon nitride, SiN) layer 208,1 second polysilicon layer 210 and a patterning photoresist layer (photo resist) 212 in regular turn.Patterning photoresist layer 212 has a pitch P1 and several openings 211, and the big or small S1 of opening 211 is 1/2nd of pitch P1, and P1 is the summation of the big or small S1 of live width (line width) W1 and opening 211.For example, be the step-scan machine (scanner) of 193 nanometers (nm) when carrying out little shadow action with wavelength, pitch P1 is 200 nanometers (nm), and the big or small S1 of live width W1 and opening 211 is all 100 nanometers (nm).In addition, present embodiment system can form an antireflection dielectric coatings (dielectric anti-reflection coating, DARC) between the silicon nitride layer 208 and second polysilicon layer 210 or between the silicon nitride layer 208 and first polysilicon layer 206, the integrality when being formed to increase patterning photoresist layer 212.
Then, prune (trimming) patterning photoresist layer 212, prune back photoresist layer 212a to form one, shown in Fig. 2 B.In Fig. 2 B, prune back photoresist layer 212a and have pitch P1 and several openings 213, the big or small S2 of opening 213 is about 3/4ths of pitch P1, as 150 nanometers.Live width W2 but is 1/4th of pitch P1, as 50 nanometers.Then, be etch stop (etch stop) layer of second polysilicon layer 210 with silicon nitride layer 208, and second polysilicon layer, 210, the second patterned polysilicon layer 210a that remove exposed portions will be formed, it is to finish with dry ecthing method, shown in Fig. 2 C.In Fig. 2 C, the second patterned polysilicon layer 210a has pitch P1 and several openings 215, and the big or small S3 of opening 215 equals 3/4ths of pitch P1, as 150 nanometers.After treating that the second patterned polysilicon layer 210a is formed, prune back patterning photoresist layer 212a and also can then be removed.
Then, (chemical vapor deposition CVD) forms a polymeric layer 214, and polymeric layer 214 is to cover to prune back photoresist layer 212a and silicon nitride layer 208, shown in Fig. 2 D with polymer (polymer) chemical vapour deposition technique.In Fig. 2 D, polymeric layer 214 has pitch P1 and several recesses 217, and recess 217 is the centres that are positioned at the opening 215 of Fig. 2 C, and the big or small S4 of each recess 217 is 1/4th of pitch P1, as 50 nanometers.
The present invention takes the reason of polymer chemistry vapour deposition process to be: the polymer chemistry vapour deposition process is than traditional plasma enhanced chemical vapor deposition method (plasma enhanced chemical vapor deposition, PECVD) have more and more extensively make window (wider process window), the polymeric layer of anisotropy (aniostropic) deposition form can be provided.That is to say that be positioned at the thickness of the deposit thickness of the polymeric layer 214 on the photoresist layer 212a after pruning greater than the polymeric layer under the recess 215 214, this is the place that PECVD does not accomplish.In addition, because the making temperature of polymer chemistry vapour deposition process is a room temperature, can protect the integrality of pruning back photoresist layer 212a, this also is to be difficult to adopted factor for PECVD that high temperature is made.
Then, with the etch stop of first polysilicon layer 206 as silicon nitride layer 208, and the silicon nitride layer 208 of the polymeric layer 214 of the part under the removal recess 217 and part, patterned sin layer 208a and patterned polymer layer 214a will be done, it is to finish with the anisotropy etching method, shown in Fig. 2 E.Patterned sin layer 208a has pitch P1 and several openings 219, and the big or small S5 of opening 219 is 1/4th of pitch P1, as 50 nanometers.
Then, remove patterned polymer layer 214a and prune back photoresist layer 212a, and form many irrigation canals and ditches 221 on first polysilicon layer 206.(high density plasma, HDP) sedimentation forms monoxide layer 216, shown in Fig. 2 F with high-density electric slurry again.In Fig. 2 F, oxide skin(coating) 216 is to fill up irrigation canals and ditches 221, and covers the second patterned polysilicon layer 210a.
Then, planarization oxide layer 216 is to form a patterned oxide layer 216a, and expose the second pattern polysilicon layer 210a, its be with chemical mechanical milling method (chemical mechanical polishing, CMP) or etch-back method (etch-back) finish, shown in Fig. 2 G.In Fig. 2 G, irrigation canals and ditches 221 just fill up in patterned oxide layer 216a system, and the end face copline of the end face of the patterned oxide layer 216a system and the second patterned polysilicon layer 210a.Then, remove the second patterned polysilicon layer 210a, make patterned oxide layer 216a have pitch P1 and several openings 223, shown in Fig. 2 H.In Fig. 2 H, the opening 223 of patterned oxide layer 216a is that the opening 219 with below patterned sin layer 208a is staggered, and the big or small S6 of opening 223 is 1/4th of pitch P1, as 50 nanometers.
Then, remove the patterned sin layer 208a that exposes, to form another patterned sin layer 208b, shown in Fig. 2 I.In Fig. 2 I, patterned sin layer 208b has a pitch P2, several openings 225 and opening 219, and pitch P2 is 1/2nd of pitch P1, as 100 nanometers.Opening 225 is to be staggered with opening 219, and the size of opening 225 equals 1/2nd of pitch P2, as 50 nanometers.Then, remove patterned oxide layer 216a, shown in Fig. 2 J.Then, remove first polysilicon layer 206 that exposes, to form the first patterned polysilicon layer 206a, shown in Fig. 2 K.In Fig. 2 K, the first patterned polysilicon layer 206a has pitch P2, as 100 nanometers.Then, remove patterned sin layer 208b, shown in Fig. 2 L.In Fig. 2 L, the live width W10 of the first patterned polysilicon layer 206a and the big or small S10 of opening are all half of pitch P2, as 50 nanometers.So the present invention can obtain the semiconductor junctions distance also littler than the pitch specification of existing step-scan machine, the upgrade cost that can save the step-scan machine.
Embodiment two
Please refer to Fig. 3 A～3H, be depicted as flow process profile according to the manufacture method of the semiconductor junctions distance of embodiments of the invention two.At first, in Fig. 3 A, provide a substrate 302,, and on substrate 302, form a lock oxide skin(coating) 304, a polysilicon layer 306, a silicon nitride layer 308 and patterning photoresist layer 312 in regular turn as silicon substrate.Patterning photoresist layer 312 has a pitch P1 and several openings 311, and the big or small S1 of opening 311 is 1/2nd of pitch P1, and P1 is the summation of the big or small S1 of live width W1 and opening 211.For example, be the step-scan machine of 193 nanometers when carrying out little shadow action with wavelength, pitch P1 is 200 nanometers, and the big or small S1 of live width W1 and opening 211 is all 100 nanometers.
Then, prune patterning photoresist layer 312, prune back photoresist layer 312a to form one, shown in Fig. 3 B.Prune back photoresist layer 312a and have pitch P1 and several openings 313, the big or small S2 of opening 313 is 3/4ths of pitch P1, as 150 nanometers.But live width W2 is 1/4th of pitch P1, as 50 nanometers.Then, remove the silicon nitride layer 308 that exposes, to form a patterned sin layer 308a, shown in Fig. 3 C.In Fig. 3 C, patterned sin layer 308a has pitch P1 and several openings 315, and the big or small S3 of opening 315 is 3/4ths of pitch P1, as 150 nanometers.
Then, form a polymeric layer 314 with a polymer chemistry vapour deposition process, shown in Fig. 3 D.In Fig. 3 D, polymeric layer 314 is the polysilicon layer 306 of cover part and prunes back photoresist layer 312a that polymeric layer 314 has pitch P1 and several recesses 317.Recess 317 is the centre that is positioned at the opening 315 of Fig. 3 C, and the big or small S4 of recess 317 is 1/4th of pitch P1, as 50 nanometers.Then, remove the polymeric layer 314 of the part under the recess 317 and the polysilicon layer 306 of part, to form patterned polymer layer 314a and patterned polysilicon layer 306a, shown in Fig. 3 E.In Fig. 3 E, patterned polysilicon layer 306a has pitch P1 and several openings 319, and the big or small S5 of opening 319 is 1/4th of pitch P1, as 50 nanometers.Then, remove patterned polymer layer 314a and prune back photoresist layer 312a, to form many irrigation canals and ditches 321 on lock oxide layer 304.Form a polymeric layer 316 again, to fill up irrigation canals and ditches 321 and overlay pattern silicon nitride layer 308a, shown in Fig. 3 F.In Fig. 3 F, polymeric layer 316 for example be an end antireflective coating (bottom anti-reflection coating, BARC).
Then, planarization polymeric layer 316 with formation patterned polymer layer 316a, and exposes patterned sin layer 308a, and it is to finish with the etch-back method, shown in Fig. 3 G.Then, remove patterned sin layer 308a, make patterned polymer layer 316a have pitch P1 and several openings 323, shown in Fig. 3 H.The opening 323 of patterned sin layer 308a is that the opening 319 with below patterned polysilicon layer 306a is staggered, and the big or small S6 of opening 323 is 1/4th of pitch P1, as 50 nanometers.Then, remove the patterned polysilicon layer 306a that exposes, to form another patterned polysilicon layer 306b, shown in 3I figure.Patterned polysilicon layer 306b has pitch P2, several openings 325 and 319, and pitch P2 is 1/2nd of pitch P1, as 100 nanometers.Opening 325 is to be staggered with opening 319, and the big or small S7 of opening 325 is half of pitch P2, as 50 nanometers.Then, remove patterned polymer layer 316a, shown in 3J figure.Wherein, the live width W10 of patterned polysilicon layer 306b and the big or small S10 of opening are all half of pitch P2, as 50 nanometers.So the present invention can obtain the semiconductor junctions distance also littler than the pitch specification of existing step-scan machine, the upgrade cost that can save the step-scan machine.
Embodiment three
Please refer to Fig. 4 A～4K, be depicted as flow process profile according to the manufacture method of the semiconductor junctions distance of embodiments of the invention three.At first, in Fig. 4 A, provide a substrate 402,, and on substrate 402, form a lock oxide skin(coating) 404, a polysilicon layer 406, one first silicon nitride layer 408, one second silicon nitride layer 409 and a patterning photoresist layer 412 in regular turn as silicon substrate.Patterning photoresist layer 412 has a pitch P1 and several openings 411, and the big or small S1 of opening 411 is 1/2nd of pitch P1, and P1 is the summation of the big or small S1 of live width W1 and opening 411.For example, be the step-scan machine of 193 nanometers when carrying out little shadow action with wavelength, pitch P1 is 200 nanometers, and the big or small S1 of live width W1 and opening 411 is all 100 nanometers.
Then, prune patterning photoresist layer 412, prune back photoresist layer 412a to form one, shown in Fig. 4 B.In Fig. 4 B, prune back photoresist layer 412a and have pitch P1 and several openings 413, the big or small S2 of opening 413 is about 3/4ths of pitch P1, as 150 nanometers.But live width W2 is 1/4th of pitch P1, as 50 nanometers.Then, remove second silicon nitride layer 409 of exposed portions, to form one second patterned sin layer 409a, shown in Fig. 4 C.The second patterned sin layer 409a has pitch P1 and several openings 415, and the big or small S3 of opening 415 equals 3/4ths of pitch P1, as 150 nanometers.
Then, form a polymeric layer 414 with the polymer chemistry vapour deposition process, polymeric layer 414 is to cover first silicon nitride layer 408 of pruning back photoresist layer 412a and part, shown in Fig. 4 D.Polymeric layer 414 has pitch P1 and several recesses 417, and recess 417 is the centre that is positioned at the opening 415 of Fig. 4 C, and the big or small S4 of recess 417 is 1/4th of pitch P1, as 50 nanometers.
Then, remove the polymeric layer 414 of the part under the recess 417 and first silicon nitride layer 408 of part, to form the first patterned sin layer 408a and patterned polymer layer 414a, shown in Fig. 4 E.The first patterned sin layer 408a has pitch P1 and several openings 419, and the big or small S5 of opening 419 is 1/4th of pitch P1, as 50 nanometers.Then, remove patterned polymer layer 414a and prune back photoresist layer 412a, to form many irrigation canals and ditches 421 on polysilicon layer 406.Form monoxide layer 416 with the high-density electric slurry sedimentation again, oxide skin(coating) 416 is to fill up irrigation canals and ditches 421 and cover the second patterned sin layer 409a, shown in Fig. 4 F.
Then, planarization oxide layer 416 forming a patterned oxide layer 416a, and exposes the second pattern silicon nitride layer 409a, and it is to finish with chemical mechanical milling method or etch-back method, shown in Fig. 4 G.Then, remove the first patterned sin layer 408a of the part of the second patterned sin layer 409a and below thereof, to form one the 3rd patterned sin layer 408b, shown in Fig. 4 H.The 3rd patterned sin layer 408b has a pitch P2, several openings 423 and opening 419, and pitch P2 is 1/2nd of pitch P1, as 100 nanometers.Opening 423 is to be staggered with opening 419, and the big or small S6 of opening 423 equals 1/2nd of pitch P2, as 50 nanometers.Then, remove patterned oxide layer 416a, shown in Fig. 4 I.Then, remove the polysilicon layer 406 that exposes, to form patterned polysilicon layer 406a, shown in Fig. 4 J.Patterned polysilicon layer 406a has pitch P2, as 100 nanometers.Then, remove the 3rd patterned sin layer 408b, shown in Fig. 4 K.The live width W10 of patterned polysilicon layer 406a and the big or small S10 of opening are all half of pitch P2, as 50 nanometers.
The manufacture method of the disclosed semiconductor junctions distance of the above embodiment of the present invention can obtain also little or even half the semiconductor junctions distance of gauge specification than step-scan machine.Thus, can promote the drawingdimension of semiconductor junctions distance, and save many upgrade costs that are used as the step-scan machine, quite meet economic benefit.
In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; any personnel that are familiar with this field; without departing from the spirit and scope of the present invention; when can doing various modifications, so the scope that claims defined that protection scope of the present invention should basis is as the criterion.
Claims (18)
1. the manufacture method of a semiconductor junctions distance comprises at least:
One substrate is provided;
Form a lock oxide layer on this substrate;
Form one first polysilicon layer on this lock oxide layer;
Form a silicon nitride layer on this first polysilicon layer;
Form one second polysilicon layer on this silicon nitride layer;
Form a patterning photoresist layer on this second polysilicon layer, this patterning photoresist layer has this first segment distance and a plurality of first opening, and respectively the size of this first opening is 1/2nd of this first segment distance;
Prune this patterning photoresist layer, prune the back photoresist layer to form one, this pruning back photoresist layer has this first segment distance and a plurality of second opening, and respectively the size of this second opening is 3/4ths of this first segment distance;
Remove this second polysilicon layer that exposes, to form one second patterned polysilicon layer, this second patterned polysilicon layer has this first segment distance and a plurality of the 3rd opening, respectively the size of the 3rd opening is 3/4ths of this first segment distance, and the pattern line-width of this second patterned polysilicon layer is 1/4th of this first segment distance;
Form a polymeric layer with a polymer chemistry vapour deposition process, this silicon nitride layer of this polymer series of strata cover part and this are pruned the back photoresist layer, this polymeric layer has this first segment distance and a plurality of recess, respectively this recess system is positioned at the respectively centre of the 3rd opening, and respectively the size of this recess is 1/4th of this first segment distance;
Remove this polymeric layer of the part under those recesses and this silicon nitride layer of part, to form a patterned polymer layer and this patterned sin layer, this patterned sin layer has first segment distance and a plurality of the 4th opening, and respectively the size of the 4th opening is 1/4th of this first segment distance;
Form a patterned oxide layer, to fill up this patterned sin layer of those the 4th openings and cover part, this patterned oxide layer has this first segment distance and a plurality of the 5th opening, the position of the 5th opening is corresponding with the pattern of this second patterned polysilicon layer, respectively the size of the 5th opening system equals 1/4th of this first segment distance, and those the 5th opening systems arrange with those the 4th interleaved openings of below;
Remove this patterned oxide layer; And
Remove this first polysilicon layer that exposes, to form one first patterned polysilicon layer, this first patterned polysilicon layer has this second pitch.
2. method according to claim 1 is characterized in that, this method lies in this step that forms a patterned oxide layer and more comprises:
Remove this patterned polymer layer and this pruning back photoresist layer, and form several irrigation canals and ditches on this first polysilicon layer;
Form the monoxide layer with a high-density electric slurry sedimentation, these oxide series of strata are filled up those irrigation canals and ditches and are covered this second patterned polysilicon layer;
This oxide skin(coating) of planarization is to form this patterned oxide layer and to expose this second patterned polysilicon layer; And
Remove this second patterned polysilicon layer, make this patterned oxide layer have this first segment distance and those the 5th openings.
3. method according to claim 2 is characterized in that, this method lies in the step of this this oxide skin(coating) of planarization and more comprises:
With this oxide skin(coating) of chemical mechanical milling method planarization.
4. method according to claim 2 is characterized in that, this method lies in the step of this this oxide skin(coating) of planarization and more comprises:
With this oxide skin(coating) of etch-back method planarization.
5. method according to claim 1 is characterized in that, this method more comprises after lying in this step that forms one first patterned polysilicon layer:
Remove this patterned sin layer in addition.
6. method according to claim 1 is characterized in that, this substrate is a silicon substrate.
7. method according to claim 1 is characterized in that, on this patterned sin layer is to form an antireflection dielectric coatings.
8. the manufacture method of a semiconductor junctions distance comprises at least:
One substrate is provided;
Form a lock oxide layer on this substrate;
Form a polysilicon layer on this lock oxide layer;
Form a silicon nitride layer on this polysilicon layer;
Form a patterning photoresist layer on this silicon nitride layer, this patterning photoresist layer has this first segment distance and a plurality of first opening, and respectively the size of this first opening is 1/2nd of this first segment distance;
Prune this patterning photoresist layer, prune the back photoresist layer to form one, this pruning back photoresist layer has this first segment distance and a plurality of second opening, and respectively the size of this second opening is 3/4ths of this first segment distance;
Remove this silicon nitride layer that exposes, to form a patterned sin layer, this patterned sin layer has this first segment distance and a plurality of the 3rd opening, respectively the size of the 3rd opening is 3/4ths of this first segment distance, and the pattern line-width of this patterned sin layer is 1/4th of this first segment distance;
Form one first polymeric layer with a polymer chemistry vapour deposition process, this polysilicon layer of this first polymer series of strata cover part and this are pruned the back photoresist layer, this first polymeric layer has this first segment distance and a plurality of recess, respectively this recess system is positioned at the respectively centre of the 3rd opening, and respectively the size of this recess is 1/4th of this first segment distance; And
Remove this first polymeric layer of the part under those recesses and this polysilicon layer of part, to form one first patterned polymer layer and this patterned polysilicon layer, this patterned polysilicon layer has first segment distance and a plurality of the 4th opening, and respectively the size of the 4th opening is 1/4th of this first segment distance;
Remove this first patterned polymer layer and this pruning back photoresist layer, to form a plurality of irrigation canals and ditches on this lock oxide layer;
Form a second polymer layer, those the 4th openings and those irrigation canals and ditches fill up in this second polymer layer system, and non-this patterned polysilicon layer in cover part and this patterned sin layer;
This second polymer layer of planarization, to form this second patterned polymer layer and to expose this patterned sin layer, this second patterned polymer layer has this first segment distance and a plurality of the 5th opening, respectively the size of the 5th opening is 1/4th of this first segment distance, and those the 5th opening systems arrange with those the 4th interleaved openings of below;
Remove the The patterned sin layer; And
Remove this patterned polysilicon layer that exposes, to form another patterned polysilicon layer, this patterned polysilicon layer has one second pitch, a plurality of the 6th opening and those the 4th openings in addition, this second pitch is half of this first segment distance, respectively the size of the 6th opening is half of this second pitch, and those the 4th opening systems arrange with those the 6th interleaved openings.
9. method according to claim 8 is characterized in that, this method lies in the step of this first polymeric layer of this planarization and more comprises:
With this first polymeric layer of etch-back method planarization.
10. method according to claim 8 is characterized in that, this method more comprises after lying in the step of this patterned polysilicon layer that this removal exposes:
Remove this first patterned polymer layer.
11. method according to claim 8 is characterized in that, this substrate is a silicon substrate.
12. method according to claim 8 is characterized in that, this first patterned polymer series of strata, one end antireflective coating.
13. the manufacture method of a semiconductor junctions distance comprises at least:
One substrate is provided;
Form a lock oxide layer on this substrate;
Form a polysilicon layer on this lock oxide layer;
Form one first silicon nitride layer on this polysilicon layer;
Form one second silicon nitride layer on this first silicon nitride layer;
Form a patterning photoresist layer on this second silicon nitride layer, this patterning photoresist layer has this first segment distance and a plurality of first opening, and respectively the size of this first opening is 1/2nd of this first segment distance;
Prune this patterning photoresist layer, prune the back photoresist layer to form one, this pruning back photoresist layer has this first segment distance and a plurality of second opening, and respectively the size of this second opening is 3/4ths of this first segment distance;
Remove this second silicon nitride layer that exposes, to form one second patterned sin layer, this second patterned sin layer has this first segment distance and a plurality of the 3rd opening, and respectively the 3rd opening is 3/4ths of this first segment distance;
Form a polymeric layer with the long-pending method in a polymer chemistry gas phase Shen, this first silicon nitride layer of this polymer series of strata cover part and this are pruned the back photoresist layer, this polymeric layer has this first segment distance and a plurality of recess, respectively this recess system is positioned at the respectively centre of the 3rd opening, and respectively the size of this recess is 1/4th of this first segment distance;
Remove this first polymeric layer of the part under those recesses and this first silicon nitride layer of part, to form a patterned polymer layer and this first patterned sin layer, this first patterned sin layer has first segment distance and a plurality of the 4th opening, and respectively the size of the 4th opening is 1/4th of this first segment distance;
Form a patterned oxide layer, those the 4th openings fill up in this patterned oxide layer system, and this first patterned sin layer of cover part, this patterned oxide layer has this first segment distance and a plurality of the 5th opening, those the 5th opening systems arrange with those the 4th interleaved openings of below, respectively the size of the 5th opening is 1/4th of this first segment distance, and this second patterned sin layer system is arranged in those second openings;
Remove this first patterned sin layer of the part of this second patterned sin layer and below, to form one the 3rd patterned sin layer, the 3rd patterned sin layer has one second pitch, a plurality of the 6th opening and those the 4th openings, this second pitch is 1/2nd of this first segment distance, respectively the size of the 6th opening is half of this second pitch, and those the 4th opening systems arrange with those the 6th interleaved openings;
Remove this patterned oxide layer; And
Remove this polysilicon layer that exposes, to form a patterned polysilicon layer, this patterned polysilicon layer has this second pitch.
14. method according to claim 13 is characterized in that, this method lies in this step that forms a patterned oxide layer and one second patterned sin layer and more comprises:
Remove this patterned polymer layer and this pruning back photoresist layer, to form a plurality of irrigation canals and ditches on this polysilicon layer;
Form the monoxide layer with a high-density electric slurry sedimentation, these oxide series of strata are filled up those irrigation canals and ditches and are covered this second patterned sin layer; And
This oxide skin(coating) of planarization is to form this patterned oxide layer and to expose this second patterned sin layer.
15. method according to claim 14 is characterized in that, this method lies in the step of this this oxide skin(coating) of planarization and more comprises:
With this oxide skin(coating) of chemical mechanical milling method planarization.
16. method according to claim 14 is characterized in that, this method lies in the step of this this oxide skin(coating) of planarization and more comprises:
With this oxide skin(coating) of etch-back method planarization.
17. method according to claim 13 is characterized in that, this method more comprises after lying in this step that forms a patterned polysilicon layer:
Remove the 3rd patterned sin layer.
18. method according to claim 13 is characterized in that, this substrate is a silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101225678A CN100405531C (en) | 2003-12-12 | 2003-12-12 | Method for preparing pitch of semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101225678A CN100405531C (en) | 2003-12-12 | 2003-12-12 | Method for preparing pitch of semiconductor |
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| CN1627474A CN1627474A (en) | 2005-06-15 |
| CN100405531C true CN100405531C (en) | 2008-07-23 |
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| CNB2003101225678A Expired - Lifetime CN100405531C (en) | 2003-12-12 | 2003-12-12 | Method for preparing pitch of semiconductor |
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| CN102832108A (en) * | 2012-09-17 | 2012-12-19 | 东莞市天域半导体科技有限公司 | Method for realizing submicron-level process line width in manufacturing of silicon carbide power electronic devices |
| CN113634831A (en) * | 2020-05-11 | 2021-11-12 | 光群雷射科技股份有限公司 | Seamless hologram pattern transfer method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100837A (en) * | 1998-01-14 | 2000-08-08 | Mitsubishi Denki Kabushiki Kaisha | A-D converter |
| US6416933B1 (en) * | 1999-04-01 | 2002-07-09 | Advanced Micro Devices, Inc. | Method to produce small space pattern using plasma polymerization layer |
| US6537866B1 (en) * | 2000-10-18 | 2003-03-25 | Advanced Micro Devices, Inc. | Method of forming narrow insulating spacers for use in reducing minimum component size |
| US20030203285A1 (en) * | 2002-04-26 | 2003-10-30 | Chung Henry Wei-Ming | Method of fabricating phase shift mask |
-
2003
- 2003-12-12 CN CNB2003101225678A patent/CN100405531C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100837A (en) * | 1998-01-14 | 2000-08-08 | Mitsubishi Denki Kabushiki Kaisha | A-D converter |
| US6416933B1 (en) * | 1999-04-01 | 2002-07-09 | Advanced Micro Devices, Inc. | Method to produce small space pattern using plasma polymerization layer |
| US6537866B1 (en) * | 2000-10-18 | 2003-03-25 | Advanced Micro Devices, Inc. | Method of forming narrow insulating spacers for use in reducing minimum component size |
| US20030203285A1 (en) * | 2002-04-26 | 2003-10-30 | Chung Henry Wei-Ming | Method of fabricating phase shift mask |
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| CN1627474A (en) | 2005-06-15 |
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