CN100405328C - Method for improving data transmission efficiency - Google Patents
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- CN100405328C CN100405328C CNB2005101260276A CN200510126027A CN100405328C CN 100405328 C CN100405328 C CN 100405328C CN B2005101260276 A CNB2005101260276 A CN B2005101260276A CN 200510126027 A CN200510126027 A CN 200510126027A CN 100405328 C CN100405328 C CN 100405328C
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Abstract
The present invention relates to a method for improving the data transmission efficiency of a multimedia playing device, which comprises the steps that the address of requested data is read, and then, whether the address of the requested data is larger than an initial reading address is detected, wherein the initial reading address is the first reading address of sequential reading data. If the address of the request data is larger than the initial reading address and is not positioned in a critical zone of a transmitted decoding data area, the requested data is read from the transmitted decoding data area.
Description
Technical field
The present invention is about a kind of method of improving data transmission efficiency, particularly a kind of method of improving data transmission efficiency that is applied to multimedia playing apparatus.
Background technology
Please refer to Fig. 1, it is the synoptic diagram of conventional digital disk player (Digital Versatile Discplayer, DVD player) 100.Do not mentioning that the part-structure of optical digital disk playing device 100 has been simplified omission under the situation that prior art discloses.One optical digital disk playing device 100 comprises a DRAM (Dynamic Random Access Memory) (dynamic random access memory substantially, DRAM) 104 and one chip (chip) 108, one ring buffer zone (ring buffer) 106 is wherein arranged in the DRAM (Dynamic Random Access Memory) 104, and a demoder (decoder) 110 is arranged in the chip 108.Optical digital disk playing device 100 is used for reading data stored on the disc 102, chip 108 can write to disc 102 stored data earlier ring buffer zone 106, write full 16 sections (sector) afterwards whenever writing data, again the data of these storages are sent back demoders 110 decodings in the chip 108, at last with decoded data transmission to main frame 112, handle the usefulness of computing as follow-up data.
Please refer to Fig. 2, its address for ring buffer zone 106 inside corresponds to the synoptic diagram of disc 102 addresses.In this embodiment, the size of ring buffer zone 106 is 160 sections (sector).As shown in the figure, chip 108 can write to disc 102 stored data ring buffer zone 106 constantly, at first begins to write data by address 0, is all write full up to the 160th section.Afterwards, write data can be again from the address 0 data that write before writing constantly and overriding, also therefore be called as the ring buffer zone.
In ring buffer zone 200, write address (write index) 210 for writing the address of data, the address of the data that decode address (decode index) 212 has write for decoding, host address (host index) 214 is the addresses of the decoded data of transmission to main frame.In addition, data clear area (unused data area) 202 for writing the zone before the address, also represents that this distinguishes not deposit any data as yet.Decoded data district (un-decoded data area) the 204th between the zone that writes between address 210 and the decode address 212, do not represent the data field that has write ring buffer zone 200 but do not decoded as yet.Do not transmit decoded data district (un-transferred decoded dataarea) the 206th, the zone between decode address 212 and host address 214, representative does not transfer to the district of decoded data of main frame as yet.On the contrary, transmitted decoded data district (transferreddecoded data area) the 208th, between host address 214 and write zone between the address 210, its representative has transferred to the district of decoded data of main frame.
Generally speaking, main frame 112 can read the data of a certain address on the disc 102 (be the address 216 of request msg in the present embodiment) by indication chips 108, then the request msg of this corresponding address can be in ring buffer zone 106 wait transfer to main frame 112 again after decoded.In known technology, the request msg of address 216 correspondences of request msg is positioned at does not transmit decoded data district 206, is called high-speed cache success (cache hit), and then request msg will directly transfer to main frame 112.Do not transmit decoded data district 206 if the request msg of address 216 correspondences of request msg is positioned at, be called high-speed cache failure (cache miss), then main frame 112 needs the address 216 that read request msg once more from disc 102.In this embodiment, a buffering start address (buffer start address) 218 is the address of host address 214 disc that corresponds to 102.
Fig. 3 is the process flow diagram of prior art one embodiment.At first, the address 216 (square 302) that main frame 112 indication chips 108 read a request msg, whether the request msg of then detecting address 216 correspondences of request msg is positioned at does not transmit decoded data district 206 (square 304).If request msg is not positioned at and does not transmit decoded data district 206, then be judged to be the high-speed cache failure, then main frame 112 indication chips 108 address 216 (square 306) of reading request msg again from disc 102.If request msg is positioned at and does not transmit decoded data district 206, judge again then whether host address 214 points to the address 216 of request msg (square 308), if host address 214 does not point to the address 216 of request msg, then correct host address 214 and make it to point to the address 216 (square 310) of request msg, then read request msg (square 312) from host address 214.In addition, if host address 214 has pointed to the address 216 of request msg, then directly read request msg (square 312) from host address 214.
Based on above-mentioned, in known technology, when request msg falls into when transmitting decoded data district 208, because whether uncertain request msg is also in transmitting decoded data district 208, or be sent to main frame 112, even the data that also may be write again in transmitting decoded data district 208 when request msg override, can judge that this kind situation is the high-speed cache failure this moment, the address 216 that need read request msg again from disc 102, that is need execution seek rail (seeking), focus on (focusing), follow the address 216 that request msg is read in rail actions such as (tracking).This shows, because playing device 100 must can make broadcasting speed slack-off again from disc 102 reading of data, and will see the phenomenon that image pauses, and then reduce the efficient of computer processing data.
Summary of the invention
The invention provides a kind of method of improving data transmission efficiency, a kind of method of improving data transmission efficiency that is applied to multimedia playing apparatus particularly is provided.
Based on above-mentioned, the invention provides a kind of method of improving data transmission efficiency that is applied to multimedia playing apparatus, the method comprises: the address of reading a request msg; And whether the address of detecting this request msg initially reads the address greater than one; Wherein initially read the address greater than this, judge then whether this request msg is positioned at one and has transmitted the decoded data district, not, then read the address of this request msg again, and upgrade this and initially read the address when the address of this request msg.When this request msg is not positioned at this and has transmitted the decoded data district, then detect the address whether a host address points to this request msg; And when this request msg is positioned at this and has transmitted the decoded data district, judge then whether this request msg is positioned at a critical section.When this request msg is positioned at this critical section, then be judged to be the high-speed cache failure, and the address of reading this request msg again, and upgrade this and initially read the address.When this request msg is not positioned at this critical section, then correct the address that this host address makes it to point to this request msg; And judge the high-speed cache success, read this request msg from this host address.Point to the address of this request msg when detecting this host address, then judge the high-speed cache success, read this request msg from this host address; Not, then correct the address that this host address makes it to point to this request msg earlier, judge the high-speed cache success again, read this request msg from this host address.
According to the method for improving data transmission efficiency that is applied to multimedia playing apparatus in one embodiment of the invention,, more comprise: judge whether an action that writes data stops if the described request data are positioned at described described critical section of having transmitted the decoded data district; If stop, then correcting the address that described host address makes it to point to the described request data earlier, judge the high-speed cache success again and read the described request data from described host address; And, then be judged to be the high-speed cache failure if do not stop, reading the address of described request data again and upgrade the described address of initially reading.
Now cooperate graphic preferred embodiment of the present invention to be described in detail as follows, but this explanation only is used for illustrating the present invention, but not interest field of the present invention is done any restriction.
Description of drawings
Fig. 1 is the synoptic diagram of a conventional digital disk player;
Fig. 2 is the synoptic diagram of an embodiment of prior art;
Fig. 3 is the process flow diagram of an embodiment of prior art;
Fig. 4 is the synoptic diagram of one embodiment of the invention;
Fig. 5 is the synoptic diagram of another embodiment of the present invention;
Fig. 6 is the process flow diagram of one embodiment of the invention; And
Fig. 7 is the process flow diagram of another embodiment of the present invention.
The element numbers explanation:
100: optical digital disk playing device 102: disc
104: DRAM (Dynamic Random Access Memory) 106: the ring buffer zone
108: chip 110: demoder
112: main frame 202,402: data clear area
204,404: decoded data district not
206,406: do not transmit decoded data district
208,408: transmitted the decoded data district
210,410: write address 212,412: decode address
214,414: host address 216,418: the address of request msg
218,422: buffering start address 302～312: step
400: ring buffer zone 416: initially read the address
602～618: step 702～716: step
Embodiment
The invention provides a kind of method of improving data transmission efficiency that is applied to multimedia playing apparatus.Below enumerate a preferred embodiment now with explanation the present invention, so be familiar with this operator and know that all this only is one for example, but not in order to restriction invention self, about the detailed description of this preferred embodiment as follows.
Please refer to the 4th figure, it is the synoptic diagram of one embodiment of the invention.Ring buffer zone 400 in multimedia playing apparatus is set one and is initially read address (cache start address) 416, and it is that first that read data in the disc 102 reads the address, and is simultaneously corresponding to address 0 part of encircling in the buffer zone 400.For instance, the size of supposing the ring buffer zone 400 in the optical digital disk playing device is 160 sections, and this time begin to read to the 400th section by the 200th section of disc 102, then the 200th section just read for this first read the address, also be initial read and get address 416.After the high-speed cache failure, just can reset and initially read address 416.Therefore, when the address 418 of request msg is read in the main frame indication, if the address 418 of request msg is less than initially reading address 416, main frame can be judged to be the high-speed cache failure, therefore needs again to read the address 418 of request msg and upgrade and initially read address 416 from disc 102.If the address 418 of request msg is greater than initially reading address 416, be the high-speed cache success, represent the address 418 of request msg to be positioned at not transmit decoded data district 406 or transmitted decoded data district 408, then can never transmit decoded data district 406 respectively or transmit in the decoded data district 408 and read request msg.For instance, supposing initially to read address 416 is the 4th section, and the address 418 of request msg is the 1st section.Read the address owing to initially read address 416 for first of each reading of data in proper order, therefore the position before the 4th section may be data clear area 402.This moment request msg address 418 less than initially reading address 416, the address of expression request msg 418 is read in the process at this and never was read, so that be judged as the high-speed cache failure, needs the address 418 that read request msg again from disc 102.If initially read address 416 is the 4th section, and the address 418 of request msg is the 8th section, because the address 418 of request msg is greater than initially reading address 416, transmitted decoded data district 408 or do not transmitted decoded data district 406 so the address 418 of request msg may be positioned at, so be judged to be the high-speed cache success, can from these data fields, read request msg.In addition, multimedia playing apparatus can be digitized video recorder or digitized video player.
Please refer to the 5th figure, it is the synoptic diagram of another embodiment of the present invention.Its framework is roughly identical with the 4th figure, and (please refer to Fig. 4) in this preferred embodiment, and the address 418 of request msg needs greater than initially reading address 416, and Figure 5 shows that ring buffer zone 400 write the synoptic diagram after full.One critical section 420 is positioned at and transmits decoded data district 408, and its size is for writing address 410 m section before, and for example the size of critical section 420 is to write address 410 5 sections before.Right be familiar with this operator and know that all this only is one for example, but not invent self, be familiar with this operator and can change required numerical value according to practical application in order to limit.When if request msg is positioned at the critical section 420 of transmitting decoded data district 408, and one writes mark is set up, represent that then write activity carries out, the data that the request msg that read this moment may be write again override, so that can't read request msg originally, so main frame 112 can be judged to be the high-speed cache failure; If request msg is when being positioned at the critical section 420 of transmitting decoded data district 408, and when writing mark and not being set up, expression does not have the action that writes data at present, and it is successful that this moment, main frame 112 can be judged to be high-speed cache.
For instance, supposing initially to read address 416 is the 50th section, and the size in decoded data district 404 is not 20 sections, and the size in decoded data district 406 is 10 sections and do not transmit, if the address 418 of request msg is the 200th section, buffering start address 422 is the 360th section.The distance that the address of calculating buffering start address 422 and request msg is 418 is 160 sections (360-200=160).Buffering start address 422 deductions do not transmit decoded data district 406 (10 sections) and the not size in decoded data district 404 (20 sections), and the numerical value that obtains also is 130 sections (160-10-20=130) for having transmitted the size in decoded data district 408.The address 418 of above-mentioned buffering start address 422 and request msg at a distance of (160 sections) greater than transmitting decoded data district 408 (130 sections), the expression request msg has been written into address 410 and has write other data, and main frame 112 can be judged to be the high-speed cache failure.Suppose that request msg is the 280th section, buffering start address 422 still is the 360th section, and the spacing of the address 418 (the 280th section) of buffering start address 422 (the 360th section) and request msg is less than transmitting decoded data district 408 (130 sections), the expression request msg is positioned at transmits decoded data district 408, and then main frame 112 can be judged to be the high-speed cache success.In addition, continuity the above embodiments, lift a preferred embodiment again, the known above-mentioned size of having transmitted decoded data district 408 is 130 sections, if the address 418 of request msg is the 231st section, calculate buffering start address 422 (the 360th section) and request msg address 418 (the 231st section) apart be 129 sections (360-231=129).Write lattice before the address 410 because this section is positioned at,, represent that then write activity carries out, so main frame 112 can be judged to be the high-speed cache failure if when writing mark and being set up; If when writing mark and not being set up, then expression does not have the action that writes data at present, and this moment, main frame 112 can be judged to be the high-speed cache success.In addition, enumerate another embodiment again, when being positioned at the critical section 420 of transmitting decoded data district 408, whether carry out no matter write the action of data as if request msg, main frame 112 directly is judged to be high-speed cache failure, the address 418 of reading request msg again from disc 102.At this, for prevent request msg for originally write data (being capped new data), so a critical section is set to avoid reading non-default request msg.
A kind of process flow diagram that improves the method for data transmission efficiency that Fig. 6 proposes for the present invention.When the address 418 (square 602) that main frame 112 indication chips 108 read request msg, whether the address 418 of then detecting request msg is greater than initially reading address 416 (square 604), if the address of request msg 418 is not greater than the address 416 of initially reading, the address 418 of then representing request msg is not dropped in the ring buffer zone 400, then be judged to be high-speed cache failure, main frame 112 must be again reads the address 418 of request msg and upgrades and initially read address 416 (square 606) from disc 102.If the address 418 of request msg is greater than initially reading address 416, judging then whether request msg is positioned at has transmitted decoded data district 408 (square 608) again, if request msg is not positioned at and has transmitted decoded data district 408, the expression request msg falls into does not transmit decoded data district 406, whether detecting host address 414 points to the address 418 (square 610) of request msg subsequently, if the address 418 of request msg is pointed in detecting host address 414, be the high-speed cache success, main frame 112 directly reads request msg (square 618) from host address 414.On the other hand, when not pointing to the address 418 (square 610) of request msg, must correct the address 418 (square 616) that host address 414 makes it to point to request msg, then read request msg (square 618) from host address 414 as if host address 414.In addition, if request msg is positioned at when transmitting decoded data district 408, still need and judge whether request msg is positioned at a critical section 420 (square 612), if request msg is not positioned at critical section 420, also must correct host address 414 and make it to point to the address 418 (square 616) of request msg, be the high-speed cache success, main frame 112 directly reads request msg (square 618) from host address 414.If request msg is positioned at critical section 420, then detects the action that writes data and whether stop (square 614).When not stopping (writing flag is set up) as if the action that writes data, then be judged to be the high-speed cache failure, main frame 112 must read the address 418 (square 606) of request msg again from disc 102.Stop (writing mark is not set up) if write the action of data, promptly correct the address 418 (square 616) that host address 414 makes it to point to request msg, then read request msg (square 618) from host address 414.
Please refer to Fig. 7, it is the process flow diagram of another embodiment of the present invention.When the address 418 (square 702) that main frame 112 indication chips 108 read request msg, whether the address 418 of then detecting request msg is greater than initially reading address 416 (square 704), if the address of request msg 418 is not greater than the address 416 of initially reading, the address 418 of then representing request msg is not dropped in the ring buffer zone 400, then be judged to be high-speed cache failure, main frame 112 must be again reads the address 418 of request msg and upgrades and initially read address 416 (square 706) from disc 102.If the address 418 of request msg is greater than initially reading address 416, judging then whether request msg is positioned at has transmitted decoded data district 408 (square 708) again, if request msg is not positioned at and has transmitted decoded data district 408, representing then that request msg falls into does not transmit decoded data district 406, whether detecting host address 414 points to the address 418 (square 710) of request msg subsequently, if the address 418 of request msg is pointed in detecting host address 414, be the high-speed cache success, main frame 112 directly reads request msg (square 718) from host address 414.On the other hand, when not pointing to the address 418 (square 710) of request msg, must correct the address 418 (square 716) that host address 414 makes it to point to request msg, then read request msg (square 718) from host address 414 as if host address 414.In addition, if request msg is positioned at when transmitting decoded data district 408, still need and judge whether request msg is positioned at a critical section 420 (square 712), if request msg is not positioned at critical section 420, also must correct host address 414 and make it to point to the address 418 (square 716) of request msg, be the high-speed cache success, main frame 112 directly reads request msg (square 718) from host address 414.If request msg is positioned at critical section 420, then be judged to be the high-speed cache failure, main frame 112 must read the address 418 (square 706) of request msg again from disc 102.
In sum, the invention provides a kind of method of improving data transmission efficiency that is applied in multimedia playing apparatus, it initially reads the address by setting one, when the address of request msg when initially reading the address, the decision request data are positioned at which section of ring buffer zone again, and make corresponding address translation, so can reduce the probability that main frame is returned the disc reading of data, to improve the efficient of transmission data; Playback quality is good on the other hand, allows picture that the beholder saw not have the phenomenon of pause.In addition, in an embodiment of the present invention, more set a critical section of having transmitted in the decoded data district, whether visual write activity carries out, and whether the clearer request msg that read of defining is request msg originally.
The present invention describes in detail as above at specific embodiment, haveing the knack of this operator can be under the condition of not violating spirit of the present invention and scope, to change of the present invention or change, these changes or change still do not depart from the scope of the present invention, and spirit of the present invention and scope will be defined in as described the claim.
Claims (6)
1. method of improving data transmission efficiency that is applied to multimedia playing apparatus, it comprises:
Read the address of a request msg;
Detect the address of this request msg and whether initially read the address greater than one;
When the address is initially read greater than this in the address of this request msg, judge then whether this request msg is positioned at one and has transmitted the decoded data district, when the address is initially read less than this in the address of this request msg, then read the address of this request msg again, and upgrade this and initially read the address of address for this request msg;
When this request msg is not positioned at this and has transmitted the decoded data district, then detect the address whether a host address points to this request msg, when this request msg is positioned at this and has transmitted the decoded data district, judge then whether this request msg is positioned at a critical section;
Point to the address of this request msg when detecting this host address, then judge the high-speed cache success, read this request msg from this host address; Otherwise correct this host address earlier, make it to point to the address of this request msg, judge the high-speed cache success again, read this request msg from this host address; And
When this request msg is positioned at this critical section, then be judged to be the high-speed cache failure, and the address of reading this request msg again, and upgrade this and initially read the address of address for this request msg, when this request msg is not positioned at this critical section, then correct this host address, make it to point to the address of this request msg, judge the high-speed cache success again, read this request msg from this host address
Wherein this initially to read the address be that first of sequential loop read loop buffer data reads the address.
2. the method for claim 1, judge wherein whether this request msg is positioned at one and has transmitted the step in decoded data district, more comprises:
Provide this to transmit the size in decoded data district;
The address of this request msg and the spacing of a buffering start address are provided; And
The spacing that deducts when this buffering start address behind the address of this request msg has been transmitted the decoded data district less than this, judges that this request msg is positioned at this and has transmitted the decoded data district.
3. method as claimed in claim 2 provides this size of having transmitted the decoded data district further to comprise:
Provide one not transmit the not size in decoded data district of decoded data district and; And
Measure the size of a storer and this and do not transmit not difference of decoded data district size of decoded data district and this, represent this to transmit the size in decoded data district to make this difference.
4. the method for claim 1 is positioned at this critical section that this has transmitted the decoded data district as if this request msg, more comprises:
Judge whether an action that writes data stops;
If stop, then correcting the address that this host address makes it to point to this request msg earlier, judge the high-speed cache success again and read this request msg from this host address; And
If do not stop, then being judged to be the high-speed cache failure, read the address of this request msg again and upgrade this and initially read the address of address for this request msg.
5. whether method as claimed in claim 4 more comprises setting one and writes mark, stop in order to judging this action that writes data.
6. the method for claim 1, wherein said multimedia playing apparatus is digitized video recorder or digitized video player.
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| CN101339799B (en) * | 2007-07-05 | 2011-09-28 | 深圳市华曦达科技股份有限公司 | Method and system for implementing media play |
| CN106294213B (en) * | 2016-08-02 | 2019-07-16 | 芯启源电子科技有限公司 | Storage device, electronic equipment and buffer management method |
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| JP2000076126A (en) * | 1998-09-03 | 2000-03-14 | Matsushita Electric Ind Co Ltd | Method for controlling read of image data to ring buffer and controller for controlling the read |
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