CN100394570C - Method of avoid fluorination of metal joint of semiconductor element - Google Patents
Method of avoid fluorination of metal joint of semiconductor element Download PDFInfo
- Publication number
- CN100394570C CN100394570C CNB021030855A CN02103085A CN100394570C CN 100394570 C CN100394570 C CN 100394570C CN B021030855 A CNB021030855 A CN B021030855A CN 02103085 A CN02103085 A CN 02103085A CN 100394570 C CN100394570 C CN 100394570C
- Authority
- CN
- China
- Prior art keywords
- layer
- metallic contact
- semiconductor element
- weld pad
- protective layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention discloses a method for avoiding fluorination of metal contact points of semiconductor elements. Firstly, a semiconductor substrate which is provided with a metal contact point is provided; then, a protective layer is formed and covered on the semiconductor substrate and the metal contact point; the protective layer is etched through by etching until partial surface of the metal contact point is exposed, a preset opening is formed in the protective layer, wherein an etching reaction layer is formed on the protective layer after the step of plasma body etching; a removal step is carried out to remove the etching reaction layer on the protective layer, and a metal contact point and a contact window without fluoride are formed. Therefore, the reaction of residual etching reactants and the metal contact point in subsequent processing steps is avoided. In addition, the present invention can also be applied to a manufacture process of forming dielectric layer holes or contact windows above metal layers relative to multiple inner layer structures of semiconductor elements.
Description
(1) technical field
The formation method of the metallic contact of the relevant a kind of semiconductor element of the present invention, and particularly relevant for a kind of method of avoiding fluoridizing the metallic contact of semiconductor element.
(2) background technology
When the size of electronic component is done littler and littler, various trials are just arranged always, attempt to dwindle the connection space that engages of integrated circuit (IC) wafer and printed circuit board (PCB).It is by being positioned at the weld pad (Bonding Pad) around the wafer that integrated circuit on the wafer is connected with circuit between the printed circuit board (PCB).Traditional welding pad structure generally includes a jointing metal layer (Bonding Metal Layer) and and is formed at barrier layer (Barrier Layer) on the dielectric layer, and this dielectric layer is generally a silicon dioxide layer.The jointing metal layer be with wafer in one or more semiconductor elements carry out circuit and be connected, the barrier layer that is positioned on the dielectric layer then helps adhesion (Adhere) jointing metal layer and dielectric layer, this jointing metal layer is generally an aluminium lamination.
Chip bonding pads is connected with lead frame (Lead Frame) with the lead (Lead) of printed circuit board (PCB), and this is leaded package technology.In this leaded package technology, wafer is to be fixed on the lead frame that is made of the lead of arranging, and with the lead of thin wire bonds connecting wafer weld pad and lead frame.Entire wafer and lead frame assembly are covered by in plastic cement or the macromolecular material, and the lead that extends by lead frame is fixed on the printed circuit board (PCB) then.Another kind of packaging technology, promptly Chip-on-Board technology is that wafer directly is fixed on the printed circuit board (PCB), itself and leaded package technology are compared, and have advantages such as the space of saving and weight reduction.It is to engage (Wire Bonding) mode by packaging conductive wire that integrated circuit on the wafer is connected with circuit between the printed circuit board (PCB), engages with the lead of printed circuit board (PCB) with the weld pad (Pad) of lead with wafer.The available many technology of the joint of lead (Bonding) are finished, and these technology comprise that ultrasonic wave engages (Ultrasonic Bonding) method and hot pressing (Thermocompression Bonding) method.The ultrasonic wave bonding method is with ultrasonic wave or vibrations lead to be engaged with weld pad.The temperature that the pressure sintering utilization raises engages lead with compression with weld pad.Both all directly apply machinery or/and heat energy on weld pad, so also cause the damage of weld pad and wafer.In addition, tradition forms in the technology of weld pad, and the method for etching dielectric layer is the plasma etch process with fluoride.Therefore; after plasma etch step is finished; can produce one deck fluorinated layer on protective layer; this will produce many defectives in causing the subsequent technique process; for example; hinder electrical joint the between integrated circuit component and the weld pad on the wafer, this causes the reduction and the minimizing in wafer life-span of reliability.In addition, for multiple internal layer (Multi-Inter Layers) structure of semiconductor element, in the interlayer hole above each metal level or the forming process of contact hole, also cause the phenomenon of fluoridizing of above-mentioned metallic contact.
In view of above-mentioned various reasons, we more need a kind of formation method of metallic contact of new semiconductor element.So that promote the productivity ratio and the acceptance rate of subsequent process steps.
(3) summary of the invention
The objective of the invention is is providing a kind of method of avoiding fluoridizing the metallic contact of semiconductor element, improving the acceptance rate and the productivity ratio of making effectively, thereby improve economically benefit and the usability on the industry.
For achieving the above object, the formation method of the weld pad of semiconductor element according to an aspect of the present invention is characterized in, comprises the following steps: to provide the semiconductor ground, has a metallic contact on it; Form one first protective layer on this semiconductor substrate and this metallic contact; Carry out an etching step with this first protective layer of eating thrown till the part surface that exposes this metallic contact, and form a prodefined opening eating thrown on the part surface of this metallic contact, wherein, after this etching step was finished, an etching reaction layer was formed on this first protective layer; And carry out one and remove step removing this etching reaction layer on this first protective layer, and conformal generation one second protective layer is on the surface of this metallic contact, and form this weld pad.
The formation method of the weld pad of semiconductor element according to a further aspect of the invention is characterized in, comprises the following steps: to provide the semiconductor ground; Form a metallic contact on this semiconductor substrate; Form and cover a passivation layer on this semiconductor substrate and this metallic contact; Form a polyimide on this passivation layer; Carry out a gold-tinted development step with this polyimide of eating thrown and form a prodefined opening in this polyimide; Carry out one first etching step and pass through this this passivation layer of prodefined opening eating thrown till the part surface that exposes this metallic contact, wherein, after this first etching step was finished, an etching reaction layer is conformal to be created on this polyimide, and residual polyalcohol is on total; Carry out one second etching step to remove polymer; And carry out one and remove step removing this etching reaction layer on this polyimide, and conformal generation one protective layer is on the surface of this metallic contact, and form this weld pad.
Avoid fluoridizing the method for the metallic contact of semiconductor element according to another aspect of the invention a kind of, be characterized in, comprise the following steps: to provide the semiconductor ground; Form a metallic contact on this semiconductor substrate; Form and cover a dielectric layer on this semiconductor substrate and this metallic contact; Conformal generation one aramid layer is on this dielectric layer; Carry out a gold-tinted development step with this polyimide of eating thrown and form one and be opened in this polyimide; Carrying out one has the plasma etch step of fluoride and passes through this this dielectric layer of opening eating thrown till the part surface that exposes this metallic contact, wherein, after this plasma etch step with fluoride is finished, the monofluoride layer is conformal to be created on this polyimide, and residual polyalcohol is on total; Carry out a wet etch step to remove polymer; And carry out one and have the cineration step of hybrid gas source of oxygen and nitrogen to remove this fluoride layer on this polyimide; and conformal generation one oxide protective layer is on the surface of this metallic contact; wherein; the mixing ratio of oxygen and nitrogen is about 100: 1900, and oxygen content is about 5% of total gas flow.
The formation method of the contact hole of a kind of semiconductor element according to a further aspect of the present invention, be characterized in, comprise the following steps: to provide the semiconductor ground, this semiconductor substrate has a metallic contact and a dielectric layer is covered on this semiconductor substrate and this metallic contact; Form a photoresist layer on this dielectric layer; With undertaken by this photoresist layer a plasma etch step with fluoride with this dielectric layer of eating thrown till the part surface that exposes this metallic contact; and form a contact hole in this dielectric layer; wherein; the oxygen content that this etching step adopted is approximately less than 10% of total gas flow; and after etching step is finished, form the monoxide protective layer on the surface of this contact hole.
Adopt such scheme, can effectively avoid residual etch reactants and metallic contact in subsequent process steps, to react.
For further specifying purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
(4) description of drawings
Figure 1A and Figure 1B are according in first preferred embodiment of the present invention, form the profile of the contact hole of semiconductor element;
Fig. 2 A to Fig. 2 D is according in second preferred embodiment of the present invention, forms the profile of the weld pad of semiconductor element;
Fig. 3 A to Fig. 3 D is according in the 3rd preferred embodiment of the present invention, by the profile of ashing processing procedure with the weld pad of formation semiconductor element; With
Shown in Figure 4 is the experimental data figure of the content of fluoride of content of fluoride of the present invention and conventional process.
(5) embodiment
The metallic contact processing procedure that the present invention is a kind of semiconductor element in this direction of inquiring into.In order to understand the present invention up hill and dale, detailed step or element will be proposed in following description.Apparently, execution of the present invention is not defined in the specific details that skill person had the knack of of semiconductor element.On the other hand, well-known processing step or element are not described in the details, with the restriction of avoiding causing the present invention unnecessary.Preferred embodiment of the present invention will be described in detail as follows; yet except these are described in detail; the present invention can also be implemented among other the embodiment widely, and scope of the present invention do not limited, and is as the criterion with the scope of patent protection that claims were limited.
Shown in Figure 1A and Figure 1B, in the first embodiment of the present invention, at first provide semiconductor ground 100, have a metallic contact 110 on the semiconductor substrate 100, be covered on semiconductor substrate 100 and the metallic contact 110 with a dielectric layer 120.Then, form a photoresist layer 130 in dielectric layer 120 tops, and carry out an etching step 140 by photoresist layer 130, for example, plasma etch step with fluoride till the part surface of exposing metal contact 110, and forms a contact hole (or interlayer hole) 150 in dielectric layer 120 with eating thrown dielectric layer 120, wherein, etching step 140 adopts a content approximately less than 10% oxygen of total gas flow at least.In addition, after etching step 140 is finished, form monoxide protective layer 160 on the surface of metallic contact 110.Afterwards, remove photoresist layer 130.Whereby, can avoid residual etch reactants in semiconductor structure.
Shown in figure 2A to Fig. 2 D, in the second embodiment of the present invention, at first provide semiconductor ground 200, have a metallic contact 210 on it, wherein, metallic contact 210 comprises an aluminium material.Then, form and cover one first protective layer 220 on semiconductor substrate 200 and metallic contact 210, wherein, first protective layer 220 comprises a pi (polyimide at least; PI) layer and a passivation layer (passivationlayer); for example; dielectric layer; subsequently; carry out an etching step 230 with eating thrown protective layer 220 till the part surface of exposing metal contact 210; and form a prodefined opening 240 in first protective layer 220; wherein; after etching step 230 is finished; conformal being created on first protective layer 220 of one etching reaction layer, 250 meeting, and etching step 230 comprises a plasma etching step at least, for example; plasma etch step with fluoride, and etching reaction layer 250 comprises the monofluoride layer at least.Afterwards; carry out one and remove step 260; for example; cineration step; so that remove etching reaction layer 250 on first protective layer 220, wherein, the gas source that removes step 260 comprises one oxygen/nitrogen mixture gas at least; and the mixing ratio of oxygen/nitrogen comprises that at least a ratio is about 100/1900, and oxygen content comprises that at least a content is about 5% of total gas flow.In addition, after removing step 260 and finishing, conformal generation one second protective layer 270, for example, oxide layer is on the surface of metallic contact 210.Whereby, can avoid residual etch reactants 250 in subsequent step, to react with metallic contact 210.
Shown in figure 3A to Fig. 3 E, in the third embodiment of the present invention, at first provide semiconductor ground 300.Then, form a metallic contact 310 on semiconductor substrate 300.Then, deposit and cover a dielectric layer 320 on semiconductor substrate 300 and metallic contact 310, wherein, the material of dielectric layer 320 comprises oxide or nitride at least.Then, conformal generation one pi (polyimide above dielectric layer 320; PI) layer 330, wherein, the formation method of pi (PI) layer 330 comprises a rubbing method at least.Subsequently, carry out a gold-tinted development step 340 with eating thrown pi (PI) layer 330 and form a prodefined opening 350.Secondly, by prodefined opening 350 carry out a plasma etch process 360 with eating thrown dielectric layer 320 till the part surface of exposing metal contact 310, wherein, after plasma etch step 360 is finished, one etching reaction layer 370 be formed on pi (PI) layer 330 and residual polyalcohol in total, in addition, plasma etching processing procedure 360 comprises that at least one has the plasma etching processing procedure of fluoride, and etching reaction layer 370 comprises the monofluoride layer at least.Afterwards, carry out a wet etch process 380 to remove the residual polyalcohol in the total.At last, carry out an ashing processing procedure 390 so that the etching reaction layer 370 on removal pi (PI) layer 330, and form a weld pad, wherein, cineration step 380 comprises an oxygen cineration step at least, its gas source comprises one oxygen/nitrogen mixture gas at least, and its mixing ratio comprises that at least a ratio is about 100/1900, and oxygen content is about 5% of total gas flow.In addition, after cineration step 390 was finished, conformal generation one oxide protective layer 395 was on the surface of metallic contact 310.Whereby, can avoid residual etch reactants and metallic contact in subsequent step, to react.
As mentioned above, in an embodiment of the present invention, the present invention can be fluoridized to avoid protective layer by a cineration step with oxygen.In addition, can remove content of fluoride on the protective layer in a large number by the present invention, to avoid residual fluoride metal fluoride contact in the subsequent technique process.With reference to shown in Figure 4, its disclosed significantly process of the present invention far below the traditional handicraft method residual content of fluoride.In view of the above, the present invention can improve the acceptance rate and the productivity ratio of making effectively.So, the present invention can meet economically benefit and the usability on the industry.Therefore, this method can be applicable in the technology of deep-sub-micrometer of semiconductor element.
Certainly, on the formation technology of the present invention except the metallic contact that may be used in semiconductor element, also may be used on the formation technology of the contact hole of any semiconductor element or interlayer hole.And the present invention to remove fluoride fully, does not develop the formation process aspect that is used in about metallic contact by cineration step so far yet.For the technology of deep-sub-micrometer, this method is the formation process of the metallic contact of a preferable feasible semiconductor element.
Certainly, those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (13)
1. the formation method of the weld pad of a semiconductor element is characterized in that, comprises the following steps:
The semiconductor ground is provided, has a metallic contact on it;
Form one first protective layer on this semiconductor substrate and this metallic contact;
Carry out an etching step with this first protective layer of eating thrown till the part surface that exposes this metallic contact, and form a prodefined opening eating thrown on the part surface of this metallic contact, wherein, after this etching step was finished, an etching reaction layer was formed on this first protective layer; And
Carry out one and remove step removing this etching reaction layer on this first protective layer, and conformal generation one second protective layer is on the surface of this metallic contact, and form this weld pad.
2. the formation method of the weld pad of semiconductor element as claimed in claim 1 is characterized in that, the material of described protective layer comprises a pi.
3. the formation method of the weld pad of semiconductor element as claimed in claim 1 is characterized in that, described etching step comprises that one has the plasma etch step of fluoride.
4. the formation method of the weld pad of semiconductor element as claimed in claim 1 is characterized in that, describedly removes the hybrid gas source that step adopts oxygen and nitrogen.
5. the formation method of the weld pad of semiconductor element as claimed in claim 4 is characterized in that, the ratio of the mixing ratio of the hybrid gas source of described oxygen and nitrogen is about 100/1900.
6. the formation method of the weld pad of semiconductor element as claimed in claim 4 is characterized in that, described oxygen content is about 5% of total gas flow.
7. the formation method of the weld pad of a semiconductor element is characterized in that, comprises the following steps:
The semiconductor ground is provided;
Form a metallic contact on this semiconductor substrate;
Form and cover a passivation layer on this semiconductor substrate and this metallic contact;
Form a polyimide on this passivation layer;
Carry out a gold-tinted development step with this polyimide of eating thrown and form a prodefined opening in this polyimide;
Carry out one first etching step and pass through this this passivation layer of prodefined opening eating thrown till the part surface that exposes this metallic contact, wherein, after this first etching step was finished, an etching reaction layer is conformal to be created on this polyimide, and residual polyalcohol is on total;
Carry out one second etching step to remove polymer; And
Carry out one and remove step removing this etching reaction layer on this polyimide, and conformal generation one protective layer is on the surface of this metallic contact, and form this weld pad.
8. the formation method of the weld pad of semiconductor element as claimed in claim 7 is characterized in that, described first etching step comprises that one has the plasma etch step of fluoride.
9. the formation method of the weld pad of semiconductor element as claimed in claim 7 is characterized in that, described second etching step comprises a wet etch step.
10. the formation method of the weld pad of semiconductor element as claimed in claim 7 is characterized in that, the described step that removes comprises a cineration step.
11. the formation method of the weld pad of semiconductor element as claimed in claim 10 is characterized in that described cineration step adopts the hybrid gas source of oxygen and nitrogen, and the mixing ratio of oxygen and nitrogen is about 100/1900.
12. the formation method of the weld pad of semiconductor element as claimed in claim 11 is characterized in that described oxygen content is about 5% of total gas flow.
13. a method of avoiding fluoridizing the metallic contact of semiconductor element is characterized in that, comprises the following steps:
The semiconductor ground is provided;
Form a metallic contact on this semiconductor substrate;
Form and cover a dielectric layer on this semiconductor substrate and this metallic contact;
Conformal generation one aramid layer is on this dielectric layer;
Carry out a gold-tinted development step with this polyimide of eating thrown and form one and be opened in this polyimide;
Carrying out one has the plasma etch step of fluoride and passes through this this dielectric layer of opening eating thrown till the part surface that exposes this metallic contact, wherein, after this plasma etch step with fluoride is finished, the monofluoride layer is conformal to be created on this polyimide, and residual polyalcohol is on total;
Carry out a wet etch step to remove polymer; And
Carry out one and have the cineration step of hybrid gas source of oxygen and nitrogen to remove this fluoride layer on this polyimide; and conformal generation one oxide protective layer is on the surface of this metallic contact; wherein; the mixing ratio of oxygen and nitrogen is about 100: 1900, and oxygen content is about 5% of total gas flow.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100033264A CN101217123A (en) | 2002-02-08 | 2002-02-08 | A method of fluorination protection on the metallic contact of semiconductor element |
| CNB021030855A CN100394570C (en) | 2002-02-08 | 2002-02-08 | Method of avoid fluorination of metal joint of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021030855A CN100394570C (en) | 2002-02-08 | 2002-02-08 | Method of avoid fluorination of metal joint of semiconductor element |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008100033264A Division CN101217123A (en) | 2002-02-08 | 2002-02-08 | A method of fluorination protection on the metallic contact of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1437237A CN1437237A (en) | 2003-08-20 |
| CN100394570C true CN100394570C (en) | 2008-06-11 |
Family
ID=27627738
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021030855A Expired - Fee Related CN100394570C (en) | 2002-02-08 | 2002-02-08 | Method of avoid fluorination of metal joint of semiconductor element |
| CNA2008100033264A Pending CN101217123A (en) | 2002-02-08 | 2002-02-08 | A method of fluorination protection on the metallic contact of semiconductor element |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008100033264A Pending CN101217123A (en) | 2002-02-08 | 2002-02-08 | A method of fluorination protection on the metallic contact of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN100394570C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298556A (en) * | 2015-05-19 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of a kind of chip pressure welding block and chip |
| CN114334642B (en) * | 2022-03-10 | 2022-06-17 | 绍兴中芯集成电路制造股份有限公司 | Film patterning method and preparation method of semiconductor device |
-
2002
- 2002-02-08 CN CNB021030855A patent/CN100394570C/en not_active Expired - Fee Related
- 2002-02-08 CN CNA2008100033264A patent/CN101217123A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN101217123A (en) | 2008-07-09 |
| CN1437237A (en) | 2003-08-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1332431C (en) | Method for producing semiconductor device, semiconductr device and electronic device | |
| KR101257274B1 (en) | Room temperature metal direct bonding | |
| CN100573854C (en) | Semiconductor device, circuit substrate and electronic equipment | |
| US6822336B2 (en) | Semiconductor device | |
| KR100499006B1 (en) | Manufacturing method for package substrate without electrolytic plating lead | |
| US20060189117A1 (en) | Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment | |
| US6593222B2 (en) | Method to improve the reliability of thermosonic gold to aluminum wire bonds | |
| JP2003243436A (en) | Bump forming method, bump attached semiconductor element and manufacturing method thereof, semiconductor device and manufacturing method thereof, substrate and electronic device | |
| US7192803B1 (en) | Method of making a semiconductor chip assembly with simultaneously formed interconnect and connection joint | |
| TW200305190A (en) | Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding | |
| JP2002319588A (en) | Bond pad of semiconductor element and its forming method | |
| CN100394570C (en) | Method of avoid fluorination of metal joint of semiconductor element | |
| CN100514590C (en) | Method and structure for preventing soldering pad stripping | |
| US6699780B1 (en) | Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching | |
| JP2023165032A (en) | Semiconductor device, method of manufacturing semiconductor device, and module | |
| TWI228785B (en) | Substrate, wiring board, substrate for semiconductor package, semiconductor device, semiconductor package and its manufacturing method | |
| TW201239987A (en) | Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer | |
| US6576560B1 (en) | Method for avoiding the fluorination of the metal contact of the semiconductor device | |
| US6908788B1 (en) | Method of connecting a conductive trace to a semiconductor chip using a metal base | |
| JP4599929B2 (en) | Method for manufacturing power semiconductor device | |
| TW200812027A (en) | Flip-chip attach structure and method | |
| US6984576B1 (en) | Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip | |
| TWI292214B (en) | Method for avoiding the fluorination of the metal contact | |
| US20020123228A1 (en) | Method to improve the reliability of gold to aluminum wire bonds with small pad openings | |
| US6949408B1 (en) | Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080611 Termination date: 20210208 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |