CN100392987C - 解码装置、网格处理器及方法 - Google Patents
解码装置、网格处理器及方法 Download PDFInfo
- Publication number
- CN100392987C CN100392987C CNB2004100330898A CN200410033089A CN100392987C CN 100392987 C CN100392987 C CN 100392987C CN B2004100330898 A CNB2004100330898 A CN B2004100330898A CN 200410033089 A CN200410033089 A CN 200410033089A CN 100392987 C CN100392987 C CN 100392987C
- Authority
- CN
- China
- Prior art keywords
- decoding
- data path
- turbo
- decoding device
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
- H03M13/6511—Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
Abstract
Description
Claims (22)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10310812A DE10310812B4 (de) | 2003-03-12 | 2003-03-12 | Dekodiervorrichtung, Trellis-Prozessor und Verfahren |
DE10310812.2 | 2003-03-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1531212A CN1531212A (zh) | 2004-09-22 |
CN100392987C true CN100392987C (zh) | 2008-06-04 |
Family
ID=33038729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100330898A Expired - Fee Related CN100392987C (zh) | 2003-03-12 | 2004-03-12 | 解码装置、网格处理器及方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7269777B2 (zh) |
CN (1) | CN100392987C (zh) |
DE (1) | DE10310812B4 (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2409134B (en) * | 2003-12-11 | 2005-11-09 | Motorola Inc | A decoder |
WO2005112273A1 (en) * | 2004-05-18 | 2005-11-24 | Koninklijke Philips Electronics N.V. | Turbo decoder input reordering |
US7502412B2 (en) * | 2004-05-20 | 2009-03-10 | Qisda Corporation | Adaptive channel estimation using decision feedback |
US8046662B2 (en) * | 2004-08-20 | 2011-10-25 | Broadcom Corporation | Method and system for decoding control data in GSM-based systems using inherent redundancy |
FR2883434B1 (fr) * | 2005-03-21 | 2007-04-20 | Commissariat Energie Atomique | Methode et dispositif de demodulation a deux niveaux. |
KR100706608B1 (ko) * | 2005-07-19 | 2007-04-13 | 한국전자통신연구원 | 이중 스트림 전송에 적합한 부호기 추정 방법 및 이를이용한 부호화 장치 |
US8065588B2 (en) * | 2007-01-17 | 2011-11-22 | Broadcom Corporation | Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave |
US8739009B1 (en) * | 2007-12-27 | 2014-05-27 | Marvell International Ltd. | Methods and apparatus for defect detection and correction via iterative decoding algorithms |
CN102158235B (zh) * | 2011-04-26 | 2016-11-23 | 中兴通讯股份有限公司 | turbo译码的方法及装置 |
US9048990B2 (en) | 2011-12-01 | 2015-06-02 | Broadcom Corporation | Power efficient paging channel decoding |
US8873420B2 (en) | 2011-12-01 | 2014-10-28 | Broadcom Corporation | Detecting extended acquisition indicators |
US20130142057A1 (en) * | 2011-12-01 | 2013-06-06 | Broadcom Corporation | Control Channel Acquisition |
RU2516624C1 (ru) * | 2012-12-10 | 2014-05-20 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Владимирский государственный университет имени Александра Григорьевича и Николая Григорьевича Столетовых" (ВлГУ) | Способ декодирования сверточных кодов |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5432804A (en) * | 1993-11-16 | 1995-07-11 | At&T Corp. | Digital processor and viterbi decoder having shared memory |
CN1183681A (zh) * | 1996-08-23 | 1998-06-03 | 大宇电子株式会社 | 韦特比解码器中的相加-比较-选择处理器 |
WO2002021699A2 (en) * | 2000-09-08 | 2002-03-14 | Avaz Networks | Programmable and multiplierless viterbi accelerator |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7031408B2 (en) * | 1997-12-10 | 2006-04-18 | Adtran Inc. | Mechanism for reducing recovery time after path loss in coded data communication system having sequential decoder |
US20020015401A1 (en) * | 2000-08-03 | 2002-02-07 | Ravi Subramanian | Flexible TDMA system architecture |
WO2002054601A1 (en) * | 2000-12-29 | 2002-07-11 | Morphics Technology, Inc. | Channel codec processor configurable for multiple wireless communications standards |
JP2003018047A (ja) * | 2001-07-02 | 2003-01-17 | Kawasaki Microelectronics Kk | Cdma受信装置及び誤り訂正符号のシンボル軟判定方法 |
EP1436930B1 (en) * | 2001-08-02 | 2008-03-26 | Infineon Technologies AG | Configurable terminal engine |
US7529559B2 (en) * | 2002-10-07 | 2009-05-05 | Panasonic Corporation | Communication apparatus and method for reconfiguring communication apparatus |
US7197686B2 (en) * | 2002-10-11 | 2007-03-27 | Nvidia Corporation | Reconfigurable bit-manipulation node |
-
2003
- 2003-03-12 DE DE10310812A patent/DE10310812B4/de not_active Expired - Fee Related
-
2004
- 2004-03-12 CN CNB2004100330898A patent/CN100392987C/zh not_active Expired - Fee Related
- 2004-03-12 US US10/799,099 patent/US7269777B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5432804A (en) * | 1993-11-16 | 1995-07-11 | At&T Corp. | Digital processor and viterbi decoder having shared memory |
CN1183681A (zh) * | 1996-08-23 | 1998-06-03 | 大宇电子株式会社 | 韦特比解码器中的相加-比较-选择处理器 |
WO2002021699A2 (en) * | 2000-09-08 | 2002-03-14 | Avaz Networks | Programmable and multiplierless viterbi accelerator |
Also Published As
Publication number | Publication date |
---|---|
US7269777B2 (en) | 2007-09-11 |
CN1531212A (zh) | 2004-09-22 |
DE10310812B4 (de) | 2007-11-22 |
DE10310812A1 (de) | 2004-10-28 |
US20040199858A1 (en) | 2004-10-07 |
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C14 | Grant of patent or utility model | ||
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Owner name: INFINEON TECHNOLOGY DELTA CO., LTD. Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG Effective date: 20111101 |
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Owner name: INFINEON TECHNOLOGIES AG Free format text: FORMER NAME: INFINRONG SCIENCE AND TECHNOLOGY CO., LTD. |
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Address after: Munich, Federal Republic of Germany Patentee after: Infineon Technologies AG Address before: Munich, Federal Republic of Germany Patentee before: INFINEON TECHNOLOGIES AG |
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Owner name: INTEL MOBILE COMMUNICATIONS LTD. Free format text: FORMER NAME: INTEL MOBILE COMMUNICATIONS TECHNOLOGY LTD. |
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Address after: Neubiberg, Germany Patentee after: Intel Mobile Communications GmbH Address before: Neubiberg, Germany Patentee before: Intel Mobile Communications GmbH |
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Effective date of registration: 20120615 Address after: Neubiberg, Germany Patentee after: Intel Mobile Communications GmbH Address before: Neubiberg, Germany Patentee before: Infineon Technologies AG |
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Address after: Neubiberg, Germany Patentee after: Intel Mobile Communications GmbH Address before: Neubiberg, Germany Patentee before: Intel Mobile Communications GmbH |
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