CN100386730C - Method for realizing site programmeable gate array loading - Google Patents
Method for realizing site programmeable gate array loading Download PDFInfo
- Publication number
- CN100386730C CN100386730C CNB2006100784245A CN200610078424A CN100386730C CN 100386730 C CN100386730 C CN 100386730C CN B2006100784245 A CNB2006100784245 A CN B2006100784245A CN 200610078424 A CN200610078424 A CN 200610078424A CN 100386730 C CN100386730 C CN 100386730C
- Authority
- CN
- China
- Prior art keywords
- value
- control register
- fpga
- loading control
- loading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The present invention discloses a method realizing field programmable gate array FPGA loading. The loading of FPGA is realized through a loading controlling register in a slow speed interface chip. The method comprises following steps: A. the value of the loading controlling register is read, and the read value is stored in a high speed storing device, B. the value in the high speed storing device carries out logical operation, an operated result is written in the loading controlling register to realize that the loaded data is latched in FPGA, and C. the present invention judges whether the loaded data is needed or not, if the loaded data is needed, the present invention goes to a step B, or the loading process for the FPGA is over. The method of the present invention can reduce visiting times for the slow speed interface chip, and the loading speed for the FPGA is enhanced.
Description
Technical field
The present invention relates to the programmable logic device (PLD) field, particularly a kind of realization field programmable gate array (Field Programmable Gate Array, the FPGA) method of Jia Zaiing.
Background technology
The appearance of FPGA device is the result of very large scale integration technology and Computer-aided Design Technology development.FPGA device integrated level height, volume are little, can realize special application function by user program.It allows circuit designers to utilize the computer based development platform, through design input, emulation, test and verification, up to the function that realizes expection.
Want the energy operate as normal after the FPGA device powers on, need be used for as the central processing unit (CPU) of the veneer of FPGA development platform the program that weaves being loaded into FPGA by serial mode, described loading procedure need be finished by the peripheral interface chip of CPU.Figure 1 shows that the hardware connection diagram that realization loads the FPGA program, wherein, (ErasableProgrammable Logic Device EPLD) 120 is the peripheral interface chip that is used to realize the FPGA loading to Erasable Programmable Logic Device.CPU 110 is provided with the level state of the corresponding control bit of the Loading Control register 121 in the EPLD 120 by local bus (Local Bus).Described control bit comprises data (DATA) line traffic control position and clock (CLK) line traffic control position.After FGPA 130 enters accepting state, at first EPLD 120 puts the data that will pass on data line, makes clock line become high level by low level then, at the rising edge of clock line, data on the FPGA 130 latch data lines, the data of such bit just transmit and finish; Clock line becomes low level by high level more subsequently, prepares to transmit the data of next bit.So repetitive operation can be sent on the FPGA 130 by EPLD 120 all need loaded data among the CPU 110, finishes the program loading procedure of FPGA.
Loading Control register 121 is generally an eight bit register, and described data line control bit and clock line control bit take wherein 1 respectively, remains 6 and may do other purposes.Therefore to data line or clock line set the time, can not change other everybody value in the Loading Control register 121.
At hardware configuration shown in Figure 1, the implementation procedure of existing FPGA loading procedure is: pointer variable of CPU definition is pointed to the Loading Control register among the EPLD, carry out logical operation by value to defined pointer variable, directly change the value of the corresponding control bit of Loading Control register, thereby realize the high-low level set of control data line and clock line, idiographic flow comprises the steps: as shown in Figure 2
Step 201: define a pointer variable and point to EPLD Loading Control register address;
Step 202: use this pointer variable to the value of EPLD Loading Control register carry out " with " logical operation, be 0 with clock line control position in the EPLD Loading Control register, all the other the position remain unchanged, thereby make clock line become low level; The implication of described AND-operation is: generate one 8 corresponding the counting immediately of the value with the Loading Control register, this clock line control bit of counting immediately is 0, and all the other positions are 1; Again these several immediately values with EPLD Loading Control register are carried out " with " logical operation.Other logical operation of the following stated similarly, so repeat no more.
Step 203: use this pointer variable that the value in the loading control is carried out " with or " logical operation, make that the data line control bit becomes the data that will transmit in the EPLD Loading Control register, all the other positions remain unchanged, thereby make data line be changed to the pairing level state of the data that will transmit;
Step 204: use this pointer variable to the value in the loading control carry out " or " logical operation, with clock line control position in the EPLD Loading Control register is 1, all the other positions remain unchanged, thereby make clock line become high level, at the rising edge of clock line, the data latching on the data line is in FPGA;
Step 205: need in addition to judge whether loaded data, if then go to step 202, otherwise finish loading procedure.
Wherein, step 202 is described to make clock line become low level by the operation pointer variable, though only need an instruction, the actual operating process of carrying out of this instruction is as follows:
Step 202a:CPU reads the value of Loading Control register clock line control bit and deposit in the arithmetic element of CPU inside from EPLD by local bus;
Step 202b:CPU carries out AND-operation the value of clock control position is changed to 0;
Step 202c:CPU deposits the value of the clock control position after resetting in the Loading Control register of EPLD in by local bus.
Shown in step 202a～202c, the Loading Control register that twice EPLD must be visited in a position of the Loading Control register of modification EPLD is once read, and once writes.In like manner, the Loading Control register that in Data Control position and the step 204 clock line is become twice EPLD of each needs visit of high level is set in the step 203; Like this, data need be visited 6 EPLD altogether to FPGA Loading Control register of transmission.And the bus frequency of the local bus of EPLD is generally 25MHz, and maximum is no more than 50MHz, and far below the clock frequency of CPU frequency and FPGA loading, frequent accessing EPLD will certainly greatly reduce loading speed in the loading procedure of FGPA.Therefore existing loading method shortcoming by the such low speed peripheral interface chip realization FPGA of EPLD is that efficient is low, and the load time is long, is not suitable for the occasion that requirement loads fast.
For improving the loading speed of FPGA, can adopt peripheral interface chip at a high speed to realize the loading of FPGA, but also not have ready-made being used to realize the high-speed peripheral interface chip that FPGA loads at present, and, use the high-speed peripheral interface chip can increase cost greatly.
Summary of the invention
In view of this, the objective of the invention is to, propose a kind of method that realizes that the FPGA program loads, can improve CPU and realize the speed that FPGA loads by existing low speed peripheral interface chip.This method comprises the steps:
A, read the value of Loading Control register and the value that is read is stored in the high speed memory devices;
B, the value in the described high speed memory devices is carried out logical operation, data line control bit in the described high speed memory devices is become want loaded data, data line is become want the level state of loaded data correspondence, and latching along the value in the high speed memory devices is write in the Loading Control register at described FPGA;
C, need in addition to judge whether loaded data, if then go to step B, otherwise finish loading procedure to FPGA.
Register variable of definition in described high speed memory devices, steps A is described to be stored as: the value that is read is stored in the defined register variable.
Described FPGA latchs at the rising edge of clock and wants loaded data, and then step B is described carries out logical operation to the value in the described high speed memory devices, and operation result is write the Loading Control register comprises:
B11, make the clock line control bit of the value in the described high speed memory devices become 0, the data line control bit becomes wants loaded data, more described value is write the Loading Control register by local bus;
B12, make the clock line control bit of the value in the described high speed memory devices become 1, more described value is write the Loading Control register by local bus.
Step B11 is described to be write the Loading Control register to described value by local bus and is: the value in the high speed memory devices is write in the Loading Control register, make the clock line of Loading Control register become low level, data line becomes the level state of wanting the loaded data correspondence, and all the other lines remain unchanged.
Step B12 is described to write the Loading Control register to described value by local bus, realization will loaded data be latched among the FPGA: the described value in the memory device is write in the Loading Control register, make clock line become high level, all the other lines remain unchanged, in the pairing value of level state of the rising edge FPGA of clock line latch data line.
Described FPGA latchs at the negative edge of clock and wants loaded data, and then step B is described carries out logical operation to the value in the described high speed memory devices, and operation result is write the Loading Control register comprises:
B21, make the clock line control bit of the value in the described high speed memory devices become 1, the data line control bit becomes wants loaded data, more described value is write the Loading Control register by local bus;
B22, make the clock line control bit of the value in the described high speed memory devices become 0, more described value is write the Loading Control register by local bus.
Step B21 is described to be write the Loading Control register to described value by local bus and is: the value in the high speed memory devices is write in the Loading Control register, make the clock line of Loading Control register become high level, data line becomes the level state of wanting the loaded data correspondence, and all the other lines remain unchanged.
Step B22 is described to write the Loading Control register to described value by local bus, realization will loaded data be latched among the FPGA: the described value in the memory device is write in the Loading Control register, make clock line become low level, all the other lines remain unchanged, in the pairing value of level state of the negative edge FPGA of clock line latch data line.
Described high speed memory devices is following any one: but the device with memory function of the internal memory of the register of the central processor CPU of veneer, veneer or described CPU high speed access.
Described low-speed interface chip is Erasable Programmable Logic Device EPLD.
From above scheme as can be seen, value with the Loading Control register when initialization reads in the high speed memory devices, thereafter the arithmetic operation of loading procedure all is that high speed memory devices is operated, only need operation result is write in the Loading Control register, and the negative edge at clock line is put data line simultaneously, so just reduced access times, improved loading speed FPGA to low speed peripheral interface chip.
Description of drawings
The hardware structure diagram of Fig. 1 for realizing that FPGA loads;
The process flow diagram that Fig. 2 loads for existing techniques in realizing FPGA;
Fig. 3 realizes the process flow diagram that FPGA loads for the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is further elaborated below in conjunction with accompanying drawing.
Core content of the present invention is: define a register object, read the value in the EPLD Loading Control register earlier and be stored in this object; In loading procedure, the value of described register object is carried out logical operation, then operation result is write in the EPLD Loading Control register by local bus, data of every like this loading are reduced to twice the access times of EPLD Loading Control register; In addition, according to the concrete regulation of chip, FPGA is rising edge or the negative edge latch data at clock line, so negative edge or rising edge at clock line can be provided with data line simultaneously, prepare the next data of transmission, can further save like this and load the required time raising loading velocity.Below in order to narrate conveniently, the clock edge of FPGA latch data is called latchs the edge, another one clock edge is called the unlatching edge.
Described register object can be arranged in the device with memory function that the CPU of the internal memory of register, development platform of the CPU self of development platform or other development platforms can high speed access; Described high speed is for the low speed local bus of EPLD, in general, as long as CPU is more than 5 times of local bus to described access speed with device of memory function, just can reach the effect of obvious raising loading speed.
The realization flow of the inventive method embodiment as shown in Figure 3, wherein latching along for the rising edge of clock of FPGA specifically comprises the steps:
Step 301: define a pointer variable and point to EPLD Loading Control register address, and define a register object;
Step 302:, the value of Loading Control register is read in the defined register object by local bus by the pointer variable of described sensing EPLD Loading Control register address;
Step 303: the value to the register object carry out " with " logical operation, make the clock line control bit of the value of register object be set to 0, all the other the position remain unchanged;
Step 304: the value to the register object is carried out " with or " logical operation, makes the data of data line control bit for transmitting of the value of register object, and all the other positions remain unchanged;
Step 305: the value of register object is write EPLD Loading Control register by local bus, thereby make the clock line of Loading Control register become low level, and data line is changed to the level state of the data correspondence that will transmit;
Step 306: the value to the register object carry out " or " logical operation, make the clock line control bit of the value of register object be set to 1, all the other the position remain unchanged; Again the value of register object is write EPLD Loading Control register by local bus, thereby make the clock line of Loading Control register become high level;
Step 307: judge whether to want in addition loaded data, if go to step 303; Otherwise end loading procedure.
If FPGA latchs along being the negative edge of clock, then in above-mentioned flow process, 0 and 1 of clock line control bit exchanges, and the high level of clock line and low level are exchanged can obtain corresponding flow process, so repeat no more.
From above flow process as can be seen, read the value of an EPLD Loading Control register when initialization, computing thereafter all is to operate in CPU; Only need in the loading procedure operation result is write in the Loading Control register of EPLD, load data to FPGA like this and only need visit twice local bus; And at the clock line negative edge, promptly the unlatching edge is provided with the level state of data line, thereby realizes revising simultaneously the clock bit and the data of Loading Control register, reduces the access times to local bus, can further improve loading velocity.
The described low speed peripheral interface of above embodiment chip is EPLD, in fact also can be the interface chip of other kinds, as long as comprise at least one register in this interface chip, and by changing the value of this register specific bit, can change the height of the corresponding pin level of chip, and these pins can be connected on the corresponding pin of FPGA, satisfy the low speed peripheral interface chip of above-mentioned requirements and all can use the inventive method, and described register can be used as the Loading Control register, and the inventive method is not made qualification to low speed peripheral interface chip and loading control.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a method that realizes that on-site programmable gate array FPGA loads loads by the Loading Control register pair FPGA in the low-speed interface chip, it is characterized in that this method comprises the steps:
A, read the value of Loading Control register and the value that is read is stored in the high speed memory devices;
B, the value in the described high speed memory devices is carried out logical operation, data line control bit in the described high speed memory devices is become want loaded data, data line is become want the level state of loaded data correspondence, and latching along the value in the high speed memory devices is write in the Loading Control register at described FPGA;
C, need in addition to judge whether loaded data, if then go to step B, otherwise finish loading procedure to FPGA.
2. method according to claim 1 is characterized in that, register variable of definition in described high speed memory devices, and steps A is described to be stored as: the value that is read is stored in the defined register variable.
3. method according to claim 1 is characterized in that, described FPGA latchs at the rising edge of clock and wants loaded data, and then step B comprises:
B11, make the clock line control bit of the value in the described high speed memory devices become 0, the data line control bit becomes wants loaded data, more described value is write the Loading Control register by local bus;
B12, make the clock line control bit of the value in the described high speed memory devices become 1, more described value is write the Loading Control register by local bus.
4. method according to claim 3, it is characterized in that, step B11 is described to be write the Loading Control register to described value by local bus and is: the value in the high speed memory devices is write in the Loading Control register, make the clock line of Loading Control register become low level, data line becomes the level state of wanting the loaded data correspondence, and all the other lines remain unchanged.
5. method according to claim 3, it is characterized in that, step B12 is described to write the Loading Control register to described value by local bus, realization will loaded data be latched among the FPGA: the described value in the memory device is write in the Loading Control register, make clock line become high level, all the other lines remain unchanged, in the pairing value of level state of the rising edge FPGA of clock line latch data line.
6. method according to claim 1 is characterized in that, described FPGA latchs at the negative edge of clock and wants loaded data, and then step B comprises:
B21, make the clock line control bit of the value in the described high speed memory devices become 1, the data line control bit becomes wants loaded data, more described value is write the Loading Control register by local bus;
B22, make the clock line control bit of the value in the described high speed memory devices become 0, more described value is write the Loading Control register by local bus.
7. method according to claim 6, it is characterized in that, step B21 is described to be write the Loading Control register to described value by local bus and is: the value in the high speed memory devices is write in the Loading Control register, make the clock line of Loading Control register become high level, data line becomes the level state of wanting the loaded data correspondence, and all the other lines remain unchanged.
8. method according to claim 6, it is characterized in that, step B22 is described to write the Loading Control register to described value, realization will loaded data be latched among the FPGA: the described value in the memory device is write in the Loading Control register, make clock line become low level, all the other lines remain unchanged, in the pairing value of level state of the negative edge FPGA of clock line latch data line.
9. according to each described method of claim 1 to 8, it is characterized in that described high speed memory devices is following any one: but the device with memory function of the internal memory of the register of the central processor CPU of veneer, veneer or described CPU high speed access.
10. according to each described method of claim 1 to 8, it is characterized in that described low-speed interface chip is Erasable Programmable Logic Device EPLD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100784245A CN100386730C (en) | 2006-05-26 | 2006-05-26 | Method for realizing site programmeable gate array loading |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100784245A CN100386730C (en) | 2006-05-26 | 2006-05-26 | Method for realizing site programmeable gate array loading |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1851647A CN1851647A (en) | 2006-10-25 |
| CN100386730C true CN100386730C (en) | 2008-05-07 |
Family
ID=37133126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100784245A Active CN100386730C (en) | 2006-05-26 | 2006-05-26 | Method for realizing site programmeable gate array loading |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100386730C (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1397891A (en) * | 2002-08-30 | 2003-02-19 | 清华大学 | In-line upgrade system for in-situ programmable gate array program and its implementation method |
| US6631520B1 (en) * | 1999-05-14 | 2003-10-07 | Xilinx, Inc. | Method and apparatus for changing execution code for a microcontroller on an FPGA interface device |
| CN1464421A (en) * | 2002-06-28 | 2003-12-31 | 华为技术有限公司 | Online loading process for on site programmable gate array |
| CN1499340A (en) * | 2002-11-08 | 2004-05-26 | 深圳市中兴通讯股份有限公司 | Loading method for ensuring to load programmable part reliably |
| CN1632767A (en) * | 2003-12-23 | 2005-06-29 | 华为技术有限公司 | System and method for loading on-site programmable gate array |
-
2006
- 2006-05-26 CN CNB2006100784245A patent/CN100386730C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6631520B1 (en) * | 1999-05-14 | 2003-10-07 | Xilinx, Inc. | Method and apparatus for changing execution code for a microcontroller on an FPGA interface device |
| CN1464421A (en) * | 2002-06-28 | 2003-12-31 | 华为技术有限公司 | Online loading process for on site programmable gate array |
| CN1397891A (en) * | 2002-08-30 | 2003-02-19 | 清华大学 | In-line upgrade system for in-situ programmable gate array program and its implementation method |
| CN1499340A (en) * | 2002-11-08 | 2004-05-26 | 深圳市中兴通讯股份有限公司 | Loading method for ensuring to load programmable part reliably |
| CN1632767A (en) * | 2003-12-23 | 2005-06-29 | 华为技术有限公司 | System and method for loading on-site programmable gate array |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1851647A (en) | 2006-10-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7769577B2 (en) | Hardware accelerator with a single partition for latches and combinational logic | |
| USRE44479E1 (en) | Method and mechanism for implementing electronic designs having power information specifications background | |
| US7257799B2 (en) | Flexible design for memory use in integrated circuits | |
| CN105468568B (en) | Efficient coarseness restructurable computing system | |
| Coates et al. | The Post Office experience: Designing a large asynchronous chip | |
| US9058860B2 (en) | Methods and apparatus for synthesizing multi-port memory circuits | |
| JPH0773066A (en) | Method and apparatus for constitution of memory circuit | |
| EP3223430B1 (en) | Systems and methods for configuring an sopc without a need to use an external memory | |
| US8397190B2 (en) | Method for manipulating and repartitioning a hierarchical integrated circuit design | |
| US6943605B2 (en) | Scan cell designs for a double-edge-triggered flip-flop | |
| US7624209B1 (en) | Method of and circuit for enabling variable latency data transfers | |
| US7958476B1 (en) | Method for multi-cycle path and false path clock gating | |
| US7496869B1 (en) | Method and apparatus for implementing a program language description of a circuit design for an integrated circuit | |
| Peeters et al. | Synchronous handshake circuits | |
| US7131099B2 (en) | Method, apparatus, and computer program product for RTL power sequencing simulation of voltage islands | |
| JP2000315223A (en) | Design database and design method of integrated circuit device | |
| CN100386730C (en) | Method for realizing site programmeable gate array loading | |
| Quinton et al. | Post-silicon debug using programmable logic cores | |
| US7260804B1 (en) | Method for circuit block routing based on switching activity | |
| CN116009647A (en) | Chip for reducing power consumption on clock tree and clock control method | |
| KR100453821B1 (en) | Data bus system for micro controller | |
| US7360193B1 (en) | Method for circuit block placement and circuit block arrangement based on switching activity | |
| US7437635B1 (en) | Testing hard-wired IP interface signals using a soft scan chain | |
| CN101236576B (en) | Interconnecting model suitable for heterogeneous reconfigurable processor | |
| Muralitharan | TinyParrot: An Integration-Optimized Linux-Capable Host Multicore |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: Xinhua three Technology Co., Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: Huasan Communication Technology Co., Ltd. |