CN100385391C - Hardware implementing method for embedded real-time precise abnormal mechanism - Google Patents

Abstract

The present invention discloses a hardware implementing method for an embedded real-time precise abnormal mechanism, which comprises the following steps: a distributed structure is adopted, and an instruction extracting stage, a decoding stage, an execution stage, a memory access stage and a write-back stage are all provided with abnormal checking logic for checking the abnormal type generated in the pipeline stage in the current clock cycle; the checked highest abnormal relative information generated by the pipeline stage in the current clock cycle is transferred to centralized abnormal arbitration logic, and a mirror register is added in each architectural register of a pipeline of an embedded processor; when the response of the processor is abnormal, the architectural resisters are stored in the mirror registers corresponding to the architectural registers; when the response of the processor returns abnormally, the values of the mirror registers are recovered in the corresponding architectural registers, and the processor is switched to a normal program process after completing an abnormal response once. As a distributed abnormal processing method based on the mirror registers is adopted, the speed of the real-time processing of the embedded processor is increased.

Description

The hardware implementation method of embedded real-time precise abnormal mechanism

Technical field

The present invention relates to a kind of hardware implementation method of embedded real-time precise abnormal mechanism.

Background technology

In embedded pipeline processor design, the realization of real-time precise abnormal mechanism is very crucial to the influence of processor performance.In the processor course of work, response abnormality means the change of processor instruction execution flow process and processor state.For the Embedded Real-Time processor, rapid saving processor standing state and enter the embodiment that exception handling procedure is exactly its real-time how.As shown in table 1, for pipeline processor, all might take place unusually in each level of streamline, and in the same clock period, have a plurality of pipelining-stages and produce unusual.Therefore the efficient of precise abnormal realization mechanism directly influences the performance of flush bonding processor.

Table 1 streamline is at different levels contingent unusual

Pipelining-stage	Exception Type
		Get and refer to level	External interrupt, instruction storage is unusual
Decode stage	External interrupt, illegal instruction exceptions, floating-point exception etc.
		Execution level	External interrupt, arithmetical operation is unusual, and trap is unusual etc.
The memory access level	External interrupt, alignment is unusual, and data storage is unusual
		Write back level	Outside unusual etc.

With reference to Fig. 4, document " PowerPC750 RISC Microprocessor User ' s manual (www.ibm.com) " has been introduced the precise abnormal realization mechanism of the PowerPC750 processor of IBM Corporation.This processor is made up of hardware and software two parts unusual complete processing once.When the processor response abnormality, at first hardware is preserved the program counter register and the machine status register(MSR) of current processor, begins the execute exception service subprogram according to Exception Type then.In the middle of the execute exception service subprogram, at first preserve whole states of current processor by software, comprise 32 general-purpose registers, some specified registers etc.After preservation finishes, carry out the core of interrupt service subroutine.After the core was finished, whole states of the processor of having been preserved by software rejuvenation switched to normal program circuit.Clearly, the state that software is preserved and recovery is handled is realized by carrying out access instruction.But because the difference of intrinsic response speed between current processor and the storer, the efficient that processor is carried out access instruction is very low.For the processor of PowerPC architecture, show by benchmark, when hitting Cache, on average need 10-20 clock period when carrying out an access instruction.If when not hitting cache, on average need 30-40 clock period.Adopt software that the scene of processor is preserved and when recovering,, when carrying out access instruction, can not hit Cache because change has taken place program circuit.Need a cost hundreds of clock period in order between normal state and anomalous mode, to switch.Therefore adopt the method for software to preserve processor state and can reduce processor, be unfavorable for the application of processor in real-time system unusual response speed.

Summary of the invention

In order to overcome the prior art processor deficiency low to unusual response speed, the invention provides a kind of hardware implementation method of embedded real-time precise abnormal mechanism, improved processor to unusual response speed.

The technical solution adopted for the present invention to solve the technical problems is: a kind of hardware implementation method of embedded real-time precise abnormal mechanism, it is characterized in that, and comprise the steps:

1) adopts distributed frame, refer to level, decode stage, execution level, memory access level and write back level an abnormal logic detection all is set getting of flush bonding processor streamline, detect and get finger level, decode stage, execution level, memory access level described in the present clock period and write back the Exception Type that level produces, and the highest unusual relevant information of priority of getting finger level, decode stage, execution level, memory access level and writing back the level generation to detected this cycle of centralized exception arbitration logical delivery;

2) each architecture register to the flush bonding processor streamline increases a mirror registers;

3) during the processor response abnormality, the value of architecture register is saved in the mirror registers corresponding with it, loads exception vector, the execute exception service subprogram;

4) when from described unusual service subprogram, returning, the value of mirror registers is returned in the architecture register corresponding with it, processor is finished an exception response, switches to normal program circuit.

The invention has the beneficial effects as follows that the distributed abnormality eliminating method owing to having adopted based on mirror registers behind the flush bonding processor response abnormality, can switch to the exception handler state from normal handling device state in a clock period.After abnormality processing is finished, can be in a clock period from the abnormality processing recovering state to normal condition.Compare with prior art " between normal state and anomalous mode, switch and need a cost hundreds of clock period ", improved the speed of flush bonding processor aspect processing in real time greatly.

The present invention is further described below in conjunction with drawings and Examples.

Description of drawings

Fig. 1 is the hardware implementation method process flow diagram of embedded real-time precise abnormal mechanism of the present invention

Fig. 2 is a distributed frame synoptic diagram in the hardware implementation method of embedded real-time precise abnormal mechanism of the present invention

Fig. 3 is a mirror registers structural representation in the hardware implementation method of embedded real-time precise abnormal mechanism of the present invention

Fig. 4 is the precise abnormal implementation method process flow diagram of document PowerPC750 processor in the background technology

Embodiment

With reference to Fig. 1～3, the streamline of flush bonding processor is divided into 5 grades, is respectively to get to refer to level decode stage, execution level, memory access level and write back level.Adopt distributed frame, an abnormal logic detection all is set in each level of streamline.This logic be responsible for detecting this grade all Exception Types that can judge, the centralized exception arbitration logic of co-current flow waterline reports the detected priority of this grade present clock period the highest Exception Type.Centralized exception arbitration logic is unusual at different pipelining-stage reports, priority according to the exception response of architectural definition is carried out centralized arbitration, judge the highest unusual of the priority of present clock period inner treater response, this structure is assigned to each flowing water section of streamline with abnormal logic detection, realizes the fast detecting to a unusual clock period.

In the pipeline processor design, each architecture register has been increased a mirror registers, when the processor response abnormality, hardware is saved in architecture register in the mirror registers corresponding with it like this.When returning unusually, hardware returns to the value of mirror registers in the architecture register corresponding with it.

Behind the processor response abnormality, the processor scene was saved in architecture register in its corresponding mirror registers a clock period.Interrupt service subroutine includes only the real kernel program relevant with Interrupt Process.When returning unusually, hardware returned to data in the architecture register in a clock period from mirror registers, and abnormality processing is finished.Distributed abnormality detection structure has been accelerated unusual response speed simultaneously.

This implementation method is compared with existing method, has avoided preserving the memory access time-delay that the processor scene is produced by the method for software.Unusual service subprogram includes only and is somebody's turn to do unusual relevant kernel program.Processor is responsible for preserving and recovering by hardware because of caused on-the-spot the switching fully of exception response.This method can be finished the switching at processor scene in a clock period, with processor processing when unusual because the on-the-spot performance loss that switching caused has dropped to minimumly, accelerated flush bonding processor to unusual real-time response ability.

The present invention has finished the exception response mechanism of this processor in the flush bonding processor " dragon rises R2 " that our design is finished.This flush bonding processor operation Vxworks operating system, unusual and personal computer carries out data interaction by serial ports.By the test of Vxworks operating system, adopt the exception handling of this method design to compare with exception handling based on software, the abnormality processing performance of processor has improved 10 times.

Claims (1)

1. the hardware implementation method of an embedded real-time precise abnormal mechanism is characterized in that, comprises the steps:

1) adopts distributed frame, refer to level, decode stage, execution level, memory access level and write back level an abnormal logic detection all is set getting of flush bonding processor streamline, detect and get finger level, decode stage, execution level, memory access level described in the present clock period and write back the Exception Type that level produces, and the highest unusual relevant information of priority of getting finger level, decode stage, execution level, memory access level and writing back the level generation to detected this cycle of centralized exception arbitration logical delivery;

2) each architecture register to the flush bonding processor streamline increases a mirror registers;

3) during the processor response abnormality, the value of architecture register is saved in the mirror registers corresponding with it, loads exception vector, the execute exception service subprogram;

4) when from described unusual service subprogram, returning, the value of mirror registers is returned in the architecture register corresponding with it, processor is finished an exception response, switches to normal program circuit.

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