CN100383928C

CN100383928C - Polycrystalline silicon etching process capable of removing residual gas

Info

Publication number: CN100383928C
Application number: CNB200510126340XA
Authority: CN
Inventors: 唐果
Original assignee: Beijing North Microelectronics Co Ltd
Current assignee: Beijing North Microelectronics Co Ltd
Priority date: 2005-12-07
Filing date: 2005-12-07
Publication date: 2008-04-23
Anticipated expiration: 2025-12-07
Also published as: CN1851871A

Abstract

The present invention provides a polysilicon etching technology capable of removing influence of remnant gas, which comprises a stabilizing step 1, a BT step, a stabilizing step 2, a main etching step, a stabilizing step 3, an over etching step and a dry process cleaning step. Process gas used by each stabilizing step can be process gas used by the processing step which is about to start and can also be N2 or any other one noble gas, such as He and Ar. An etching sectional plane micrograph obtained by using the polycrystalline silicon etching process of the present invention displays that the depression and a ladder structure of the juncture of a hard film protective layer and a polycrystalline silicon layer completely disappear, and the micro channel effect does not happen.

Description

A kind of polycrystalline silicon etching process that can eliminate residual gas

Technical field

The present invention relates to a kind of polycrystalline silicon etching process, specifically, relate to a kind of polycrystalline silicon etching process that can eliminate residual gas.

Background technology

In deep-submicron polysilicon dry etch process, the formation of a complete grid structure generally need successively through mask really up to the mark opens, remove photoresist, natural silicon dioxide layer is opened (BT), polysilicon main etching (ME), over etching (OE), etching technics finish after dry method cleaning several processing steps such as (dry clean).Nature silicon dioxide layer open stage mainly is to remove the natural silicon dioxide layer of polysilicon surface, so that the etching agent of main etching can carry out effective etching to polysilicon; The main etching stage adopts the endpoint monitoring mode to switch to selection than higher over etching step, the steep property of and outline less with the loss of guaranteeing gate oxide.In order to reach different technology purposes, the employed process gas of this several steps has nothing in common with each other.

Existing polycrystalline silicon etching process is not done other processing in the processing step handoff procedure, directly carry out next step technology, the profile of the lines that obtain after the etching can present serious trapezoidal situation, and significantly " neck " (recess) shape appearred in the intersection of hard mask layer and polysilicon layer, and little channel effect has taken place.By analysis, the formation of bad outline, relevant with the residual gas of previous processing step.To of great impact to the over etching stage of the etching of polysilicon and the etching gas in ME stage, simultaneously, the residual gas that each dry method is cleaned all may cause process results and have a strong impact on as the etching gas in BT stage.So, still need existing technology is improved to eliminate the residual gas influence, improve the quality of polycrystalline silicon etching process.

Summary of the invention

(1) technical problem that will solve

Purpose of the present invention aims to provide a kind of polycrystalline silicon etching process, make its can removal process switch in the influence of residual gas, improve the quality of polycrystalline silicon etching process.

(2) technical scheme

In order to reduce the influence of lines depth-width ratio (aspect ratio) to the etching section, in general the hard mask unlatching and the step of removing photoresist are opened to the elimination that etching technics end back dry method is cleaned residual gas influence between this several steps with a few step process separate processes in back so the present invention only inquires into from natural silicon dioxide layer.

Polycrystalline silicon etching process provided by the invention may further comprise the steps: stabilizing step 1, run through etching (BT) step, stabilizing step 2, main etching step, stabilizing step 3, over etching step and dry method and clean the step.

The process conditions of wherein said stabilizing step 1 are: chamber pressure 0-10mT, and gases used consistent with flow with running through etching (BT) step gaseous species.

The process conditions of wherein said stabilizing step 2 are: chamber pressure 0-15mT, and gases used consistent with flow with main etching step gaseous species.

The process conditions of wherein said stabilizing step 3 are: chamber pressure 0-60mT, and gases used consistent with flow with over etching step gaseous species.

More than in each stabilizing step up and down the power of utmost point electrode be 0w, the time is 5-10s.

The 0mT pressure edge value that is wherein adopted is a set point, i.e. the equipment reality max vacuum limit that can reach.

The employed process gas of each stabilizing step of technology provided by the invention can be the used process gas of processing step that is about to begin, and can also be N ₂Perhaps other any inert gases such as He, Ar, or their mist (proportioning is any) adopt the flow of 150-300sccm, and set molecular pump pendulum valve standard-sized sheet (be about to equipment pressure and be set at 0mT).Stabilizing step is equal to the residual gas purge step of a processing step fully like this, above-mentioned gas can both purge the gas and the accessory substance of a last processing step remaining in clean gas path pipe and the reative cell, reduce the influence of residual gas, also play the effect of stopping reaction chamber pressure in advance on the other hand, helped the stability of plasma glow start and course of reaction.

In addition, to clean the process conditions that the step relates to identical with the prior art processes condition for run through etching (BT) step, main etching step, over etching step and the dry method described in the technology of the present invention, that is,

Run through etching (BT) step middle chamber pressure 5-10mT, upper electrode power 250-400W, lower electrode power 40-80W, process gas are CF ₄, its flow is 30-80sccm, perhaps C ₂F ₂, its flow is 50-120sccm, the time is 5-7s;

Main etching step middle chamber pressure 8-15mT, upper electrode power 250-400W, lower electrode power 40-80W, process gas are Cl ₂0-50sccm, HBr 100-200sccm and He/O ₂(the two volume ratio is 7: 3, down together) is the mist of 5-15sccm, utilizes the end point determination instrument to control the end of this step;

Over etching step middle chamber pressure 40-80mT, upper electrode power 250-400W, lower electrode power 30-80W, process gas are Cl ₂0-30sccm, HBr 150-250sccm, He/O ₂Be the mist of 10-20sccm and He 0-200sccm, the time is 40-60s;

Dry method is cleaned step middle chamber pressure 8-20mT, upper electrode power 350-900W, and lower electrode power 0W, process gas are Cl ₂0-50sccm, SF ₆80-200sccm, O ₂The mist of 10-50sccm, the time is 10s.

(3) beneficial effect

Adopt the resulting etching section of polycrystalline silicon etching process of the present invention micrograph to show that the intersection recess of hard mask layer and polysilicon layer and trapezium structure complete obiteration do not have little channel effect yet.And technology is simple, need not the hardware system of equipment is optimized design, and different shape, types of devices are all had good adaptability.

Description of drawings

Fig. 1 is a stack architecture schematic diagram before and after hard mask is opened;

Wherein 1. being photoresist layer (lines form), 2. is hard mask layer, 3. is polysilicon layer, 4. is silicon dioxide layer, 5. is silicon substrate.

Fig. 2 is a stack architecture after the etching;

Fig. 3 and 4 is silicon chip lines profile after the existing technology etching;

Fig. 5-10 is silicon chip lines profile after the technology etching of the present invention;

Wherein Fig. 3-10 optical viewer is the HitachiS-4700 field emission scanning electron microscope, and multiplication factor is 150,000 times.

Embodiment

Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiment only to be used to the present invention is described and be not used in and limit the scope of the invention.

Embodiment 1

Technology (etching) equipment: ICP plasma dry etching machine

Scope is the HitachiS-4700 field emission scanning electron microscope.

Processing step:

Run through etching: pressure 7mt, last radio frequency source power 300w, following radio-frequency power 80w, etching gas CF ₄50sccm, etch period 5s.

Main etching: pressure 10mt, last radio frequency source power 300w, following radio-frequency power 40w, etching gas Cl ₂Be 30sccm, HBr 170sccm, He/O ₂The mist of 10sccm (the two volume ratio is 7: 3, and is together following), etch period is 6s.

Over etching: pressure 60mt, last radio frequency source power 300w, following radio-frequency power 40w, etching gas are HBr 200sccm, He 140sccm, He/O ₂The mist of 15sccm, etch period are 60s.

Dry method is cleaned: step 1: pressure 10mt, last radio frequency source power 400w, following radio-frequency power 0w, gas are Cl ₂20sccm, SF ₆100sccm, O ₂The mist of 20sccm, the time is 3s; Step 2: pressure 10mt, last radio frequency source power 800w, following radio-frequency power 0w, gas are Cl ₂20sccm, SF ₆100sccm, O ₂The mist of 20sccm, the time is 3s.

Shown in Fig. 3 and 4, the profile of etching gained polysilicon chip lines presents serious trapezoidal situation, and significantly " neck " (recess) shape appearred in the intersection of hard mask layer and polysilicon layer, and little channel effect has taken place.

Embodiment 2

With the method for embodiment 1, its difference is:

Increased stabilizing step 1 before BT step, process conditions are: pressure 7mt, go up radio frequency source power 0w, radio-frequency power 0w, gas CF down ₄50sccm, time 5s;

Increased stabilizing step 2 before main etching step, process conditions are: pressure 10mt, go up radio frequency source power 0w, radio-frequency power 0w, gas are Cl down ₂30sccm, HBr 170sccm, He/O ₂The mist of 10sccm, etch period are 5s;

Increased stabilizing step 3 before over etching step, process conditions are: pressure 60mt, go up radio frequency source power 0w, radio-frequency power 0w, gas are HBr 200sccm, He 140sccm, He/O down ₂The mist of 15sccm, the time is 5s.

As illustrated in Figures 5 and 6, recess and the disappearance of little channel effect have appearred in the intersection of etching gained polysilicon chip lines hard mask layer and polysilicon layer.

Embodiment 3

With the method for embodiment 2, its difference is: stabilizing

step

1,2 and 3 process conditions are: pressure sets 0mt, goes up radio frequency source power 0w, radio-frequency power 0w, gas N down ₂150sccm, the time is 10s.

As shown in Figure 7, recess and the disappearance of little channel effect have appearred in the intersection of etching gained polysilicon chip lines hard mask layer and polysilicon layer.

Embodiment 4

With the method for embodiment 2, its difference is: the pressure of stabilizing step 1 is that the pressure of 10mt, stabilizing step 2 is that the pressure of 15mt, stabilizing step 3 is 60mt, and last radio frequency source power 0w, radio-frequency power 0w, gas are N down ₂The mist of 100sccm, He 100sccm, Ar 100sccm, the time is 10s.

As shown in Figure 8, recess and the disappearance of little channel effect have appearred in the intersection of etching gained polysilicon chip lines hard mask layer and polysilicon layer.

Embodiment 5

With the method for embodiment 2, its difference is: stabilizing

step

1,2 and 3 process conditions are: pressure is set 10mt, is gone up radio frequency source power 0w, radio-frequency power 0w, gas are the mist of Ar 120sccm and He 200sccm down, and the time is 8s.

Shown in Fig. 9-10, the intersection of etching gained polysilicon chip lines hard mask layer and polysilicon layer recess occurred and little channel effect disappears.

Claims

1. the polycrystalline silicon etching process that can eliminate residual gas, comprise that running through etching step, main etching step, over etching step and dry method cleans the step, it is characterized in that, increased stabilizing step 1 in the described etching that runs through before step, process conditions are: chamber pressure 0-10mT, upper/lower electrode power is 0w, and gases used consistent with flow with running through etching step gaseous species, the time is 5-10s; Increased stabilizing step 2 at described main etching before step, process conditions are: chamber pressure 0-15mT, upper/lower electrode power is 0w, gases used consistent with flow with main step at quarter gaseous species, the time is 5-10s, increases stabilizing step 3 at described over etching before the step, process conditions are: chamber pressure 0-60mT, upper/lower electrode power is 0w, and gases used consistent with flow with over etching step gaseous species, the time is 5-10s.