CN100375068C - Selective prefetch method and bridge module - Google Patents
Selective prefetch method and bridge module Download PDFInfo
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- CN100375068C CN100375068C CNB2005101058890A CN200510105889A CN100375068C CN 100375068 C CN100375068 C CN 100375068C CN B2005101058890 A CNB2005101058890 A CN B2005101058890A CN 200510105889 A CN200510105889 A CN 200510105889A CN 100375068 C CN100375068 C CN 100375068C
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Abstract
The present invention relates to a selective prefetch method which is used for a bridge connection module. The bridge connection module is provided with a prefetch controller and a memory controller, wherein the prefetch controller is provided with at least one source comparison buffer capable of storing at least one judgment reference value; the selective prefetch method comprises the following procedures: firstly, the bridge connection module receives a command, and subsequently, the prefetch controller judges whether the source of the command accords with a particular source or not according to the judgment reference value; when the source of the command accords with the particular source, the prefetch controller executes a prefetch action through the memory controller; inversely, when the source of the command does not accord with the particular source, the prefetch controller does not execute the prefetch action.
Description
Technical field
The present invention relates to a kind of selective prefetch method and bridge module, relate in particular to a kind of selective prefetch method and bridge module that is used for computer system.
Background technology
Please referring to Fig. 1, it is the synoptic diagram of conventional personal computer system.Conventional personal computer 1 comprises a casing (not shown), a motherboard 11, a display screen 12.Wherein, motherboard 11 has a CPU (central processing unit) 111 (CPU), a main bus 112, a north bridge module 113, a rambus 114, a DRAM (Dynamic Random Access Memory) 115, a south bridge module 116, an I/O (I/O) bus 117, an advanced graphics port (AGP) bus 118, reaches a video and graphic accelerator card (hereinafter to be referred as the VGA card) 119.Casing is in order to place motherboard 11 and at least one peripheral unit 13, and for example hard disk, CD-ROM drive, power supply unit etc. promptly form the known main frame of general user.Generally speaking, CPU (central processing unit) 111 is connected by main bus 112 with north bridge module 113, and north bridge module 113 is connected by rambus 114 with internal memory 115, and north bridge module 113 is connected by AGP bus 118 with VGA card 119.
In conventional personal computer system 1, CPU (central processing unit) 111 is used for the overall operation of control computer system 1, north bridge module 113 be used for controlling high-speed peripheral (for example internal memory 115) and and CPU (central processing unit) 111 between the signal transmission.And south bridge module 116 is transmitted by the signal that input/output bus 117 is used for controlling between low speed peripheral unit 13 (for example hard disk, input/output device) and the north bridge module 113.VGA card 119 is in order to carry out graphic operation to produce vision signal to drive display screen 12.
Along with scientific-technical progress, the function of central processing unit 111 from strength to strength and execution speed more and more faster, therefore personal computer system 1 performance depends on the speed of internal memory 115 or peripheral unit 13, for example, when personal computer system's 1 executive utility, the access of internal memory 115 may consume the execution time of long application program, and the access time that therefore how to shorten internal memory 115 is epochmaking problem to promote the efficient of computer system.
Generally speaking, in the cycle, a Memory Controller Hub (not shown) of north bridge module 113 inside can receive the memory address of desiring access by rambus 114, is addressed to internal memory 115 corresponding addresses after being deciphered and writes to carry out reading of data in memory access.Because internal memory 115 access speeds own limit, so personal computer system 1 usually can spend many times in the data of waiting for access memory 115.Those skilled in the art have disclosed a kind of looking ahead (Prefetch) mechanism to solve the above problems at present, prefetch mechanisms is earlier data to be stored in the impact damper of a high speed, for example in the LRU impact damper, if required data have been pre-fetched in the impact damper of a high speed, then the data of buffer can be taken out at the internal memory read cycle, can significantly reduce the access time of internal memory 115, to promote the efficient of computer system.
But, traditional prefetch mechanisms whether need not to consider to carry out the action of looking ahead, the action of looking ahead of execution just blindly, therefore when the data of looking ahead are not required data, can cause whole efficiency low on the contrary,, not meet demand in fact for the modern science and technology that requires efficient and utilization rate, therefore how to provide a kind of selective prefetch method and bridge module of effectively prefetch data, real one of the current important topic that belongs to.
Summary of the invention
In view of above-mentioned problem, the purpose of this invention is to provide a kind of selective prefetch method and bridge module of effectively prefetch data.
Thus, for reaching above-mentioned purpose, be implemented on a bridge module according to selective prefetch method of the present invention, wherein bridge module has a prefetch controller and a Memory Controller Hub, prefetch controller has relatively buffer of at least one source, and source relatively buffer stores at least one judgement reference value, and selective prefetch method of the present invention comprises the following step: at first, receive an instruction by bridge module; Then, whether prefetch controller meets a peripherals according to the source of judging the reference value decision instruction; Moreover when the source of instruction when meeting this peripherals, prefetch controller is carried out the action of looking ahead by this Memory Controller Hub; Otherwise when the source of instruction did not meet this peripherals, prefetch controller was not carried out this action of looking ahead.
Thus, for reaching above-mentioned purpose, match with an internal memory according to bridge module of the present invention, bridge module of the present invention comprises a Memory Controller Hub and a prefetch controller.Wherein, prefetch controller has relatively buffer of a source, and it stores at least one judgement reference value, and Memory Controller Hub is in order to access memory.Prefetch controller can according to judge reference value judge one the instruction the source whether meet a peripherals, when the source of instruction meets this peripherals, prefetch controller is carried out the action of looking ahead by Memory Controller Hub, when the source of instruction did not meet this peripherals, prefetch controller was not carried out this action of looking ahead.
In sum, because of judging by prefetch controller elder generation foundation whether the source of reference value decision instruction meets peripherals according to selective prefetch method of the present invention and bridge module, and when the source of instruction meets this peripherals, prefetch controller is carried out the action of looking ahead by Memory Controller Hub, when the source of instruction does not meet this peripherals, prefetch controller is not carried out this action of looking ahead, so promptly optionally whether decision will look ahead action to avoid blindly looking ahead action, so whole efficiency of the computer system of prefetch data, and then lifting effectively.
Description of drawings
Fig. 1 is the synoptic diagram of conventional personal computer system;
Fig. 2 is the synoptic diagram of a computer system, and it comprises the bridge module of preferred embodiment of the present invention; And
Fig. 3 is the process flow diagram of the selective prefetch method of preferred embodiment of the present invention.
The element numbers complete list
| Numbering | |
| 1 | Conventional |
| 11 | |
| 12 | Display screen |
| 111 | CPU (central processing unit) |
| 112 | |
| 113 | The |
| 114 | |
| 115 | DRAM (Dynamic Random Access Memory) |
| 116 | The |
| 117 | Input/ |
| 118 | The AGP |
| 119 | The video and graphic accelerator card |
| 13 | Peripheral unit |
| 2 | Computer system |
| 20 | Bridge module |
| 231 | The source is buffer relatively |
| 232 | The working area of looking ahead |
| 233 | The history accuracy register as a result of looking ahead |
| 22 | Memory Controller Hub |
| 23 | Prefetch controller |
| S01～S06 | The process step of the selective prefetch method of preferred embodiment |
Embodiment
Hereinafter with reference to relevant drawings, selective prefetch method and bridge module according to preferred embodiment of the present invention are described.
Please, wherein be depicted as the synoptic diagram that bridge module 20 of the present invention is applied to a computer system 2 referring to Fig. 2.And the foregoing personal computer system 1 of the operation principles of computer system 2 is not influencing under the disclosed situation of the technology of the present invention, is no longer given unnecessary details about the operation principles of computer system 2, and wherein identical assembly gives identical element numbers.The bridge module 20 of preferred embodiment of the present invention is to match with internal memory 115 in the computer system 2.Below explanation is that data with the internal memory 115 of looking ahead are as a preferred embodiment explanation.
The bridge module 20 of this preferred embodiment can be that a north bridge module is used for controlling and CPU (central processing unit) 111 between the signal transmission.Certainly bridge module 20 also can be an integral chip group (integrated chipset) with south/north bridge module.Bridge module 20 comprises a Memory Controller Hub 22 and a prefetch controller 23.
Prefetch controller 23 comprises relatively buffer 231, a working area 232 and the history accuracy register 233 as a result of looking ahead of looking ahead of a source.
Wherein, source relatively buffer 231 stores at least one judgement reference value, this judges that reference value can be a source reference value, compare and judge whether to look ahead the usefulness of action in order to the follow-up prefetch controller 23 that offers, the working area 232 of looking ahead is a high-speed buffer, LRU impact damper for example, its content comprise look ahead action obtained prefetch data and address thereof.
History the look ahead accuracy of action of accuracy register 233 analytic records as a result of looking ahead, specifically, history look ahead as a result accuracy register 233 be used for statistics, record before the H till, when action is looked ahead in execution, the probability that prefetch data is really used.If present accuracy is higher, prefetch controller 23 just can be carried out the action of looking ahead; If present accuracy is lower, then prefetch controller 23 can not carried out the action of looking ahead.
Memory Controller Hub 22 connects internal memory 115, both interconnect by rambus 114, this rambus 114 is in order to data, memory address and the control signal of transmission DRAM, and rambus 114 comprises data bus (data bus), address bus (address bus), reaches control signal bus (control signal bus) in addition.
But prefetch controller 23 basis sources compare the judgement reference value in the buffer 231, judgement is from central processing unit 111 or whether the source of the instruction of peripheral unit (for example pci bus device) conforms to a particular source, when the source of instruction meets particular source, prefetch controller 23 is through the action of looking ahead by Memory Controller Hub 22 execution one, when the source of instruction did not meet particular source, prefetch controller 23 was not carried out the action of looking ahead.
In the present embodiment, receive when prefetch controller 23 to read instruction and address when meeting the address of being looked ahead in the working area 232 of looking ahead, then directly prefetch data is taken out and needn't therefore can effectively save the time of data read via Memory Controller Hub 22.
Please refer to Fig. 3, wherein be depicted as the process flow diagram of the selective prefetch method of preferred embodiment of the present invention, selective prefetch method of the present invention may be implemented in above-mentioned bridge module, below in order to the explanation bridge module 20 the start flow process.
Step S01: set the relatively judgement reference value of buffer 231 of source, generally speaking, central processing unit 111 itself has had pre-fetch function at present, if bridge module 20 is looked ahead at the instruction of central processing unit 111 again, then cause the waste in processing time on the contrary, therefore central processing unit 111 is set get rid of and judged outside the reference value, so when prefetch controller 23 is analyzed received instruction from central processing unit 111, the action of not looking ahead is to avoid the waste in processing time.
Step S02: receive an instruction by bridge module 10, for example, the source of this instruction can be central processing unit 111 or peripheral unit 13.
Step S03: prefetch controller 23 is according to judging that reference value judges whether the source of this instruction meets a particular source, at this if this instruction of hypothesis from the instruction of central processing unit 111, when bridge module 10 receives this instruction, learn that promptly this instruction is sent by central processing unit 111, and whether the source of this instruction is a particular source according to judging that reference value is judged, to determine whether will look ahead action, at this, central processing unit 111 is not for judging one of reference value, therefore prefetch controller 23 judges that the source of this instruction does not meet particular source, i.e. execution in step S05.Otherwise if suppose this instruction from a peripheral unit 13 (for example pci bus device), then prefetch controller 23 judges that the source of these instructions meets particular source, i.e. execution in step S04.
Step S04: prefetch controller 23 looks ahead as a result according to historical whether the rate of correct judgment as a result of accuracy register 233 is higher than a standard value, if present accuracy is higher, i.e. and execution in step S06; If present accuracy is lower, then execution in step S05.
Step S05: prefetch controller 23 is not carried out the action of looking ahead, and at this, prefetch controller 23 judges that according to the judgement reference value source of this instruction does not meet particular source, so prefetch controller 23 is not carried out the action of looking ahead; In addition, when prefetch controller 23 according to historical when looking ahead that the rate of correct judgment as a result of accuracy register 233 is lower than a standard value as a result, prefetch controller 23 is not also carried out the action of looking ahead.
Step S06: prefetch controller 23 is carried out the action of looking ahead by Memory Controller Hub 22.
In sum, because of according to selective prefetch method of the present invention and bridge module by prefetch controller earlier according to judging that reference value judges whether a source of instructing meets a particular source, then when the source of instruction meets particular source, prefetch controller is carried out the action of looking ahead by Memory Controller Hub, when the source of instruction does not meet particular source, prefetch controller is not carried out this action of looking ahead, so promptly optionally determine whether will look ahead action, thereby avoided the action of blindly looking ahead, so whole efficiency of the computer system of prefetch data, and then lifting effectively.
The above only is an illustrative, but not is restricted.Anyly do not break away from spirit of the present invention and category, and, all should be contained in the claims scope its equivalent modifications of carrying out or change.
Claims (12)
1. selective prefetch method, be imposed in a bridge module, this bridge module has a prefetch controller and a Memory Controller Hub, this prefetch controller has relatively buffer of at least one source, and this source relatively buffer stores at least one judgement reference value, and this selective prefetch method comprises:
Receive an instruction by this bridge module;
This prefetch controller judges that according to this reference value judges whether the source of this instruction meets a peripherals;
When the source of this instruction met this peripherals, this prefetch controller was carried out the action of looking ahead by this Memory Controller Hub; And
When the source of this instruction did not meet this peripherals, this prefetch controller was not carried out this action of looking ahead.
2. selective prefetch method as claimed in claim 1, wherein this prefetch controller also comprises the working area of looking ahead, and this selective prefetch method also comprises:
A this obtained prefetch data and address thereof of action of looking ahead is temporarily stored in this working area of looking ahead.
3. selective prefetch method as claimed in claim 1, wherein this judgement reference value is a source reference value.
4. selective prefetch method as claimed in claim 1, wherein this prefetch controller also comprises the history accuracy register as a result of looking ahead, and this selective prefetch method also comprises:
This history look ahead accuracy register analytic record as a result this look ahead the action accuracy; And
When this accuracy of looking ahead action was lower than a standard value, this prefetch controller was not carried out this action of looking ahead.
5. selective prefetch method as claimed in claim 1, wherein this instruction is sent or is sent by a computer peripheral device by a central processing unit.
6. selective prefetch method as claimed in claim 1, wherein this bridge module is a north bridge chips or is an integral chip.
7. bridge module, it is to match with an internal memory, this bridge module comprises:
One Memory Controller Hub, it is in order to this internal memory of access; And
One prefetch controller, it has relatively buffer of a source, wherein this source comparison buffer stores at least one judgement reference value, this prefetch controller according to this judge reference value judge one the instruction the source whether meet a peripherals, wherein when the source of this instruction meets this peripherals, this prefetch controller is carried out the action of looking ahead by this Memory Controller Hub, and when the source of this instruction did not meet this peripherals, this prefetch controller was not carried out this action of looking ahead.
8. bridge module as claimed in claim 7, wherein this prefetch controller also comprises the working area of looking ahead, and this an obtained prefetch data and address thereof of action of looking ahead is temporarily stored in this working area of looking ahead.
9. bridge module as claimed in claim 7, wherein this instruction is sent or is sent by a computer peripheral device by a central processing unit.
10. bridge module as claimed in claim 7, this bridge module are a north bridge chips or are an integral chip.
11. bridge module as claimed in claim 7, wherein this judgement reference value is a source reference value.
12. bridge module as claimed in claim 7, wherein this prefetch controller also comprises the history accuracy register as a result of looking ahead, this history look ahead accuracy register analytic record as a result this look ahead the action accuracy, and when this accuracy of looking ahead action was lower than a standard value, this prefetch controller was not carried out this action of looking ahead.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101058890A CN100375068C (en) | 2005-09-29 | 2005-09-29 | Selective prefetch method and bridge module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101058890A CN100375068C (en) | 2005-09-29 | 2005-09-29 | Selective prefetch method and bridge module |
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| CN1744059A CN1744059A (en) | 2006-03-08 |
| CN100375068C true CN100375068C (en) | 2008-03-12 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09231164A (en) * | 1996-02-28 | 1997-09-05 | Nec Corp | Bus bridge and computer system equipped with the bus bridge |
| US5787475A (en) * | 1992-07-21 | 1998-07-28 | Digital Equipment Corporation | Controlled prefetching of data requested by a peripheral |
| EP1096384A1 (en) * | 1999-10-26 | 2001-05-02 | Bull S.A. | Bridge unit between a system bus and a local bus |
| JP2003316723A (en) * | 2002-04-25 | 2003-11-07 | Nec Corp | Bus bridge device, and bus cycle control method and program |
| US6795876B1 (en) * | 2001-03-27 | 2004-09-21 | Intel Corporation | Adaptive read pre-fetch |
| US20040225771A1 (en) * | 2000-12-28 | 2004-11-11 | Riesenman Robert J. | Data pre-fetch control mechanism and method for retaining pre-fetched data after PCI cycle termination |
-
2005
- 2005-09-29 CN CNB2005101058890A patent/CN100375068C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5787475A (en) * | 1992-07-21 | 1998-07-28 | Digital Equipment Corporation | Controlled prefetching of data requested by a peripheral |
| JPH09231164A (en) * | 1996-02-28 | 1997-09-05 | Nec Corp | Bus bridge and computer system equipped with the bus bridge |
| EP1096384A1 (en) * | 1999-10-26 | 2001-05-02 | Bull S.A. | Bridge unit between a system bus and a local bus |
| US20040225771A1 (en) * | 2000-12-28 | 2004-11-11 | Riesenman Robert J. | Data pre-fetch control mechanism and method for retaining pre-fetched data after PCI cycle termination |
| US6795876B1 (en) * | 2001-03-27 | 2004-09-21 | Intel Corporation | Adaptive read pre-fetch |
| JP2003316723A (en) * | 2002-04-25 | 2003-11-07 | Nec Corp | Bus bridge device, and bus cycle control method and program |
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| CN1744059A (en) | 2006-03-08 |
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