CN100375063C - Method and device for managing transmitting buffer area in field programmable gate array - Google Patents
Method and device for managing transmitting buffer area in field programmable gate array Download PDFInfo
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- CN100375063C CN100375063C CNB2004100099155A CN200410009915A CN100375063C CN 100375063 C CN100375063 C CN 100375063C CN B2004100099155 A CNB2004100099155 A CN B2004100099155A CN 200410009915 A CN200410009915 A CN 200410009915A CN 100375063 C CN100375063 C CN 100375063C
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Abstract
The present invention relates to a method and a device for managing a transmitting and buffering area in a field programmable gate array FPGA. A buffering area storing unit, a write-in controlling unit, a reading/ writing pointer register, a total length/ write-in length register, a state indicating unit and a reading unit are defined in the FPGA. Through the write-in controlling unit, a data frame to be transmitted is read out from an externally hung RAM many times and is written in the buffering area storing unit in the FPGA. The data is read from the buffering area by the reading unit and is sent out. Through the present invention, under the condition that the data frame is processed for a long time, a blocks RAM resource in the FPGA, which is occupied by the buffering area is very few, so lots of blocks RAM resources in the FPGA can be saved.
Description
Technical field
The present invention relates to field programmable gate array (FPGA), relate in particular at the scene and manage the method and apparatus that sends buffer zone in the programmable gate array (FPGA).
Background technology
In the FPGA of current communication field design, often processed Frame to be kept in plug-in high capacity RAM earlier, again Frame is moved into the transmission buffer zone of FPGA inside afterwards, send at last.Usual method is that the capacity of transmission buffer zone is 1 complete Frame length at least.Whenever have data to need to send and FIFO buffer (FIFO) in space when surpassing frame length; Just begin whole packet is moved among the FIFO.The advantage of this method is that disposal route is simple.But under the situation that maximum length is long, sendaisle quantity is many of processed frame type, needed FPGA internal storage region will need very big.(for example the frame length of Ethernet can be 1518 BYTE, if sendaisle is 32, the transmission buffer pool size that so only needs is 1518*32*8=388Kbit at least.) this will be a very big expense for FPGA.
At application number is 03121413.4 (publication number: in Chinese patent application CN1439966), described a kind of the needed FIFO of a plurality of passages is integrated in the two-port RAM, and the read-write pointer control of each passage also has been integrated in a device in the read/write pointer control module respectively.This device has reduced a plurality of independent FIFO and has constructed employed a large amount of read-write pointer counter resources.But this patent can not solve under the very long situation of frame length to be processed, and buffer zone takies inner a large amount of storage block (BLOCKRAM) problem of resource of FPGA.
Summary of the invention
Technical matters to be solved by this invention provides a kind of method and apparatus that sends buffer zone of managing in FPGA, solve under the very long situation of frame length to be processed, and buffer zone takies inner a large amount of storage block (BLOCKRAM) problem of resource of FPGA.
The invention provides a kind of method that sends buffer zone of in FPGA, managing, it is adapted to have the FPGA of plug-in RAM, adopt the method for repeating query to import FPGA several times into by a long data frame that will be stored among the plug-in high capacity RAM, to save the inner buffer resource that sends of FPGA.
According to said method of the present invention, further comprise the steps:
Step 1: in the inner definition of FPGA buffer stores unit, write control unit, read/write pointer register, total length/write length register, state indicating member, sensing element, and with total length/write length register, read/write pointer all to be initialized as 0;
Step 2: the said write control module is inquired about described plug-in RAM, when finding that the Frame that will transmit is arranged, is the length of this frame with the total length assignment of total length register, is 0 with the length assignment that writes that writes in the length register;
Step 3: the said write control module adopts the method for repeating query, reads and be written to Frame in the described buffer stores unit from described plug-in RAM several times; With the current writing of described read/write pointer register difference log buffer storage unit; Read data in the described buffer stores unit by described sensing element, send then; Finish when a frame sends, just change step 2 over to.
According to said method of the present invention, under single transmit passage situation, in described step 3, the said write control module once need to determine the data length that transmits by inquiry total length/write length register, and constantly can the query State indicating member hold the once partial data of transmission with the free space of determining buffer zone; Whenever data write or during the playback buffer district, just whether surpass predetermined threshold value by the state indicating member according to the idle capacity that the read/write pointer register calculates buffer zone, and the update mode value.
According to said method of the present invention,, when the length that deducts the remainder frame that writes the length gained when total length is less than or equal to the length S of write-once, then transmit the length that length is the remainder frame in described step 3; When the length of remainder frame during greater than the length S of write-once, then transmitting length is S, by write control unit from plug-in RAM reading of data read the value that the side-play amount of starting point in frame equals to write length register, whenever write control unit when buffer zone writes data, write pointer increases progressively 1, will write length register simultaneously and upgrade; Judged whether that according to the read/write pointer register data can read with sensing element, and after each sense data, upgraded read pointer.
According to said method of the present invention, described buffer stores unit comprises a plurality of passages, in described step 3,, use as one " position form " with read/write pointer register, total length/write length register to be stored in according to channel number in the block RAM of FPGA inside; In the state indicating member, record the state of each passage; By each passage of write control unit repeating query, search and allow the passage that writes, and determined whether that Frame needs to send.
According to said method of the present invention, with buffer zone merging the becoming whole piece dual port RAM capacious of a plurality of passages, each passage takies fixing part zone, in the time of each the visit, the high address is used for selector channel number, and low order address is used for representing the buffer zone home address of respective channel; When write control unit found that available passage is arranged, the access location form obtained the strange storage of read/write pointer, total length/write the numerical value in the length register.
The invention provides a kind of device that sends buffer zone of managing in FPGA, it comprises:
One buffer stores unit is used for the data of the Frame that buffer-stored will send;
One read/write pointer register is used for the current position of reading, writing of log buffer storage unit respectively;
One total length/write length register is used for writing down respectively the total length of current buffer zone Frame, writes length;
One write control unit is used for the data of a Frame are read continuously from plug-in RAM several times, is written in the buffer stores unit of FPGA inside;
One sensing element is used for the data of buffer stores unit are read, sent;
One state indicating member is used to indicate the free space of current buffer zone whether to surpass predetermined threshold value, whether can hold the partial data that once transmits;
When among the plug-in RAM Frame that will transmit being arranged, write control unit once need to determine the data length that transmits by total length/write length register, the query State indicating member is to determine in the buffer zone whether enough free spaces being arranged, when enough spaces, sense data from plug-in RAM, and the data of being read are write the buffer stores unit.
According to said apparatus of the present invention, described buffer stores unit is single pass.
According to said apparatus of the present invention, described buffer stores unit is multichannel, and wherein multichannel buffer zone merges becomes the whole piece dual port RAM, and each passage takies wherein fixing part zone.
According to said apparatus of the present invention, the read/write pointer register of described each passage, total length/write length register to be stored in according to channel number in another block RAM of FPGA inside are as " position form "; Each paths of write control unit repeating query is with the passage of determining to write; Write control unit access location form therefrom obtains write pointer register, total length/write the numerical value in the length register, and whether inquiry judging has Frame to need to send; When Frame sends and available passage is arranged, reading section frame from plug-in RAM just, and being written in the corresponding region of dual port RAM, and the write pointer register after will upgrading, total length/write length register numerical value to deposit in the form of position; The strange storage of read/write pointer in the sensing element inquiry " position form ", judging has the data of denying to read, and after each sense data, upgrades read pointer and also deposits back in " position form ".
Description of drawings
Fig. 1 is the structural drawing of the FPGA internal circuit of the present invention under the single channel situation.
Fig. 2 is the present invention send the FPGA internal circuit under the situation of passage at pilosity a structural drawing.
Fig. 3 is a method flow diagram of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
Shown in Figure 1 be the structural drawing of the present invention under the single channel situation.When among the plug-in RAM packet being arranged, the continuous query State indicating member of write control unit is ' 1 ' if find it, and explanation can be held the data that once transmit, and then prepares to write.Write control unit is at first with reference to " total length/write length register ", need to determine the partial data frame length that once transmits.Concrete method is: deducted by the total length of Frame and write the length that length register obtains the remainder frame.Before in Frame writes buffer zone, write length register and should be 0, the length of remainder frame at this moment just equals the length of the complete data frame preserved among the plug-in RAM.If the length of remainder frame is equal to or less than the length threshold S that once transmits data, then the Frame of at this moment reading from plug-in RAM can all be written in the buffer zone once; If the length of resulting remainder frame is greater than the length S of write-once, then the length of Chuan Songing is S, write control unit is the data in the continuous sense data frame from plug-in RAM, the frame bias internal amount that reads starting point equals to write the value of length register, simultaneously the data of reading is write the FPGA internal buffer continuously.To " write length register " again upgrades, and increases to the length of this transmission, with as reading starting point the next time of Frame; Whenever write data, write pointer increases progressively 1.Finish after the transmission of a Frame, then prepare the transmission of next frame, the total length register is updated to the length of next frame when in finding plug-in RAM new Frame being arranged, and has write length register and has been updated to 0.Afterwards, write control unit repeats aforesaid operations.
Whenever data write or during the playback buffer district, the state indicating member is just according to " read/write pointer register ", whether the idle capacity that calculates buffer zone surpasses certain threshold value, and update mode value correspondingly.
Sensing element has judged whether that according to the read/write pointer register data can read.After each sense data, need to upgrade read pointer.
For example in the application of Ethernet, frame length=1518 BYTE.We adopt the design of new method, and write-once length S is 64 BYTE, and buffer pool size can be set to 128 BYTE, and the thresholding that allows to write zone bit can be set to 64 BYTE (be exactly be equivalent to half-full).The frame of 1518 length just is divided into 24 times and writes buffer zone, and the preceding length that writes for 23 times all is 64 BYTE, and the 24th time the length that writes is 46 BYTE.As seen, utilize said method of the present invention, transmitting length is the Frame of 1518 BYTE, and needed transmission buffer pool size is 128*8=1Kbit, makes used dual port RAM reduce greatly, has saved the needed BLOCKRAM resource of transmission buffer zone.
Fig. 2 has described the structural drawing under the present invention send passage at pilosity the situation.At this moment, because each channel buffer capacity can be set very for a short time, if use an independent BLOCKRAM for each passage then can waste very much, become whole piece dual port RAM capacious so the buffer zone of a plurality of passages can be merged, each passage takies fixing part zone.In the time of each visit, the high address is used for selector channel number, and low order address is used for representing the buffer zone home address of respective channel.In addition, also " read/write pointer register, total length/write length register " can be stored in another block RAM of FPGA inside according to channel number, use as one " position form ".At this moment, the state indicating member is merged by multiplexer channel state indicating bit separately becomes a vector and constitutes.
During work, write control unit is worked according to the mode of each paths of repeating query: the zone bit of seeing the space of which passage earlier allows to write, and whether inquiry has Frame to need to send.After having found available passage, with regard to the access location form, obtain the read/write pointer register, total length/write the numerical value of length register.Handle according to method like the single channel channel types then, obtain writing length.Afterwards, begin and to read partial frame among the plug-in RAM, and be written to the corresponding region of dual port RAM.At last, " write pointer register/total length register/write length register " after upgrading being deposited return puts in the form.
The working method of sensing element also respective change is: inquiry " position form " earlier obtains the numerical value of read/write pointer register, has judged whether that data can read.After each sense data, upgrade read pointer, again read pointer is deposited back " the position form " in.
For example, when the frame length of handling is 1518 BYTE to the maximum, treatment channel quantity is 32, if when selecting for use the size of the inner BLOCKRAM of FPGA to be 4KBIT, use said structure of the present invention, the transmission buffer zone of every paths is made as 128 BYTE, then total buffer pool size=128*32=4K BYTE (taking 8 BLOCKRAM).In the form of position, 4 records of " read pointer/write pointer/total length/write length " that each passage is preserved respectively account for 2 BYTE.RAM capacity=32*8=256 BYTE (taking 1 BLOCKRAM) that whole position form uses.Like this, total BLOCKRAM quantity that takies only needs 9, and if use traditional method 388Kbit to take 95 BLOCKRAM at least.As seen under multichannel situation, use said method of the present invention can obviously reduce the inner BLOCKRAM number of resources of using of FPGA.
Fig. 3 shows method flow diagram of the present invention.As shown in Figure 3, at step S1: in the inner definition of FPGA buffer stores unit, write control unit, read/write pointer register, total length/write length register, state indicating member, sensing element, and with total length/write length, read/write pointer all to be initialized as 0;
At step S2: the said write control module is inquired about described plug-in RAM, when finding the Frame that will transmit is arranged, is the length of this frame with the total length assignment of total length register, is 0 with the length assignment that writes that writes in the length register;
At step S3, the said write control module adopts the method for repeating query, reads and be written to Frame in the described buffer stores unit from described plug-in RAM several times; With the current writing of described read/write pointer register difference log buffer storage unit; Read data in the described buffer stores unit by described sensing element, send then; Finish when a frame sends, just change step S2 over to.
Above described method under single transmit passage situation, at described step S3, once need to determine the data length that transmits by the said write control module by inquiry total length/write length register, and constantly can the query State indicating member hold the once partial data of transmission with the free space of determining buffer zone; Whenever data write or during the playback buffer district, whether the state indicating member just surpasses predetermined threshold value according to the idle capacity that the read/write pointer register calculates buffer zone, and the update mode value.
For top described method,, when the length that deducts the remainder frame that writes the length gained when total length is less than or equal to the length S of write-once, then transmit the length that length is the remainder frame at described step S3; When the length of remainder frame during greater than the length S of write-once, then transmitting length is S, in this case, write control unit from plug-in RAM reading of data read the value that the side-play amount of starting point in frame equals to write length register, whenever write control unit when buffer zone writes data, write pointer increases progressively 1, will write length register simultaneously and upgrade; Judged whether that according to the read/write pointer register data can read with sensing element, and after each sense data, upgraded read pointer.
For top described method, described buffer stores unit can comprise a plurality of passages, at this moment, at described step S3, read/write pointer register, total length/write length register to be stored in according to channel number in the block RAM of FPGA inside can be used as one " position form "; In the state indicating member, record the state of each passage; By each passage of write control unit repeating query, search and allow the passage that writes, and determined whether that Frame needs to send.In addition, the buffer zone of above-mentioned a plurality of passages can be able to be combined to be whole piece dual port RAM capacious, wherein each passage takies fixing part zone, in the time of each the visit, the high address is used for selector channel number, and low order address is used for representing the buffer zone home address of respective channel; When write control unit found that available passage is arranged, the access location form obtained read/write pointer register, total length/write the numerical value in the length register.
Claims (9)
1. in FPGA, manage the method that sends buffer zone for one kind, be adapted to have the FPGA of plug-in RAM, it is characterized in that, comprise the steps:
Step 1: in the inner definition of FPGA buffer stores unit, write control unit, read/write pointer register, total length/write length register, state indicating member, sensing element, and with total length/write the strange storage of length, read/write pointer all is initialized as 0;
Step 2: the said write control module is inquired about described plug-in RAM, when finding that the Frame that will transmit is arranged, is the length of this frame with the total length assignment of total length register, is 0 with the length assignment that writes that writes in the length register;
Step 3: the said write control module adopts the method for repeating query, reads and be written to Frame in the described buffer stores unit from described plug-in RAM several times; With the current writing of described read/write pointer register difference log buffer storage unit; Read data in the described buffer stores unit by described sensing element, send then; Finish when a frame sends, just change step 2 over to.
2. method according to claim 1, it is characterized in that, under single transmit passage situation, in described step 3, the said write control module once need to determine the data length that transmits by inquiry total length/write length register, and constantly can the query State indicating member hold the once partial data of transmission with the free space of determining buffer zone; Whenever data write or during the playback buffer district, just whether surpass predetermined threshold value by the state indicating member according to the idle capacity that the read/write pointer register calculates buffer zone, and the update mode value.
3. method according to claim 1 is characterized in that, in described step 3, when the length that deducts the remainder frame that writes the length gained when total length is less than or equal to the length S of write-once, then transmits the length that length is the remainder frame; When the length of remainder frame during greater than the length S of write-once, then transmitting length is S, by write control unit from plug-in RAM reading of data read the value that the side-play amount of starting point in frame equals to write length register, whenever write control unit when buffer zone writes data, write pointer increases progressively 1, will write length register simultaneously and upgrade; Judged whether that according to the read/write pointer register data can read with sensing element, and after each sense data, upgraded read pointer.
4. method according to claim 1, it is characterized in that, described buffer stores unit comprises a plurality of passages, in described step 3, with read/write pointer register, total length/write length register to be stored in according to channel number in the block RAM of FPGA inside, use as one " position form "; In the state indicating member, record the state of each passage; By each passage of write control unit repeating query, search and allow the passage that writes, and determined whether that Frame needs to send.
5. method according to claim 4, it is characterized in that, buffer zone merging becoming whole piece dual port RAM capacious with a plurality of passages, each passage takies fixing part zone, in the time of each the visit, the high address is used for selector channel number, and low order address is used for representing the buffer zone home address of respective channel; When write control unit found that available passage is arranged, the access location form obtained read/write pointer register, total length/write the numerical value in the length register.
6. a device that adopts the described method of claim 1 is characterized in that, comprising:
One buffer stores unit is used for the data of the Frame that buffer-stored will send;
One read/write pointer register is used for the current position of reading, writing of log buffer storage unit respectively;
One total length/write length register is used for writing down respectively the total length of current buffer zone Frame, writes length;
One write control unit is used for the data of a Frame are read continuously from plug-in RAM several times, is written in the buffer stores unit of FPGA inside;
One sensing element is used for the data of buffer stores unit are read, sent;
One state indicating member is used to indicate the free space of current buffer zone whether to surpass predetermined threshold value, whether can hold the partial data that once transmits;
When among the plug-in RAM Frame that will transmit being arranged, write control unit once need to determine the data length that transmits by total length/write length register, the query State indicating member is to determine in the buffer zone whether enough free spaces being arranged, when enough spaces, sense data from plug-in RAM, and the data of being read are write the buffer stores unit.
7. device according to claim 6 is characterized in that, described buffer stores unit is single pass.
8. device according to claim 6 is characterized in that, described buffer stores unit is multichannel, and wherein multichannel buffer zone merges becomes the whole piece dual port RAM, and each passage takies wherein fixing part zone.
9. device according to claim 8 is characterized in that, the read/write pointer register of described each passage, total length/write length register to be stored in according to channel number in another block RAM of FPGA inside are as " position form ";
Each paths of write control unit repeating query is with the passage of determining to write; Write control unit access location form therefrom obtains write pointer register, total length/write the numerical value in the length register, and has judged whether that Frame needs to send; When Frame sends and available passage is arranged, reading section frame from plug-in RAM just, and being written in the corresponding region of dual port RAM, and the write pointer register after will upgrading, total length/write length register numerical value to deposit in the form of position; Read/write pointer register in the sensing element inquiry " position form ", judging has the data of denying to read, and after each sense data, upgrades read pointer and also deposits back in " position form ".
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| CNB2004100099155A CN100375063C (en) | 2004-11-30 | 2004-11-30 | Method and device for managing transmitting buffer area in field programmable gate array |
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| CNB2004100099155A CN100375063C (en) | 2004-11-30 | 2004-11-30 | Method and device for managing transmitting buffer area in field programmable gate array |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661429B (en) * | 2009-08-18 | 2012-07-18 | 中兴通讯股份有限公司 | Storage method of statistical information and device thereof |
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| CN100527274C (en) * | 2006-11-03 | 2009-08-12 | 北京大学 | 3D read / write method for RAM in field programmable gate array |
| CN102096648B (en) * | 2010-12-09 | 2013-08-14 | 深圳中兴力维技术有限公司 | System and method for realizing multipath burst data business caching based on FPGA (Field Programmable Gate Array) |
| CN102521157B (en) * | 2011-12-13 | 2015-01-21 | 曙光信息产业(北京)有限公司 | System and method for realizing onboard storage resource management on FPGA (Field Programmable Gate Array) |
| CN103744621A (en) * | 2013-12-31 | 2014-04-23 | 深圳英飞拓科技股份有限公司 | Circular read-write method and device for buffer |
| CN110134630B (en) * | 2019-05-27 | 2023-02-10 | 西安电子工程研究所 | Design method of multi-input single-output transmission cache controller |
| CN111050107B (en) * | 2019-11-11 | 2022-09-27 | 湖南君瀚信息技术有限公司 | Wireless high-definition low-delay video transmission device, system and method |
| CN111128245A (en) * | 2019-12-19 | 2020-05-08 | 珠海市一微半导体有限公司 | Voice framing processing circuit and method |
| CN113141288B (en) * | 2021-04-23 | 2022-08-23 | 北京航天发射技术研究所 | Mailbox message receiving and sending method and device of CAN bus controller |
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| CN1439966A (en) * | 2003-03-28 | 2003-09-03 | 北京港湾网络有限公司 | Multichannel FILO data buffer storage devices |
| KR20040088105A (en) * | 2003-04-08 | 2004-10-16 | 엘지전자 주식회사 | Method for controlling buffer in flexible program array chip |
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| US20030160632A1 (en) * | 1998-12-31 | 2003-08-28 | Actel Corporation | Programmable multi-standard I/O architecture for FPGAs |
| CN1439966A (en) * | 2003-03-28 | 2003-09-03 | 北京港湾网络有限公司 | Multichannel FILO data buffer storage devices |
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