CN100373772C - On-chip fast signal generating circuit in alternating current sweep test - Google Patents
On-chip fast signal generating circuit in alternating current sweep test Download PDFInfo
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Abstract
The present invention belongs to the technical field of the structure test of large scale integrated circuits (LSIC) and particularly relates to an on-chip fast signal generating circuit in AC sweep test which is composed of a mode counter, a two-way selector, an NAND gate, a three-input AND gate and a self-locking storage unit. The circuit can be reconfigured only by a high-speed clock and has the characteristics of simple structure and little delay. At a configuring stage, the mode counter configures values in the mode counter according to configured signal input; at the time, the mode counter runs at a low speed; at a counting stage, the mode counter runs at a high speed and generates a modulating signal, a high-speed clock and a circuit enabling signal according to the content of a mode word for simple calculation so as to generate a required fast capture signal; the capture signal can be applied to an AC test and can also be applied to a bridging fault diagnosis as the fast capture signal. The circuit provided by the present invention has the characteristic of irrelevance to a circuit to be tested; thereby, the circuit can be used as an independent kernel to be applied to a system on-chip (SOC) test.
Description
Technical field
The present invention relates to the structural technical field of measurement and test of large scale integrated circuit, the fast signal that particularly is used for the ac sweep test on a kind of produces circuit, also relates to using the test environment that ac sweep test and low cost test equipment are tested chip.
Background technology
In LSI testing, structural measuring technology is widely accepted.Sweep test and memory built in self test of sram have been included in general A SIC (application-specific integrated circuit (ASIC)) design cycle.Along with the development of technology, be accompanied by the development of system level chip especially, chip functions becomes increasingly complex, integrated logical block on the single chip (such as microprocessor, memory, DSPs, the I/O controller) also more and more, this has just brought a lot of new challenges to test.These challenges mainly comprise: 1) frequency of testing equipment does not catch up with the raising of working frequency of chip, and it is more and more difficult to make that the true speed test becomes.2) testing time long, cause testing cost significantly to increase.3) testing equipment memory size less than 4) chip can be used as the test pin deficiency of full scan design.
In the design for Measurability based on scanning, the register in the primary circuit will be divided into several different parts, and the register in each part is contacted becomes a scan chain.Each bar scan chain is to having an input pin, an output pin.In the full scan design architecture of classics, the input of each bar scan chain is corresponding to the original input pin of a chip, and each output is corresponding to the original output pin of chip.The test and excitation vector is loaded into by shooting by automatic test equipment in each register of scan chain, and these test and excitation vectors produce by some automatic test vector Core Generators, are stored in the automatic test equipment through after the format conversion.After loading process finished, chip transferred functional mode to by test pattern, and under the functional mode situation, test vector is applied to circuit-under-test, and the response of test circuit is captured in the scan chain.At last, chip is converted into scan pattern again by functional mode, value in the scan chain is unloaded in the automatic test equipment internal memory, and the automatic test equipment response that will collect is compared with the correct response that is stored in advance in the internal memory then, determines the chip quality and fault message is provided.
In order to produce test vector, need be with the fault modeling of chip.The fault model that comparative maturity is generally acknowledged has: stuck-at fault, path time delay fault and jump delay failure and bridging fault.Stuck-at fault is meant that the value that hypothesis breaks down a little remains 1 or 0.Though the stuck-at fault model is very simple,, the verified this fault model of a lot of experiments is effectively.The flow process that produces test vector at stuck-at fault is: set possible fault point, and produce test vector at these fault points, these test vectors can be delivered to fault message on original output or the trigger.The program that is used for producing automatically test vector is called ATPG (test vector produces automatically).Various ATPG algorithms have been integrated in the commercial design for Measurability instrument.These instruments are summed up as stuck-at fault with various physical faults, and produce test vector at this fault model.
Jump delay failure is meant that a saltus step (can be 1-〉0 saltus step also can be 0-〉1 saltus step) can not be delivered to original output or register in a clock cycle.Two kinds of typical jump delay failure models are arranged: the saltus step fault that rises slowly and the jump delay failure that descends slowly.The saltus step fault is meant that the rising saltus step of any this node of process all is delayed the cycle of the time that causes signal to pass whole path when having surpassed clock work thereby node has taken place to rise slowly.Thereby the saltus step fault that descends slowly is meant the decline saltus step of any this node of process and all is delayed the cycle of the time that causes signal to pass whole path when having surpassed clock work.The path time delay fault is meant on the path accumulation of each and wire delay, and the one-period time that has surpassed clock when this accumulation will cause the incorrect of function.The path delay fault model can be found the problem that a lot of jump delay failure can not be found, yet the path time delay fault is because place mix is very many, makes that to produce the complexity of algorithm of test vector at this fault model big especially.If a design has N bar line, so at most have 2N saltus step fault, still, behind the calculating path, just have 2
NIndividual path, obviously, the complexity of calculating path fault will be far longer than the complexity of calculating the saltus step fault.
Chip is carried out true speed test, can help us to find more fault, be embodied in (1) and can find other faults beyond the stuck-at fault, such as the fault model in the delay testing: path fault and saltus step fault.The fault that these are relevant with sequential need could be spied out under high-speed case.(2) can find that other are not by modeled fault, stuck-at fault is a kind of good fault model, yet, it can not guarantee 100% coincide with physical fault, particularly to behind the deep submicron process, the fault characteristic that emerging fault characteristic and stuck-fault model are described has a lot of inconsistent aspects, thereby, if only use the test vector that produces at stuck-fault model to go to cover circuit under test, then having a lot of faults will can not be covered to.These faults great majority are directly relevant with sequential, so the true speed test helps our raising coverage rate to this part fault.
In the sweep test flow process, comprised three basic processes: load, function is caught and unloading.Common scan chain design why can not carrying out true speed is tested, and derive from the restraining factors of two aspects: (1) scan chain is long, makes the transposition frequency of scan chain be hard to keep at a high speed.(2) testing equipment can not provide true speed test clock and true speed test scan chain data channel.
A reasonable method as the solution above-mentioned two problems: the ac sweep test is accepted gradually and is adopted.The design philosophy of ac sweep test is: using traditional Scan Design hardware frame, also is that register still is concatenated into the multi-strip scanning chain.Scan test data moves into by the scan chain shifting function, uses fast clock signal to enable circuit under test in the function seizure stage and catches the response of circuit under test, still uses low-speed clock that the content in the test scan chain is shifted out at unloading phase.As can be seen, for common scanning process, the ac sweep test process is actually the process of " move soon slowly and grab ".Can be with reference to following document about the ins and outs of ac sweep test: " Experimental Study of Scan Based Transition Fault TestingTechniques ", Published by Vinay B.Jayaram, The master thesis of VirginiaPolytechnic Institute and State University, 2003
“An Experiment to Compare AC Scan and At-Speed Functional Testing”，Published by P.Maxwell，I.Hartanto and L.Bentz，In：Proceeding of EuropeanTest Workshop，2000
Chinese patent application CN1499213A discloses measuring circuit in a kind of path delay, and this circuit can be measured the path delay in the combinational circuit automatically under the situation of not using the LSI tester.But this circuit can't provide the high-frequency clock passage at external test facility, and then can't produce pulse signal acquisition and the multiple-pulse signal acquisition that meets ac sweep test and diagnosis usefulness.
Summary of the invention
The present invention will propose a kind of fast signal based on high-frequency clock and produce circuit, this circuit can directly provide the situation of high-frequency clock passage at external test facility, also can only provide low-speed clock, use the built-in chip type frequency multiplication of phase locked loop to go out the situation of high-frequency clock at external test facility.On the basis that is input as the quick clock of standard, circuit of the present invention will be modulated quick clock, thereby produce pulse signal acquisition and the multiple-pulse signal acquisition that meets ac sweep test and diagnosis usefulness.
The present invention is directed in the low cost structure testing equipment, the situation that can only provide quick clock that fast data channel can not be provided has proposed a kind of quick signal acquisition and has produced circuit.This circuit and in conjunction with the ac sweep testing process can provide a kind of true speed test and diagnostic process based on sweep test.Utilize this flow process can realize low cost, effectively test.
A kind of high-frequency clock that provides based on low cost test equipment is provided one of the object of the invention, produces the generation circuit of quick signal acquisition.
A kind of high-frequency clock that provides based on frequency multiplication of phase locked loop on the sheet is provided two of the object of the invention, produces the generation circuit of quick signal acquisition.
In order to reduce testing cost, chip will carry out structural design for Measurability, adopts low-cost configuration property testing equipment during test.The design for Measurability that chip will carry out has:
| Circuit under test | Structural design for Measurability |
| Logical circuit | SCAN design AC SCAN test LBIST IDDQ JTAG |
| Memory | MBIST |
| Analog circuit, mixed signal circuit | The built-in self-test technology of the built-in self-test technology phase-locked loop of the analog circuit of high-speed interface |
For reaching above-mentioned order, the invention provides the fast signal that is used for the ac sweep test on a kind of and produce circuit, this circuit is made of a mode counter, No. two selectors, self-locking memory cell and some NAND gate, and it specifically comprises:
A) four inputs: fast clock signal, clock signal at a slow speed, test enable signal testmode, pattern configurations signal;
B) output: quick signal acquisition;
C) mode counter, when mode counter was in configuration status, this mode counter was by clock signal driving at a slow speed, and the pattern configurations signal is as the input of this mode counter, when mode counter was in count status, this mode counter was driven by fast clock signal;
D) one No. two selector is used for the clock that uses according to circuit enable signal preference pattern counter;
E) feedback loop of the mode counter of being made up of two NAND gate, this loop are according to the different value of circuit enable signal, and decision is scan chain feedback or pattern configurations;
F) memory cell of a self-locking, the self-locking memory cell by one or and a memory cell form, be used for according to test enable signal generative circuit enable signal, the circuit enable signal is used to select different clocks and whether determines the feedback loop of gate mode counter;
G) input of one two end and door are used for the combined test enable signal and the mode counter output signal generates quick signal acquisition.
In the such scheme, mode counter is made up of a plurality of memory cell, and this memory cell is register or latch.
In the such scheme, the circuit enable signal links to each other with the feedback loop of No. two selectors and mode counter, and the circuit enable signal is generated by test enable signal testmode, is 0 when testmode is initial, and the circuit enable signal also is 0; When testmode becomes 1 for the first time, the circuit enable signal also becomes 1.
In the such scheme,,, realizes mode counter by being carried out different assignment when needs produce different quick signal acquisition patterns.
Structural testing equipment can be supported design for Measurability that chip is carried out.The sweep test meeting produces a large amount of test vectors, and store these test vectors needs testing equipment that big memory headroom can be provided.And jumbo internal memory can increase the single pass cost of testing equipment, thereby increases the testing cost of chip.The way that addresses this problem is to use the design of shared drive pond, because sweep test is usually operated at lower test frequency, can provide jumbo shared drive pond with general SDRAM or DDRAM.Usually the high-speed internal memory that can be furnished with 16M～64M on each passage when this Out of Memory time spent, can be used shared drive.In the shared drive pond, the memory size of distributing to each passage is variable, and therefore, the visit of the vector in the memory pool is based on the address.Structural testing equipment supports that the requirement of Logic BIST (logic built-in self-test circuit) mainly is that quick clock can be provided, to support the high speed simulation test.Pertinent literature has been used description of test in SOC (system level chip) test, what need high speed test mainly is some analog modules, such as testing for CPU (CPU), numerical portion may not need high speed test, and the parts that need high speed test are interfaces.For the ease of these analog modules are tested, need carry out the built-in self-test design to these analog modules, provide quick clock by testing equipment then, drive built-in self-test and finish test.
Structural testing equipment is if the support ac sweep is tested, and then this testing equipment must can provide quick signal acquisition.The ac sweep testing feature is to adopt displacement at a slow speed, catches fast, to simulate the true speed test.Though the signal acquisition pulse duration is consistent with quick clock fast,, it needs waveform and common quick clock that bigger difference is arranged.Yet low cost structure property testing equipment can not provide the fast data passage in order to reduce the cost on the single passage, and quick clock passage can only be provided.Therefore, the quick clock that directly uses structural testing equipment to provide obviously can not be satisfied the demand.
This paper has proposed a kind of quick clock that low cost structure property testing equipment can be provided and has been modulated into the circuit that satisfies the delay testing desired signal.Like this, can directly utilize low-cost configuration property testing equipment that chip to be measured is carried out the true speed test, reduce the cost of true speed test.
Description of drawings
Fig. 1 is that fast signal produces circuit application in low cost structure property testing testing of equipment environment on the sheet of the present invention, and the high speed test clock is provided by testing equipment.
Fig. 2 is that fast signal produces circuit application in low cost structure property testing testing of equipment environment on the sheet of the present invention, and the high speed test clock is provided by the built-in chip type frequency multiplication of phase locked loop.
Fig. 3 is fast signal generative circuit hardware architecture figure on the sheet of the present invention.
Fig. 4 produces continuous two quick signal acquisition exemplary plot that circuit produces by fast signal on the sheet.
Fig. 5 produces two quick signal acquisition exemplary plot with an interval that circuit produces by fast signal on the sheet.
Embodiment
Fast signal of the present invention produces cooperation such as Fig. 1 of circuit and other signals and circuit, 2 descriptions.If high-frequency clock is provided by structural testing equipment, so its structured flowchart such as accompanying drawing 1 description.If clock is obtained by frequency multiplication of phase locked loop in the chip fast, its structured flowchart is just described as Fig. 2 so.Signal circuit is inserted between input signal and the scan chain.Input signal has four: fast clock signal, clock signal, pattern configurations signal and test enable signal at a slow speed.Output signal is the quick signal acquisition that target produces, and the detailed structure of this generation circuit is seen Fig. 3.As shown in Figure 3, its main body is a mode counter 10.This mode counter is made up of a plurality of memory cell, by a feedback loop execution cycle property counting, when mode counter is in configuration status, this mode counter is by clock signal driving at a slow speed, the pattern configurations signal is as the input of this mode counter, when mode counter was in count status, this counter was driven by fast clock signal.Need to produce different quick signal acquisition patterns, can realize by mode counter is carried out different assignment.No. two selectors 20 are used for selecting the fast clock signal and the clock signal of clock signal drive pattern counter use at a slow speed according to the circuit enable signal.In all sweep tests, need a test enable signal testmode, be used to select scanning mode and function trap state.Need multiplexing this test enable signal in the present invention, as accompanying drawing 3, testmode is as an input of circuit of the present invention, test enable signal testmode also is used for serving as control signal in fast signal generation circuit except the gated sweep chain is in scanning mode or function trap state.
Fast signal of the present invention produces circuit and divides two kinds of mode of operations: configuration mode and count mode.
Also comprise: the feedback loop of the mode counter of being made up of two two input nand gates 30,40, this loop are according to the different value of circuit enable signal, and decision is scan chain feedback or pattern configurations;
The memory cell 60 of a self-locking, the self-locking memory cell by one or and a memory cell form, be used for according to test enable signal generative circuit enable signal, the circuit enable signal is used to select different clocks and whether determines the feedback loop of gate counter;
Input of two ends and door 50 are used for the combined test enable signal and the mode counter output signal generates quick signal acquisition.
As can be seen, the circuit controls signal of No. two selectors 20 and mode counter 10 is the circuit enable signal among the figure among Fig. 3.The circuit enable signal is generated by test enable testmode.Be 0 when testmode is initial, the circuit enable signal also is 0.When testmode becomes 1 for the first time, the circuit enable signal also becomes 1.No matter how testmode changes, according to the characteristic from lock memory, it exports a circuit enable signal will remain 1 later on.
Configuration mode is used for the initialize mode counter, needs the information of configuration to be provided by the pattern configurations pin in the accompanying drawing 3.Under configuration mode, circuit enable signal=0, so clock passes No. two selector drive pattern counters at a slow speed, mode counter is operated in state at a slow speed, at this moment the pattern configurations signal pin can send pattern to mode counter with slower speed.Work as testmode=0, testmode signal gate control NAND gate 40, the output signal of NAND gate 40 is 1, configuration signal can be passed NAND gate 30 smoothly like this, moves into mode counter.Specifically need to move into the mode counter configuration signal as required the fast signal pattern and decide.
Count mode is used to cooperate other signals to produce the target fast signal.Observe accompanying drawing 3, under this pattern, circuit enable signal=1, at this moment mode counter is operated in higher operating frequency under fast clock signal drives.Because configuration signal=1 is so the value of mode counter low order end memory cell can feed back to the memory cell of counter high order end.Thereby count performance period.Therefore, under count mode, fast signal produces circuit not to be needed to import any signal, so do not need extra express passway.
Can draw from top two patterns and corresponding signal value: configuration mode must be carried out before count mode.And after in a single day fast signal generation circuit enters count status, will maintain count status all the time.Yet when actual test and debugging, such constraint is easy to satisfy, and makes troubles therefore can for actual test and debugging.
Mode counter is made up of a plurality of memory cell and a controlled loop constitutes, and this memory cell can be that register also can be a latch.But memory cell and loop constitute the counter of a cycle count.The output of this counter and quick clock and test enable signal testmode cooperate the modulation work of finishing fast signal.
It is exactly reconfigurable property that the fast signal that the present invention proposes produces key property of circuit.Reconfigurable property is meant that the fast signal waveform of generation is not unique, can reshuffle by making fast signal generation circuit be in to finish under the configuration mode according to the needs of test and debugging.Under the initial configuration pattern, the data bit that the pattern configurations signal pin moves into is called pattern-word.By pattern-word is set is different values, can set the pattern of the fast signal pulse of required modulation.
The concrete working method of lucid and lively fast signal generating circuit the several examples of the fast signal that in delay testing, needs:
Delay failure (comprising jump delay failure and path time delay fault) is used the method for testing test of two test vectors usually.Suppose to have two vectors (V1, V2), vectorial V1 is an initialization vector, this vectorial purpose is exactly that the node in the circuit is put an initial value, V2 is second vector that applies, and this vector can be used for causing a saltus step, and the result of saltus step is delivered on original output or the trigger.Concrete method of testing can reference:
“Essentials of Electronic Testing for Digital Memory，and Mixed-Signal VLSICircuits”，Published by M.L.Bushnell and V.D.Agrawal，Kluwer AcademicPublishers，Boston，2000
Structural saltus step fault test technology is divided into two big classes usually: " launch-from-capture " (loading one catches) technology and " launch-from-shift " (loading a displacement) technology.
" launch-from-capture " technology is otherwise known as: " broad-side " (broadcast mode) or " functionaljustification " (function affirmation) technology.This technical testing process is as follows: after first vector moved into scan chain by shooting by scanning input, second vector was applied to response results behind the combinational circuit for first vector.So each test only needs by shooting the motion scan chain once in " launch-from-capture " technology.In the design based on scanning, if scan chain length is N, test process can divide following a few step so:
(1), need N to clap altogether, at this moment test enable signal testmode=0 with data shift-in scan chain.
(2) put test enable position testmode=1.
(3) send two quick signal acquisitions continuously, first signal acquisition is used to apply first vector and produces response results, simultaneously response results is caught in the scan chain, the response that second signal acquisition is used for catching first vector of scan chain is applied to circuit, and catches its response results.
(4) put test enable position testmode=0, the circuit response results is scanned out observation by scan chain.
Wherein (3) step needed the waveform such as the example that Fig. 4 describes of generation.Produce such signal acquisition and need in the mode counter of quick signal acquisition generation circuit, configuration format be the pattern-word of " XX00011000XXX ".In this pattern-word, must guarantee to have two continuous 1, can guarantee to produce two quick signal acquisitions like this.A plurality of if desired (more than two) so need configuration continuously suitable with the signal acquisition number 1.If establishing the length of mode counter is 8, the number of pulses of the fast signal of so needed generation and need a kind of corresponding relation between the pattern-word of configuration can be with reference to following table:
| Numbering | The fast signal pulse that needs | Configurable pattern |
| Quantity | Word | |
| 1 | 2 | 11000000 |
| 3 | 3 | 11100000 |
| 4 | 4 | 11110000 |
| 5 | 5 | 11111000 |
| 6 | 6 | 11111100 |
| 7 | 7 | 11111110 |
| 8 | 8 | 11111111 |
" Launch-from-shift " technical characterstic is that initialization vector and second vector all adopt scan chain to move into.The modulated process of fast signal is similar with " launch-from-capture " in " Launch-from-shift ", does not just do being described in detail here.If any problem, can be with reference to the explanation of front.
If in the ac sweep test process, found mistake, may need the target defective is diagnosed.Diagnosis need be for concrete fault model, bridging fault model be a kind of under deep submicron process more common tracing trouble model.But diagnostic techniques articles of reference: " AC Scan Path Selection for Physical Debugging " based on bridging fault model, Published by Alfred LCrouch, John C.Potter, Jason Doege in the IEEE Design﹠amp; Test of Computers, pp.34-40, September/October 2003 (Vol.20, No.5).
In diagnosis bridging fault process, need to use discontinuous quick signal acquisition.Producing two discontinuous quick signal acquisitions can be by disposing in " 00010 (n) 100 " mode in pattern-word.If the length of mode counter is 8, the following table example produces the middle pattern-word that n interval arranged of two pulse signals:
| Numbering | Space-number n between the adjacent pulse | Configurable pattern-word |
| 1 | 1 | 10100000 |
| 2 | 2 | 10010000 |
| 3 | 3 | 10001000 |
| 4 | 4 | 10000100 |
| 5 | 5 | 10000010 |
| 6 | 6 | 10000001 |
Fig. 5 has provided continuous two quick signal acquisition examples of a midfeather one-period.
Produce if desired a plurality of continuously or the quick signal acquisitions that are interrupted can be similar to the mode of showing and handle.
The length that depends on scan chain of pattern-word length, the length of pattern-word should be factors of the length of scan chain.Therefore in Scan Design, the length that should guarantee scan chain is not a prime number.For the flexibility that takes into account pattern-word and the area overhead of mode counter, the span that is of convenient length of pattern-word is: 4～16.The number of the needed register of the more little then mode counter of pattern-word is just few more, so the area overhead of signal generating circuit is also little, but selectable pattern-word is just few more, that is to say that the signal mode after the modulation in the future is just fewer.The number of the long then needed register of mode counter of pattern-word length is just big more, and area overhead is just bigger like this, but big pattern-word can provide the various modes word select to select, and can take into account different application scenarios.
The quick signal acquisition of Chan Shenging calculates pattern-word as required.With reference to the accompanying drawings 3, the configuration mode of pattern-word is as follows: circuits enable signal=0, at this moment clock passes No. two selectors 20 drive pattern counters 10 at a slow speed, and mode counter is operated in state at a slow speed, and at this moment the pattern configurations signal pin just send pattern with slower speed to mode counter.This moment testmode=0, testmode signal gate NAND gate 40, the output signal of NAND gate 40 is 1, pattern-word just can be passed NAND gate 30 smoothly by the configuration signal pin like this, the immigration mode counter.
The present invention is directed to the quick signal acquisition that needs in the ac sweep test, proposed fast signal generative circuit on the sheet.This circuit can produce the quick signal acquisition of target of modulation according to the input high-frequency clock.High-frequency clock can be directed to the high-frequency clock that low cost structure property testing equipment provides, and also can be the clock behind the chip internal frequency multiplication of phase locked loop.This circuit design is simple, and area overhead is smaller, and all signals that need import are except that high-frequency clock, and other are all imported with low frequency.Because the pattern-word configuration flexibility, make this signal generating circuit can be fit to be applied under test pattern and the diagnostic mode different requirements simultaneously to quick signal acquisition.
Claims (4)
1. be used for the fast signal generation circuit that ac sweep is tested on a sheet, it is characterized in that this circuit is made of a mode counter, No. two selectors, self-locking memory cell and some NAND gate, it specifically comprises:
A) four inputs: fast clock signal, clock signal at a slow speed, test enable signal testmode, pattern configurations signal;
B) output: quick signal acquisition;
C) mode counter, when mode counter was in configuration status, this mode counter was by clock signal driving at a slow speed, and the pattern configurations signal is as the input of this mode counter, when mode counter was in count status, this mode counter was driven by fast clock signal;
D) one No. two selector is used for the clock that uses according to circuit enable signal preference pattern counter;
E) feedback loop of the mode counter of being made up of two NAND gate, this loop are according to the different value of circuit enable signal, and decision is scan chain feedback or pattern configurations;
F) memory cell of a self-locking, the self-locking memory cell by one or and a memory cell form, be used for according to test enable signal generative circuit enable signal, the circuit enable signal is used to select different clocks and whether determines the feedback loop of gate mode counter;
G) input of one two end and door are used for the combined test enable signal and the mode counter output signal generates quick signal acquisition.
2. the fast signal that is used for the ac sweep test on according to claim 1 produces circuit, it is characterized in that mode counter is made up of a plurality of memory cell, and this memory cell is register or latch.
3. the fast signal that is used for the ac sweep test on according to claim 1 produces circuit, it is characterized in that, the circuit enable signal links to each other with the feedback loop of No. two selectors and mode counter, the circuit enable signal is generated by test enable signal testmode, be 0 when testmode is initial, the circuit enable signal also is 0; When testmode becomes 1 for the first time, the circuit enable signal also becomes 1.
4. the fast signal that is used for the ac sweep test on according to claim 1 produces circuit, it is characterized in that, when needs produce different quick signal acquisition patterns, realizes by mode counter is carried out different assignment.
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| US7352170B2 (en) * | 2006-06-13 | 2008-04-01 | International Business Machines Corporation | Exhaustive diagnosis of bridging defects in an integrated circuit including multiple nodes using test vectors and IDDQ measurements |
| US8438433B2 (en) * | 2010-09-21 | 2013-05-07 | Qualcomm Incorporated | Registers with full scan capability |
| US8981815B2 (en) * | 2013-04-01 | 2015-03-17 | Mediatek Singapore Pte. Ltd. | Low power clock gating circuit |
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| CN111624478B (en) * | 2020-06-12 | 2022-12-23 | 山东云海国创云计算装备产业创新中心有限公司 | Clock signal control circuit and equipment |
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| CN1558251A (en) | 2004-12-29 |
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Application publication date: 20041229 Assignee: Zhongke Jianxin (Beijing) Technology Co.,Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: X2022990000752 Denomination of invention: On chip fast signal generator for AC scanning test Granted publication date: 20080305 License type: Exclusive License Record date: 20221009 |
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