CN100370555C

CN100370555C - Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom

Info

Publication number: CN100370555C
Application number: CNB921110634A
Authority: CN
Inventors: S·R·奥夫辛斯基; W·丘巴提; Q·伊; D·A·施特兰德; S·J·赫金斯; J·冈萨雷斯-埃尔南德斯; H·弗里切; S·A·科斯蒂列夫; B·S·赵
Original assignee: Energy Conversion Devices Inc
Current assignee: Energy Conversion Devices Inc
Priority date: 1991-08-19
Filing date: 1992-08-19
Publication date: 2008-02-20
Anticipated expiration: 2007-08-19
Also published as: CN1075377A

Abstract

A solid state, directly overwritable, non volatile, high speed, multibit single cell memory characterized by numerous stable, non volatile detectable configurations of local atomic and/or electronic order, which can be selectively and repeatably accessed by electrical input signals of varying pulse voltage and duration. There is also disclosed a unique class of microcrystalline semiconductor materials which can be modulated, within a crystalline phase, to assume any one of a large dynamic range of different Fermi level position while maintaining a substantially constant band gap over the entire range, even after a modulating field has been removed.

Description

The multidigit memory element

This invention relates generally to a class new can be modulated the semiconductor material that the free charge charge carrier is a feature with high concentration.The working mechanism of the device made from the new semiconductor material of this class is different with the working mechanism of conventional semiconductor device.The semiconductor material new with this class can provide the new device structure with thundering performance rightly.In more detail, the present invention relates to the crystallite semiconductor materials that a class has narrow band gap in fact.Can specialized designs become solid-state, electricity and light is starting, that can directly rewrite, the memory element of utmost point low energy, extremely fast conversion, non-volatile, simulation and multistage single cell operation with this class material; With the high density electricity storage array that constitutes with this class material.

Ovonic EEPROM (two-way erasable programmable read-only memory) is a kind of new, patented, high performance, non-volatile thin film electronics memory part.In this device, information can be with simulation or binary mode (bit in every unit), or stores with polymorphic form (each storage unit has a plurality of bits).The advantage of two-way EEPROM comprises the non-volatile memory of data, the higher bit density potential, its a small amount of substrate printing and the low cost that device architecture brought of simple two links, long programmable cycle life, low program design energy and high-speed, two-way EEPROM can be with scale-of-two and multimode work.Have little difference with structure and material, improve scale-of-two or multi-mode performance characteristic.For the present invention, term " memory element " and " control element " use as synonym.

The work of most of semiconductor devices is that the control of being moved carrier concentration is arranged, and the charge carrier that this migration charge carrier produces during with thermal equilibrium is different.Before the present invention, have only four kinds of known commonsense methods to be used for controlling and modulate the concentration of the excess carrier or the free carrier of solid semiconductor device, (these two terms are exchanged and use) in whole discussion.Below, for understanding advantage of the present invention, being accompanied by general discussion to the basic mechanism of required semiconductor devices work, these four kinds of known methods will obtain explanation.

As an illustration, in the perfect semiconductor lattice of inclusion-free and lattice imperfection-intrinsic semiconductor, when 0 ° of K, owing to be full of electronics in the valence band and conduction band is empty, so there is not charge carrier.Yet, when high temperature, enter conduction band because the valence band electronics, is crossed over band gap by hot activation, and produce electron-hole pair.These thermogenetic electron-hole pairs are to be present in only charge carrier in the intrinsic material.Certainly, because electronics and hole are to produce in pairs, (electron number in every cubic centimetre equals the hole concentration (the hole number in every cubic centimetre) in the valence band to conduction band electron concentration.As everyone knows, but still what be worth emphasizing is if will keep the carrier concentration of stable state, must make the recombination velocity of charge carrier identical with the generation speed of these charge carriers.An electronics in conduction band directly or indirectly by means of centre-recombination center, crack, when moving the empty state (hole) in the bid band more, has just produced compoundly, thereby has buried in oblivion a pair of electron-hole pair.

Outside the charge carrier that heat extraction produces, owing to have a mind to also can in semiconductor material, produce charge carrier with in some impurity importing lattice.This process is mixing, and represented the communication method using common that changes the semiconductor conductance.Can make semiconductor material become electronics by mixing or preponderate in the hole, that is to say, to make semiconductor material become N-type or P-type.When lattice is doped to equilbrium carrier concentration and intrinsic carrier concentration not simultaneously, semiconductor material is called as " extrinsic ", when the impurity of introducing or lattice imperfection enter other not such perfect lattices, in band structure, in band gap, can produce an additional energy level usually.For example, when in silicon or germanium, mixing phosphorus, produce the energy level of a very close conduction band.This new energy level is full of by electronics when 0 ° of K.To only need very little heat energy with these electron excitations to conduction band.Therefore, when 50-100 ° of K, all electronics in the impurity level in fact all have been applied to conduction band.With the doped semiconductor material of donor impurity, in conduction band, can have quite high electron concentration, even when temperature very low, low also is like this to can not measure intrinsic carrier concentration the time.

Now, the reader can find to represent the importance that the excess carrier of conductivity exists.Must be noted that charge carrier also can use photoactivation, they can be injected stride across p-n junction or the Schottky barrier that is added with forward bias.Briefly, no matter excess carrier produces in which way, and they are all arranging the conducting process in the semiconductor material.The front said that the control method of free charge concentration is known four kinds, below these four kinds of methods was illustrated:

(1) in 1948, Bardeen, Brattain and Schochley successfully modulate the minority carrier stream that injects in the bipolar junction-type transistor when they use, and when proving a kind of work of solid amplifier, they have declared the epochal arrival of semiconductor electronics.A kind of device that three exits are arranged in the bipolar junction-type transistor can be controlled the electric current that flows through two exits in the device when wherein the electric current of the 3rd exit has a small amount of variation.This control characteristic can be used for the amplification of small-signal, or makes device convert " disconnection " state to from " connection ".In other words, bipolar transistor is used to modulate the injection and the collection of the minority carrier of crossing over semiconductor junction.In more detail, for example when considering a p-n-p bipolar structure (a kind of work of n-p-n bipolar structure is the simple upset of the work of p-n-p structure), be added with forward bias knot marginal with add marginal identical that reverse bias ties.For this structure, n district, center is injected by p-n junction in the hole provides minority carrier.The hole is as the inverse current that flows through the n-p knot.It should be explicitly made clear at this point now, as the name of " bipolarity " this class device and electronics and the hole extremely important relation that works.

In the work, the reverse saturation current that passes the device p-n junction depends on the minority carrier speed that produces in the near field that bears neighbors.Increase the generation speed of electron-hole pair, might increase inverse current by knot.This can use up and finish (following in the face of photodetector discuss like that).On the electricity, easy hole injector spare is the p-n junction that has added forward bias, and electric current is caused by the injected hole that enters n district material from the p district at first in this device.If add the n limit of knot of positive bias when identical with the n limit of the knot that adds reverse bias, when the hole when p-n junction injects n district, center the inverse current of minority carrier hole as tying by transistor n-p is provided, synthetic p-n-p arrangement works.Certainly, the n-district is very narrow, and therefore, institute's injected holes is not in that (base of this p-n-p bipolar transistor) can be compound in the n district before the depletion layer that diffuses into the knot that is added with reverse biased.

At last, when being used as switch, this transistor is controlled at " connection " and " disconnection " two kinds of conduction states usually.Yet, when being transformed into " connection " state, do not play the short circuit effect, when being transformed into " disconnection " state, do not work the effect of opening circuit, just play approximate this effect.In the transistor switch, emitter junction adds positive bias, and collector junction adds reverse bias, flows out the suitably electric current of size from base stage.If base current is converted to 0, collector current can be ignored.Here it is " disconnection " state.Yet, if base current for just and enough big, device drive becomes state of saturation, transistor enters its " connection " state.Therefore, in typical switch work, base current is negative from just being converted to, thereby driving element ends to be saturated to, and vice versa.

(2) second kind of commonsense method of control free charge concentration realizes with metal-oxide semiconductor fieldeffect transistor (MOSFET) device.Technology as a setting, the most widely used a kind of electron device is actually digital integrated circuit, is metal-insulator semiconductor (MIS) transistor.In a MIS transistor, the carrier concentration in the conducting channel is extremely to go up added voltage by means of the canopy of insulator and raceway groove insulation to control.The device that generates can usually be called as insulation canopy utmost point field effect transistor (IGFET).Yet, since most of IGFET be with metal (being typically aluminium) as the canopy utmost point, silicon dioxide is made insulator, silicon is as semiconductor material formation, so term MOS field effect transistor or MOSFET are general.

In MOSFET work, think that n-type raceway groove is formed on the p-type silicon chip.N-type source and drain region are with foreign atom diffusion or inject slight doped p-type substrate and constitute.The oxide that one deck is thin separates metal canopy and silicon face.If between source and leakage, do not have the n-raceway groove of conduction, do not have electric current from the leakage current to the source, because the combination in leakage-substrate-source comprises the reverse opposed p-n junction of series connection.When adding forward voltage on the grid of relative substrate (being the source in this embodiment), positive charge carrier is deposited on the grid metal.The result of deposit is to be caused inducing negative carrier in bottom silicon by forming of depletion region.In addition, formed and included the thin surface district that moves electronics.The electronics that from the raceway groove of FET, induces allow electric current from leakage current to the source.The effect of canopy voltage is to change to be used for the conductance of low leakage to the raceway groove that is generated of source voltage.The MOS field effect transistor in fact in digital circuit of great use, it becomes " connection " state from " disconnection " state exchange in digital circuit.Two kinds of MOS transistor of n-raceway groove and p-raceway groove are the most frequently used.

The MOS structure can think that a pole plate is semi-conductive capacitor.If add negative voltage between metal and semiconductor, negative charge is deposited on the metal significantly.Be that the clean accumulation of positive charges of equivalent is at semiconductor surface therewith accordingly.Under the situation of p-type substrate, this is to be caused by the hole that is accumulated on semiconductor and the oxide interface.Because added negative voltage the rest potential of metal has been reduced with respect to semiconductor, the electronic energy in the metal is raised with respect to semiconductor.Semiconductor energy gap, the crooked accumulation with the hole adapts at the adjacent interface place.Because there is not electric current to pass through the MOS structure, the invariant position of the Fermi level in semiconductor, consequently, near the so crooked so that valence band of the more close abutment of Fermi level of the semiconductor energy gap at interface, and the hole concentration that makes generation is greater than the hole concentration that is produced by doping in the p-N-type semiconductor N material.

When positive voltage when metal is added to semiconductor, the metal current potential increases, and makes the metal Fermi level be lower than its equilibrium position.Consequently, the conduction band of oxide tilts once more.Positive voltage is the deposit positive charge on metal, correspondingly produces the net negative charge of equivalent on semiconductor surface.Negative charge in these p-section bar material is because exhaust from the contiguous hole of leaving over down the surface region of uncompensated Ionized acceptor impurity, and produce.In depletion region, hole concentration reduces, and being with of contiguous semiconductor surface is curved downwards.If positive charge constantly increases, being with still of semiconductor surface place can be bent downwardly again.In fact, enough big voltage can cause big electron concentration in conduction band.In this case, be close to semiconductor region typical n-section bar material conductive characteristic is arranged.This n-type superficial layer is not what mix to form, but it is by original p-N-type semiconductor N material, because making alive promptly generates its " transoid ", this inversion layer separates the p-section bar material of itself and bottom with depletion region, and it is the key that makes MOS transistor work.

(3) the third known method of control free carrier concentration is the free carrier method of two kinds of polarity of photoproduction.The photoproduction free carrier occurs in barrier-layer cell, and photoresistor, photoelectric detector and photoelectron are taken pictures in these modernized devices of reel.

Usually.When having produced excessive electronics or hole in the semiconductor material, conductivity of electrolyte materials increases.If excessive charge carrier is produced by light stimulus, caused conductivity increase is referred to as " photoconductivity ".When photon directly clashed into semiconductor material, energy was absorbed greater than the photon of band gap, and generated electron hole pair.Electronics and hole that this absorption process produces are excess carriers.Because they and its surrounding environment out of trim, and be present in can be with separately, they just help the material electric conductivity increase.

(4) the 4th kind of known method of free carrier is the physical arrangement of control chalcogenide phase change material in the modulation semiconductor material, because of their pass through reversible by the transformation of amorphous state to crystalline phase.The detailed explanation of this phenomenon was reported, and the research work the earliest of light and electric two-way phase-change material is at first carried out in the energy conversion device by S.R.Ovshinsky.To go through this material and technology below.

Because the present invention has significant science practicality and direct commercial effect in many different field of electronics and semi-conductor industry, below the said invention with three different relevant segments discussion.In more detail, the related content that the present invention discussed relates to: (A) semiconductor devices itself; (B) but phase transition storage optical manipulation, quick, non-volatile; (C) directly that rewrite, the multistage single cell memory of the erasable electricity that goes.

Early stage electric phase transition storage

But electronically written and the erasable phase-change material that goes (and this material can electricity conversion between general amorphous state and general crystalline state, the General Principle that is applied to electronic memory is known and open, for example the patentee who published on September 6th, 1966 is that the United States Patent (USP) 3271591 of Ovshinsky and the patentee of publication on September 22nd, 1970 are the United States Patent (USP) 3530441 of Ovshinsky, these two patents all transfer the assignee identical with the present invention, these two disclosed contents of patent are in the present invention involved, (being called the Ovshinsky patent in the later narration).

Disclosed as the Ovshinsky patent, this phase-change material can be changed between general impalpable structure attitude and general crystallization local order structure attitude, or amorphous state completely and completely the local order in the whole spectral region between the crystalline state recognize do not change between the homomorphism.In other words, the electricity of the disclosed this material of Ovshinsky patent conversion and not requiring appears at completely amorphous state and completely between the crystalline state, and can be the step of increase gradually that changes of amorphous state and the reflection local order in order to " gray scale " to be provided of the repeatedly local order sign of the whole spectrum between the crystalline state completely completely.Also only between general amorphous state structure and general crystallization local order structure attitude, change by the early stage material of Ovshinsky patent disclosure, to adapt to the storage and the recovery of encoded binary situation.

The phase transition storage that the electricity of Ovshinsky patent disclosure can be wiped has significant commercial practicality.But, since it can not satisfy on the business development with the follow-up developments needs of solid electronic storer at other field, thereby the phase change technique that early stage electricity can be wiped finally is substituted on market, and stops these storeies to be used for electric device resemble the personal computer.

In the typical personal computer, four row storeies are arranged usually.Database information is stored in picture tape and this cheap, slow, big device storage capacity, non-volatile of floppy disk.This information transfers to faster on demand, more expensive but still be in the non-volatile harddisk memory.That information is transferred to from hard disk successively is still more expensive, faster, use semiconductor dynamically in the easy mistake system storage of (random access memory) RAM (DRAM).The sub-fraction that very fast computing machine will be stored in the information among the DRAM is transferred to also to and fro will faster more expensive easy mistake static RAM (SRAM) (random access memory) (SRAM) in the device, like this, microprocessor just can not need the time and make speed slack-off because of detect data from slower DRAM.Transinformation has taken some power supplys in the middle of the computing machine in the memory column of hierarchy of memory, and this " additionally " need make performance descend and make Computer Architecture complicated.Yet, the generally use of hierarchy, the price of the memory device that is suitable for and Effect on Performance require to have best computing power and minimum price are arranged.

The disclosed erasable phase transition storage that goes equally with subsequently electric solid-state memory is subjected to a lot of restrictions in the Ovshinsky patent, this just hinders it to be widely used for replacing directly and all sidedly the storer that uses in the existing computing machine, for example tape, floppy disk, hard disk drive magnetic or light, the instantaneous memory of solid disc type (solid state disk flash), DRAM, SRAM and plug-in type volatile storage.Specifically, the most significant restriction in these restrictions is expressed as follows: (i) quite slow electric slewing rate (by act.std), the particularly slewing rate under bigger local order situation slow (just in the direction internal conversion that increases crystallization); (ii) begin to detect the variation in the local order district, need quite high intake; The cost of (iii) every megabyte (megabyte) canned data quite high (particularly comparing) with existing hard disk drive medium.

The most tangible restriction in these restrictions is with the variation that detects bonding structure chemistry and/or electronics in the chalcogenide materials, when detecting the variation in the local order district, to need the quite high energy of input.Also be tangible restrictive condition the switching time of the disclosed electric storage medium of Ovshinsky patent, and these materials typically need the time in several milliseconds of scopes aspect setting-up time (making material be converted to the required time of crystalline state from amorphous state).For setting-up time (making material turn back to the required time of no form), need the time of approximate microsecond from crystalline state.Change the required electric energy of these materials, measured representative value is greatly in little joule of scope.

It should be noted the energy of each memory element in the solid matrix that the size of energy, this energy be meant that the row and column that is input to memory cell forms.Cell isolation/address device of importing this high-energy in the high electrical current carriers and be address line and being tied with each discrete storage elements is required.Consider this energy requirement, the those of ordinary skill of the industry, when the selection memory cell isolation elements, all should be limited to very large monocrystalline diode or transistor isolation device, this just must use the height encapsulation high density of also inaccessible micron order offset printing now and memory component.Therefore the low bit density made from this material of matrix must cause the expensive of the every megabyte information of storage.

In order to shorten database effectively, non-volatile mass storage and fast, easily lose the gap on price and performance between the system storage, memory component of the present invention can be set up a kind of new, stepless " universal memory system ".The most essential problem of the storer in the system be can provide cost low with the fast data storehouse.Compare with original Ovshinsky type phase transformation electrical storage, storage material disclosed in this invention can provide fast six orders of magnitude of time of programming above (being lower than 30 nanoseconds), with extremely low program design energy (being lower than 50 picojoules), and proof has the storer of long-time stability and cyclicity (cycle index is above 2,000 ten thousand times).Experimental result shows, because component size reduces to increase slewing rate and cycle life.

In general, the not developed and optimization of chalcogenide storage material class by the identical speed of other class solid electrical storage, other storer has switching time and the lower in fact set and the energy that resets in fact faster at present.These other forms of memory application most typical in some storer is that each memory bits will be used several solid microelectronic circuit components (will use 3 or 4 transistors as every bit).At those solid-state memories, as original " non--Yi loses " memory element among the EEPROM is the canopy FET device that typically floats, its reprogrammable designed capacity is limited, and it is extremely gone up the canopy that electric charge is fixed on field effect transistor, stores each memory bits.Because this electric charge was missed along with the past of time, the storage of information is not real non-volatile, and in the element made from existing phase change medium, is to come canned data by the actual atomic structure of chalcogenide materials or the variation of electronic structure.Other forms of storer also is subjected to some restriction now on market.

Compare with SRAM volatile storage device and for example unsteady booth structure of similar " instantaneous " device with DRAM, electrical storage device of the present invention does not need FET device.In fact, the memory component that can directly rewrite that electricity of the present invention can be wiped is the simplest electrical storage device on making, include only two with film chalcogenide materials monomer and the electric connection that is connected as the semiconductor diode of isolation.Consequently, require a very little monolithic " true district " to store a bit information, this just provides a kind of intrinsic high density memory ics.In addition, as described below, by in each separate memory unit, using many bit storage, the subsidiary work of having finished the increase information density.

At present the cost of the solid electronic storer that uses is quite high, and the price of every bit storage ability is typically the twice of every bit storage information price in disk.On the other hand, this solid electronic storer has some advantage that surpasses magnetic disk memory, their no moving-members, and work institute energy requirement limit is little, is easy to transportation and storage, and very easy mistake is applicable to portable computer and other portable electron devices.In fact, manufacturer's advance notice in the portable computer field, uses more and more littler hard drives and the final solid-state memory that uses to store, and is expected to increase sharply.In addition, the random access system that this solid-state memory is normally real needs actual mobile coiled hair to the dish-type storage system of correct data track with the memory location that is received in defined and be different from.Yet although they have these advantages, the higher price that the solid electricity can be wiped storer hinders it to enter the principal market that is occupied by magnetic memory systems now.Although it is potential aspect the reduction cost that the solid electricity can be wiped storer, the overall performance index of these materials is not enough so that they replace disk system fully.

We have said the front to have only four kinds of known semiconductor devices, the concentration that can be used for modulating free charge.And in these devices each gone through.To go through with quite low energy pulse now, make the 5th kind of semiconductor devices can be set in a plurality of different resistance values, and quickish conversion characteristic is arranged.Carefully study performance characteristic and physical process after the device work of following several sections explanations carefully, the reader can understand why it is not returned in the 5th kind of concentration of electric charges modulation semiconductor devices.

The storage component part of exploitation is metal-amorphous silicon-metal (MSM) electrical storage switch recently.See Rose, et al, " Amorphous Silicon Analogue MemoryDevices ", Journal of Non-Crystalline Solids, 115 (1989) .pp.168-170 and Hajto, et al, " Quantized Electron Transport inAmorphous-Silicon Memory Struotures ", Physical Review Letters, Vol.66, No.14, April 8,1991, pp.1918-1921.This MSM switch is that the metallization contact will be especially selected is deposited on arbitrary limit of P-type amorphous silicon (a-Si) film and makes.The importance that the metallization contactor material is selected will be discussed in the back.Disclosed MSM storage switch when potential pulse is 1 to 5 volt, has the quite analog-converted characteristic of fast (10-100ns).When provide the resistance value scope to it from about 10 ³To about 10 ⁶Ohm resistance the time, it can be set with non-volatile manner.For industry technician, although the electric conversion properties that people's such as people such as Rose and Hajto MSM storer has (is the time, energy and total device resistance) be similar to the electric conversion properties of memory element of the present invention, but have the substantive difference in the work between the two.

The most tangible electricity conversion difference is that the MSM storage switch can not directly rewrite.That is to say that the MSM switch is at first under the electricity situation about wiping, another resistance value in can not be from the arbitrary resistance value in the analog electrical resistance scope to this Standard resistance range, directly two-way modulation (being set to a specific starting resistance value or " rising dynamically ").Specifically, must at first set high-resistance state (wiping) before MSM switch another resistance value in said shape set analog electrical resistance scope, compare with it, need not wipe before memory component of the present invention another resistance value in setting analog electrical resistance scope; That is to say that they can directly rewrite.

Being present in people's such as people such as Rose and Hajto MSM storage switch and other marked difference of the electric conversion properties between the electrical storage element of the present invention is the bipolarity of said switch.Must wipe with the Pulse Electric opposite as the disclosed MSM switch of people such as Rose with writing pulse polarity.Obviously, no matter memory component of the present invention is used for digital conversion or analog-converted, and memory component of the present invention does not need the opposite pulse of additive polarity.

The electric conversion properties difference that exists between MSM switch and the memory component of the present invention mainly is the difference in order to the material existence of composed component.This difference is the switching mechanism fundamental difference that to show with two kinds of device work physical processes be feature.As that point out above and disclosed in described article, the electric conversion properties of MSM storage switch depends on the special metal material that is used for making contact fully.This is that metal enters switch body from least one contact in this process because need a very high high energy " formation " process in these MSM switches, and forms the bound fraction of switch body.In this process, increase to 300ns and 5-15 deep-sited pulse gradually by a plurality of (having 15 at least among Fig. 1 of people's article such as Rose) and dash and constitute switch.People such as Rose say: " device has been done X-ray micro-analysis research, the top electrode material is embedded in the wire district of a-Si (amorphous silicon).Suppose that top metal is dispersed in the wire district, and in switching mechanism, work ... "; people such as Rose are also concrete to be found, the variation range of equivalent resistance, by the metal decision that constitutes the top electrode contact; say as people such as Rose: " ... have been found that, its value depends on top contact (SiC) fully, and irrelevant fully with bottom metalization (SiC), that is to say, vanadium (V) top electrode device is always analog always the top electrode device is digital for chromium (Cr), and no matter its hearth electrode ... ".

The electricity conversion occurs in this metallization wire district; Do not have a large amount of metals to move among the a-Si and just do not have conversion, see people's such as Hajto article.Opposite fully with it, that memory component of the present invention does not need contact material to move to obtain in the thin-film memory element into is high-speed, low-yield, simulation, the storer conversion that directly rewrites.In fact, in memory device of the present invention is made, must prevent that metal from advancing in the active chalcogenide materials with arbitrary electrode diffusion.Among the embodiment of device of the present invention, each all is double-decker for the electrode of making, and for example, constitutes a film barrier layer with carbon, prevent, and molybdenum for example, diffusion or migration are advanced in the chalcogenide transition material.

Clearly show from people's such as people such as Rose and Hajto analysis, the MSM storage switch is seen as the modulator of free charge concentration, the alike power of not extending undeservedly.And the MSM storage switch in order to obtain resistance range, relies on simply and sets up the wire metalized vias of passing amorphous silicon material, and its method comes the method for Control current identical with using modulation switch.The diameter of the permeation pathway of having set up can increase also and can reduce, to change its resistivity.In transfer process, fermi level position is motionless.The activation of semiconductor material is constant, so that explain this action.Moving of atom level do not take place in the electron pair of independent nonbonding.Its crystallite dimension and surface are inessential with the ratio of volume.But the most important thing is that people such as people such as Rose and Hajto can not directly rewrite the information that is stored in the unit of being made by their storage material.The MSM switch required to wipe institute's canned data before writing new information.Can be not surprisingly, people such as Rose assert, their MSM conversion is limited in 1,000,000 times, and before memory component of the present invention in the end tested, conversion times was not being damaged more than 2,000 ten thousand times.

In brief, before the present invention, develop a kind of solid-state memory system, must consider that the material of this solid storage system of preparation has low price, make easily, non-volatile, can electronically written and with hang down intake directly wipe (rewriting), in single unit (gray scale is arranged), have many bit storage ability with can be with the characteristic of high-density packages very.Accumulator system described below because overcome whole defectives of existing accumulator system, will provide the general substitute of the computer memory that can be widely used as all general on market models immediately.In addition, because storer of the present invention can be made the three-dimensional matrice of full film shape, it just can be used at a high speed, high density mentally network and artificial intelligence system.Accumulator system of the present invention is unique accumulator system that can be applied to mentally network and artificial intelligence system, because the three-dimensional matrice of its multilayer makes a large amount of information stores energy immediate addressings, therefore allows to learn from canned data.

Above discussion list is understood the quantitative change size and the energy requirement of the slewing rate of storer of the present invention, compares with the phase transition storage of prior art, proves that these storeies have established the brand-new semiconductor material modulated of a class.In addition, prior art is not similar to the direct rewriting of memory component of the present invention, characteristics such as wide dynamic range and many bit storage ability.And the work of semiconductor material of the present invention only occurs in crystalline state, and this and all existing dependence crystalline phases are to the amorphous phase conversion or rely on the work of the electric memory element that constantly powers up the stream amplification field different greatly.And the reason that causes these difference is the result that following method produces, and this method particularly by means of electric field, can not only be modulated the concentration of free charge, in fact, remove electric field after, the free charge concentration that this device was modulated remains unchanged.The 5th kind of free charge concentration in this feature representative modulation semiconductor devices and be new mechanism in essence, and might occur various newly and simply change and amplifying technique, this technology can be impacted semi-conductor industry significantly.

The those of ordinary skill of the industry is very clear, find the market of instantaneous EEPROM, must be in earnest it as general-purpose storage, its essence is that memory element really is non-volatile.If memory element requires to have many bit storage ability, this requirement is just more obvious.Lose if set resistance, even obviously drift occurs in the whole time, the information that is stored in the inside disappears, and the user loses confidence to the database capability of storer, technically loses whole credibilities.Any drift in time all can not be permitted appearance how for a short time, and the emphasis of following work is the new memory component of this class of exploitation.Because other compounds of exploitation will realize improving performances such as slewing rate, energy subsequently, also best stability will be arranged simultaneously.

Except setting resistance stability, other most important parameters that general-purpose storage requires are low switching currents.When EEPROM was used as the large-scale data storehouse memorizer, these required just remarkable especially.When using in such a way, EEPROM will replace the hard drives (as hard drives magnetic or light) of the machinery in the existing computer system.With the one of the main reasons of the general mechanical hard drives of EEPROM " hard drives " replacement, be the bigger power consumption that will reduce mechanical system.Be that mechanical hard disk drive is maximum power consumpting device in this class computing machine in above-knee (lap-top) computing machine to this interested true cause.Therefore, reduce this power termination and have special advantage, thus, show a considerable increase the service time of the each charging of computer power supply battery.If EEPROM replace having the machinery of big switching current requirement hard drives (with therefore and the high power that proposes require), conserver power source may be inessential, perhaps is not main at most.Thereby any EEPROM all is considered to the general-purpose storage of the low switching current of requirement.

Other requirements of EEPROM common store element are the long cycle life that writes/wipe.For all archival memories, the cycle life of EEPROM, can obtain consumer confidence and accepted by the consumer aspect play an important role.If storage component part cycle life is too short, the consumer is afraid of to lose valuable data and opposes to use this device.If with the primary memory or the display-memory of EEPROM substituting for computer, that is to say to replace DRAM or SRAM that so, long circulation life requires just to seem more important.Primary memory and display-memory are the most normal writing in the computing machine/the wipe places of data storage.The new computer program of at every turn packing into, the primary memory of computing machine all will be wiped and be rewritten.In Computer Program Implementation Process, computer primary memory circulates partially stabilizedly.Just there is the display-memory circulation of part each display part that changes computing machine.If be used for the EEPROM of substituting for computer primary memory and display-memory not long write/wipe cycle life, these storeies need be replaced with regard to the utmost point so.This is with regard to the too much expense that causes the consumer and lose consumer's trust.

The invention discloses a kind of new solid that comes down to, that can directly rewrite, electronics, non-volatile, highdensity, at a low price, that make easily, reduced the single cell memory element that switching current data that require, that stored have higher thermal stability.These memory components, distinctive with a class, obviously reducing under the energy situation, the chalcogen storage material of the fast order of magnitude of slewing rate is made.Memory component of the present invention and matrix are to use the new memory material to make, and as feature, particularly have stable, real non-volatile, by the pulse voltage, electric current and the pulse width that change input signal, can optionally, repeatedly set up the feature of detectable local atom and/or electronics ordered structure.Storage component part of the present invention is changed in the different atom that can be in the monocrystalline attitude and/or the local order structure of electronics, so that at least two stable setting attitudes to be provided.Use memory component disclosed by the invention, might make slewing rate and switching energy improve an order of magnitude, in fact this improvement is not only to improve gradually, and original beyond thought improvement can occur.

And to storage medium disclosed herein, the theoretical research of doing at present, also not having a kind of theory to think can the viewed distinctive electric conversion properties of best explain.Particularly, the semiconductor material of being studied can be changed between the intake that with nanosecond (ns) is the cycle is many electro-detection conditions of little joule.The semiconductor material of being studied almost is real non-volatile, and can indefinite circulation (write and rewrite), and periodic refresh signal and make the information that is stored in the memory cell keep it complete.The storage material of being studied can directly be rewritten, so change canned data in the memory element assigned address, need not wipe the information (as ferroelectric storage system and other instantaneous storage systems of needs) that is stored in other memory elements.

Among first embodiment of the present invention, disclose a kind of can be electricity conversion, that directly rewrite, many bits, single cell memory element, it comprises determines the required a large amount of storage materials of single cell memory.The feature of storage material is that resistance value has a big variable range, in a plurality of resistance values in said resistance variable range, responds the input signal of selecting, and sets one of them resistance value, has the single unit that many bits are deposited storer so that provide.The a pair of contact that separates each other is set, described input signal is provided, described storage medium is set to the resistance value of a selection, this resistance is in variable Standard resistance range, by means of selecting electric signal, set the arbitrary resistance value in the described variable resistor scope, no matter original resistance of described material, the single unit of storage medium just is set.

Among second embodiment of the present invention, description be a kind of electric operational store matrix of that can directly rewrite, multistage, single cell memory element.This matrix comprises a substrate and direct rewriting, the multistage list-cell memory element of many electric excitations of separating each other at on-chip many row and columns.Each memory element all has spacer assembly, with it element and all the other elements electricity is isolated.Each single cell memory element is determined with many storage materials.Storage material has the fermi level position that energy can be modulated, and said fermi level position is can modulating on a large scale resistance value whole and to keep substantially invariable optical band gap be feature.The feature of material is to respond selected electrical input signal, set one of them resistance value in the many resistance values in the variable Standard resistance range, so that the unit with multistage memory capacity is provided.Each memory element also comprises a pair of contact that separates each other, in order to an electrical input signal to be provided.Make said storage material set resistance value selected in the resistance value variable range, make contact be used as the exit of from memory element, reading and writing.With said selected electric signal, set any resistance value in the said resistance value variable range, and after setting signal is removed, make said material can remain on said setting value, the single unit of storage medium is set.With the arrangements of electric connection of address wire work, also as each separate memory selection of components ground and the device of setting and read resistance value respectively with many storage materials and spacer assembly.

In the 3rd embodiment of the present invention, the modulator approach of the fermi level position of crystallite semiconductor materials is disclosed, from by Se, Te, Ge, Sb, Bi, Pb, Sn, As, S, Si selects material in one group of material of P.O and composition thereof or alloy composition, makes its relative band edge from semiconductor material enter any one position many metastable states detection position.The feature of material is, have one with the variation range of the corresponding different substantially conductivity of fermi level position and whole on a large scale in stable basically optical band gap.The step that this method comprises has: the monomer of carrying an alloy of chalkogenide material; Add an electric signal and make its fermi level position be modulated to selected position, thus the given conductivity value of acquisition in the conductivity variable range; Remove the electric energy that is added on the material, the fermi level position of material remains on selected position substantially, realizes modulation.

In the 4th most preferred embodiment of the present invention, disclose the modulator approach of conductivity of the multiple elemental composition of crystallite semiconductor materials, the component of composition intercouples and forms the lattice structure of decision material grains.Method with at least a constituent atoms in the composition component exists or lacks changes the free charge concentration that is constituted, and realizes modulation.The step that this method comprises has: provide a kind of crystallite semiconductor materials composition that contains many crystal grain parts, the lattice structure decision crystal grain that mixes atom of every kind of component of composition; Add electric signal to material, give a kind of component that adds or remove composition in the lattice structure, its charge carrier that constitutes is increased or reduce, the value of the free charge concentration decision that material electric conductivity is modulated to constitute by said at least a component; And the new conductivity value after keeping (a) by the free charge concentration of adding energy decision and (b) added electric signal being removed on said material.

Among the 5th embodiment of the present invention, disclose a kind of electricity operation, direct rewrite, multistage, single cell memory element, it comprises the mass storage material of determining single cell memory.Memory element comprises a pair of electric contact that separates, and the mass storage material is arranged between the contact.Contact is as reading and write the exit that is stored in the information in the said memory element.Memory element also comprises and adds said electrical input signal, is the device of selected resistance value with the resistance value of setting said material.The mass storage material is to be made of many constituent atoms elements, and they are selected from by Te, Ge, and Sb, Bi, Pb, Sn, As, S, Si, P, the material group of O and composition thereof or alloy composition, every kind of element is all over being stored in the whole storage material.The mass storage material comprises the means of the set of locations compound that is used to change said high capacity storage medium, makes it can reduce resistance value significantly with selected resistance value drift.The feature of this storage material is, a big variable resistance scope is arranged, and no matter the original resistance value of said storage material, and can set the resistance value of this material, be one in the many resistance values in the resistance value variable range, be added to the selected electrical input signal of the said single unit of multistage storage capacity with response.After input signal was removed, storage material remained on the resistance value that sets and does not drift about.By means of forming a large amount of storage mediums gradient, layering and that have gradient/layering to synthesize are arranged on the structure, and change a large amount of storage mediums that reduce resistance because of drift by means of alternate manner, can realize the said method of the described a large amount of storage medium positional structures of change.Certainly, in a sense, this has also finished and has been used to change band gap, changes dot matrix stress or other forms of change electronics, comprises the atom of unshared electron pair or the method for movement of electrons.

Among the 6th embodiment of the present invention, disclose that can directly rewrite, the single cell memory element that comprise the mass storage material, memory component comprises a pair of contact that separates each other, and the mass storage material is arranged between the contact.Contact comprises in abutting connection with the silicon membrane layer of mass storage deposition of materials, is stored in the exit that the information in the memory element is used as reading and writing.Memory element also comprises the device that is used to provide electrical input signal, in order to set said high capacity storage medium to selected resistance value.The mass storage material is with many Se of comprising, the constituent atoms element of the chalcogen of Te and composition thereof or alloy constitutes, it is characterized in that, at least two resistance values that can measure are arranged, with have no matter the original resistance value of said storage material, and set one of resistance value that can detect, to respond the ability of selected input signal.After input signal was removed, storage material remained on selected resistance value and does not drift about.

Below in conjunction with accompanying drawing other embodiment of the present invention, feature and advantage and goal of the invention are described in detail.

Fig. 1 is the part sectioned view of an integrated circuit part, and said circuit has been described wiping and the direct multi-level store structure that rewrites by electricity of first embodiment of the present invention:

Fig. 2 is the part sectioned view of an integrated circuit part, and what said circuit had been described second embodiment of the present invention can electricity that wipe and multi-level store structure that can directly rewrite;

Fig. 3 is the top graph of a part of the integrated circuit of brief description Fig. 1 and Fig. 2.

Fig. 4 is explanation and the circuit theory diagrams of the part of the X-Y matrix of the combined isolated component of an integrated circuit illustrated in figures 1 and 2 part;

Fig. 5 is the single crystal semiconductor substrate schematic diagram logical with the integrated circuit (IC) chip Electricity Federation of having address/drivers/decoders that explanation has of the present invention integrated memory matrix illustrated in figures 1 and 2;

Fig. 6 is the curve map of the multistage storage capacity of explanation single memory cell of the present invention, and the resistance value of device is an ordinate, and signal pulse voltage is horizontal ordinate;

Fig. 7 selects the electric property of of the present invention new semiconductor material of amorphous materials and different crystalline phase materials and the data contrast table of optical property for use:

Fig. 8 is a ternary phase diagram of making the Ge:Sb:Te alloy that memory component of the present invention uses, and said phasor demonstrates heterogeneous, and the various potpourris of these elements are owing to rapid solidification separates in the phasor;

Fig. 9 is the curve map of the cycle life data of improved memory component of the present invention, and what in fact draw is the stable setting resistance value relevant with the circulation course, and ordinate is a resistance value among the figure, and horizontal ordinate is not decide pulse voltage;

The atomic structure layering that Figure 10 has drawn Ge-Sb-Te ternary alloy system shown in Figure 7, and the Ge-Te binary atomic structure of illustrative system anisotropic structure;

Figure 11 a, 11b provide device resistance value (kilo-ohm to be unit) respectively as setting pulse height (is unit with m A), pulse rise time, the three-dimensional curve diagram of the funtcional relationship of pulse fall time or pulse width (is unit with nsec);

Figure 12 a and 12b reduce through the memory component that component changes and do not change through component to set the curve map that resistance value is drifted about, and ordinate is a resistance value among the figure, and horizontal ordinate is elapsed time (starting to set memory component):

Figure 13 comprises chemical composition to be (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Ni ₅Se ₅Jumbo storage material, and the resistance value of the memory element of the present invention that structure does not change and the curve map of writing/wipe cycle index, ordinate is the resistance value of device among the figure, horizontal ordinate is to write/wipe cycle index; With

Figure 14 comprises chemical composition to be (Te ₅₀Ge ₂₂Sb ₂₂) ₉₀Ni ₅Se ₅The resistance value of the memory component of the present invention that jumbo storage material, structure improve to some extent and the graph of relation of writing/wipe cycle index; Ordinate is the resistance value of device among the figure, and horizontal ordinate is for writing/wipe cycle index.

With the erasable storer that goes that various chalcogenide materials are made, certain the class atom in the material moves, and makes material the phase transformation of crystal occur being transformed into by amorphous state, causes the respective change of material structure.For example, by the germanium (Ge) that contains 80% to 85% single (Te) and about 15% and a small amount of other elements, every kind of element is about 1%-2%, for example sulphur (S) and arsenic (As) constitute, the chalcogen alloy of can electricity changing of more orderly or crystalline state, and its characteristic feature is, but in the switch micropore of material, formed the crystal formation Te slice that high electricity is led, the typical component of existing this class material is, for example, and Te ₈₁Ge ₁₅S ₂As ₂Or Te ₈₁Ge ₁₅S ₂Sb ₂Because the high conduction of Te in its crystalline state, therefore, in more orderly or crystalline state, can set up minimum resistance value condition by the Te slice; The micropore resistance value of ordered state that its resistance value is lower or amorphous state is hanged down an order of magnitude.

Yet, form the conduction Te slice in the crystalline state, require the Te atom to become the atomic structure of the localized concentrations the crystallization Te slice from the Te atomic structure of amorphous state.Equally, when chalcogenide fine strip shape material was changed back amorphous state, the Te precipitation that requires to enter into the crystallization slice came out, and the localized concentrations structure in material from slice is moved back to the atomic structure in its amorphous state.This between amorphous state and crystalline state atomic migration, spread or rearrange, every kind of situation has all required the sufficiently long maintenance or the residence time, this just makes required switching time and energy quite high.

The inventor disclose now a kind of based on a class new at the chalcogenide semiconductor material, can reduce obviously that fundamental difference type erasable of required switching time and intake go, directly the storer of Chong Xieing.In addition, chalcogenide materials of the present invention is based on a kind of new physics process in essence, although to the also insufficient understanding of this new physics work, make the wide variable stable state scope internal conversion of material in given crystallization lattice structure, or in different crystalline states, change, and when significant fast slewing rate, having obvious low energy input, disclosed this class new material can be used to make the electronic storage element that has improved.In the work, the basis of this new material is to produce very highly, non-volatile, and band gap width can change, the semiconductor material that the free charge concentration in the narrow band gap can be modulated.This material is with general amorphous different with crystallization shape material, and wherein, crystal may be with similar than disordered state, the conductivity of influence conversion seriously.

Particularly, storage material of the present invention can be in the time cycle of nanosecond (ns), (minimum slewing rate and required least energy are not also found out with conversion in the electro-detection condition of little joule of intake change resistance value, experimental data among the application shows, electrical storage of the present invention can be 1 nanosecond of short like this pulsed modulation with the program design pulse, although be not best).This storage material is non-volatile, can make that (in error range) canned data is kept perfectly and need not to periodically update signal in the storage unit.Compare with semiconductor material with many other semiconductor materials of storer special use, semiconductor material of the present invention and material system can directly rewrite, separate memory for a change is stored in information there, to such an extent as to need not wiped the information (setting a starting point) that is stored in the storer.Be transformed into the very quick and low-energy characteristic that any one resistance value has, in the time of should taking place owing to said conversion, transition material does not need significantly whole atoms to rearrange.We often are understood as storage material and have the crystallite phase, and experimental data also proves, there is dependence in the grain size of crystallite semiconductor materials and material is presented between the ability of other stable states according to added low energy signal rapidly.

Though, the special case of semiconductor material, particularly suitable storer described below, but memory component of the present invention is to make with any substrate of following semiconductor material, this material is to move with respect to band edge by means of fermi level position, satisfies the modulation of free charge.In fact, disclosed recently semiconductor material is used for electrical storage will cause high speed, low energy, directly rewrite the performance of work.Storage material forms with many constituent atoms elements, and every kind of Suo Douneng of atom unit passes the whole volume of material.The various ingredients atomic element preferably includes at least a chalcogen, and also can comprise at least a transition metal.Term " transition metal " element of usefulness here comprises 21 to 30,39 to 48,57 and 72 to 80 atom sequence number element.Be preferably, the many constituent atoms elements that constitute the mass storage material are from Te, Se, and Ge, Sb, Bi, Pb, Sn, As, S, Si, P selects in one group of material of O and composition thereof or alloy composition.Transition metal comprises Cr preferably, Fe, Ni and alloy mixture thereof.Chalcogen comprises Te and Se.Get over preferably Ni of metal.The system example of these a plurality of elements described below is Ni and/or Se to be arranged or do not have Ni and/or the Te:Ge:Sb of Se system.

As known to the those of ordinary skill of the industry, the chalcogenide semiconductor material, similarly other semiconductors are with forbidden band energy level district or isolate its conduction band and the band gap of valence band is (the seeing the mobile band gap of the chalcogenide semiconductor material that " Cohen; Fritzsche, Ovshinsky model " described) of feature.Fermi level position, promptly the energy level occupation rate is 50% the conductivity that can partly determine semiconductor material with the position, when it moves to different basically position in the band gap, the big variable range of conductivity just might occur.But, original supposition is theoretical can not be explained and change fermi level position and set memory component required extremely low-yield of set-point, the various results that figure out below can not explaining, in fact, the intermediate value of resistance can significantly move at both direction, (according to the given electric signal of being imported, to bigger, vice versa from less for resistance value) and do not get back to and require said initial " initial state " of only in single moving direction, working.(from big resistance value to small resistance value).Here it is, and why we say that semiconductor material of the present invention is the real reason that directly rewrites.No matter what is done and explain that element provided by the invention has the valuable electric conversion properties that never occurred in the single memory element with existing mode.It must be noted that experiment conclusion proves, is studied so far, the hole conduction of chalcogenide composition, when as multi-stage data storage work, input signal can move on to valence band edge from middle interstitial site with fermi level position, even enters valence band more deeply.In fact, seem that variable range appears at valence band.

Essential difference between amorphous solid and its corresponding crystal is the constituent atoms selectivity bonding of amorphous phase.This is the necessary condition of amorphism solid.It is because crystallization symmetry regulation dot matrix, limits again successively that the selection of chemical bonding causes.The complete characteristic that amorphous solid has, its cohesive energy, its crystallization resistance, its light belt gap, its mobile band gap, its density of electronic states or the like all depends on three factors, promptly, its short scope bonding relation, its various topological structures and its total interactional environment.Yet amorphous materials can be with non-equilibrium combination, is made up of many dissimilar atoms, that various local orders are provided and alloys various non-stoichiometrics around thing.The bulky grain of the semiconductor material of the present invention that crystallization constitutes is very little, and the main length of the particle that obtains with experimental technique is at the order of magnitude of 500 .These crystal grain are surrounded by the material epidermis of structural disorder or surface region, and perhaps it have only several atomic monolayers thick.Therefore, amorphous model or be to be the model of feature with short distance local order only at least is used to confirm the interaction in surface region of atom and molecule, may be best application.The descriptive model that will illustrate is not limited below.

Make the used special semiconducting alloy of memory device, comprise celebrated chalcogenide element with the existence of " lonely to " electronics.This just must discuss the influence of these lone pair electrons in useful chemical bonding structure.Briefly, lone pair electrons are the electron pairs that typically can not carry out in the valence electron layer of bonding.This lone pair electrons structurally and chemically all important.They are with to the contiguous electron pair that enters in the bonding structure, and the extremely strong repulsive force of other lone pair electrons, influence the shape of molecule and crystallization lattice structure.Because second nucleus does not pin down lone pair electrons and enters bonding region, so its influences and help the migration of low-energy electron.Point out at first that as Ovshinsky lone pair electrons can have 1 and 3 center keies; As Kastner, Adler Fritsche confirms that they have valence electron to alternate to (valance alternationpairs).

Particularly, these several described tellurium alloys have the valence band that the lone pair electrons attitude constitutes.Because four P layer electronics of existence among the Te (tellurium), the Te atom is synthetic with two chemical bonds in these linkage electrons, and two outer-shell electrons (lone pair electrons) therefore later can not make the atomic energy of system that essential change is arranged as the bonding purpose in addition.In this, notice that the highest filling molecular orbit is the track that contains lone pair electrons.This obviously be because, tellurium and germanium atom improve in the stoichiometric proportion crystallization, some internal stresss occur owing to form in the dot matrix of crystal grain, valence band is broadened, and moves to the Fermi level position.Yet yes in the TeGe crystallization " self-compensating ", in other words, supposes and contain more Te component (Te52% Ge48%) can make crystallization more perfect.Crystal by stoichiometric proportion is a face-centered cubic lattice, yet with increasing small amount of energy, count in the Ge and/or the Sb space that increase it, and crystallization presents the rhombohedron lattice.The lattice vacancy that produces in the crystalline network can reduce the crystal lattice stress in the TeGe alloy, causes the low-energy state of material, and Fermi level is moved to valence band.

Have stable resistance intermediate value in the rhombohedron lattice although we only prove, system is a crystallite, and crystallite dimension wherein is very little, and perhaps superficial layer plays very important effect.On the model top of the main short distance local order that the amorphous model of local order is added to for explanation, if be not fine prophesy to the explanation of atomic properties, so, this theory or acceptable.When thinking that material is amorphous state, the defect state density maximum in the bandtail portion of contiguous band edge, and the recombination center degree of depth of catching charge carrier is away from the band edge place.The deep trap and the afterbody attitude that occur might be explained the intermediate stable resistance value that occurs between fermi level position and the band edge.Regardless of theory, semiconductor material of the present invention is a kind of degenerate semiconductor that metalloidization (melallic-like) electricity is led that has.

Think that also the crystallite dimension in bulk semiconductor and the storage material is quite little, preferably less than 2000 , more preferably between 50 to 500 , the most preferably at 200 to 400 .And, think that these crystal grain are the many fermi level position that are of value to rapid formation material, can detect (conductivity) of different resistance values, and only need more low-yieldly just can between these detectable resistance values, transmit, the amorphous state crust that material is set exactly and repeatedly surrounds.

By another mode discovery of the present invention, the conversion characteristic of the semiconductor devices that two ends made from crystallite semiconductor materials of the present invention or three ends are drawn modulates that to be that may command must resemble recurrent and detectable resistance value effective equally.Have been found that, for making material of the present invention be set at required conductivity (determining) rapidly by fermi level position with the low energy input signal, only need stable state (or long-term metastable state) can occur at least two different fermi level position, fermi level position is that conductivity is not all feature with stable basically band gap.

As mentioned above, think that also the crystallite of relative reduced size can help the quick conversion between the detectable resistance value.Now suppose, owing to microstructure can easily be adjusted on atomic level, so the crystallite crystalline network can be changed these resistance values quickly.For example, in order to guarantee to improve conductivity, the unshared electron pair that decision is changed fast and the key of Ge or Sb atom needn't be blocked by electric pulse.

A feature of semiconductor material of the present invention is its more and littler crystallite that tends to form per unit volume.The wideest preferable range that has been found that the crystallite dimension that embodies typical material of the present invention is much smaller than 2000 , generally less than about 2000 to 5000  of the peculiar scope of existing material.Here crystallite dimension is defined as the diameter of crystallite, perhaps is the diameter of its " characteristic dimension ", and it is equivalent to be shaped as the diameter of aspheric crystallite.

Determine that satisfy the TeGeSb material series of standard of the present invention, the feature of the composition of its high-impedance state is usually, compares with existing electrically-erasable memory material, essence has reduced the concentration of Te.In a composition that the electric conversion operations characteristic that essence improved is provided, the Te mean concentration in the deposition materials is far below 70%, is lower than approximately 60% especially, is generally about scope of 23% to about 58%Te, preferably about Te of 48% to 58%.The concentration of Ge is about more than 5%, and the mean value in the material remains on below 50% usually in about scope of 8% to 40%.Remaining basis element is Sb in this composition.The number percent that provides is atomic percent, and composition atoms of elements summation is 100%.Therefore, this composition can be expressed as Te _aGe _bSb _100-(a+b)These Te-Ge-Sb ternary alloy three-partalloys can be used as the added storage material that starting material exploitation has better electrical property.

The ternary phase diagram of Te:Ge:Sb system is shown in Fig. 8.Various potpourris by Te, Ge and Sb prepare melt, congeal into heterogeneous by quick already solidified melt branch.Analysis to the quick already solidified melt of this class shows, has 10 kinds of different phases (not being to be present in simultaneously in any quick already solidified melt).These are mutually: element Ge, Te and Sb, binary compound GeTe, and Sb ₂Te ₃, 5 kinds of different ternary phases.The element composition of all ternary phases is positioned at pseudo-binary GeTe-Sb ₂Te ₃On the line, and indicated by reference number A, B, C, D and E in the ternary phase diagram of Fig. 8.The atoms of elements ratio is listed in table 1 in these 5 kinds of ternary phases.Below will illustrate in greater detail Fig. 8.

Table 1

The ternary crystalline phase that observed TeGeSb is

Label	Atom %Ge	Atom %Sb	Atom %Te
Label	Atom %Ge	Atom %Sb	Atom %Te	A B C D E
	40 26 18 14 8	10 18 26 29 35	50 56 56 57 56	A B C D E

Novel memory cell of the present invention comprises the high capacity storage medium, and said storage medium preferably includes at least one sulfur family and can comprise one or more transition metal.The storage medium that comprises transition metal is the element modified of our Te-Ge-Sb ternary system storage medium.That is element modified storage medium has constituted the improved form of Te-Ge-Sb storage alloy.It is under additional chalcogen such as Se existence or non-existent situation that this element improves, by what realize to basic Te-Ge-Sb ternary system adding transition metal.Usually, first rope modified storage medium is divided into two classes.

First kind is the storage medium that comprises Te, Ge, Sb and transition metal, and its ratio is (Te _aGe _bSb _100-(a+b)) _cTM _100-c, footnote is an atomic percent here, and the total amount of composition element is 100%, and wherein TM is one or more transition metal, and a and b are as above-mentioned basic Te-Ge-Sb ternary system defined, and C is between about 99 to about 99.5%.Transition metal preferably includes Cr, Fe, N ₁And the potpourri of alloy.The specific examples of storage medium comprises (Te in this series ₅₆Ge ₂₂Sb ₂₂) ₉₅Ni ₅, (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Ni ₁₀, (Te ₅₆Ge ₂₂Sb ₂₂) ₉₅Cr ₅, (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Cr ₁₀, (Te ₅₆Ge ₂₂Sb ₂₂) ₉₅Fe ₅, (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Fe ₁₀, (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Ni ₅Cr ₅, (Te ₅₆Ge ₂₂Sb ₂₂) Ni ₅Fe ₅, (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Cr ₅Fe ₅Deng.

Second kind is the storage medium that comprises Te, Ge, Sb, Se and transition metal, and its ratio is (Te _aGe _bSb _100-(a+b)) _cTM _dSe _100-(c+d), footnote is an atomic percent here, and the total amount of composition element is 100%, and TM is one or more transition metal, and a and b are as above-mentioned basic Tc-Ge-Sb ternary system defined, and c is between about 80 to about 99%, and d is between about 0.5 to about 10%.Transition metal preferably includes the potpourri of Cr, Fe, Ni and alloy thereof.The specific examples of storage medium comprises (Te in this series ₅₆Ge ₂₂Sb ₂₂) ₉₀Ni ₅Se ₅, (Te ₅₆Ge ₂₂Sb ₂₂) ₈₀Ni ₁₀Se ₁₀, (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Cr ₅Se ₅, (Te ₅₆Ge ₂₂Sb ₂₂) ₈₀Cr ₁₀Se ₁₀, (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Fe ₅Se ₅, (Te ₅₆Ge ₂₂Sb ₂₂) ₈₀Fe ₁₀Se ₁₀, (Te ₅₆Ge ₂₂Sb ₂₂) ₈₅Ni ₅Cr ₅Se ₅, (Te ₅₆Ge ₂₂Sb ₂₂) ₈₀Ni ₅Fc ₅Se ₁₀, (Te ₅₆Ge ₂₂Sb ₂₂) ₈₅Cr ₅Fe ₅Sc ₅Deng.

The memory element of present patent application has non-volatile basically setting resistance value.Yet, if the resistance value of memory element of the present invention has departed from its original start value under certain conditions, " form and change ", explanation is below arranged, can be used for eliminating this departing from.Here employed term " non-volatile " relates to a kind of condition, wherein sets resistance value and remains unchanged substantially in during database.Certainly, can adopt software (comprising) to guarantee outside selected extent of the error, to occur anything but departing from hereinafter with the feedback system of discussing.Do not having under the situation of other influence, because the gray scale storage that departs from the information that can hinder of memory element resistance value, thereby wish to reduce to depart from.

" form change " here be defined as comprising the material that changes mass storage from forming, thereby produce any method of basicly stable resistance value, comprises that the interpolation band gap widens first intrinsic resistance that usually improves material.Form the inhomogeneity that an example that changes comprises that gradual change is formed with different-thickness.For example, make the mass storage material, gradual change from having different first kind of Te-Ge-Sb alloy to the second kind of Te-Ge-Sb alloys of forming.The composition gradual change can be adopted and can reduce to set any form that resistance value departs from.For example, form gradual change and be not necessarily limited in the same alloy series first kind and second kind.In addition, can also be by finishing gradual change more than two kinds of alloys.Gradual change can be uniform and continuous, also can be uneven and discontinuous.Can cause reducing the special case of forming gradual change that resistance value departs from, comprise a Ge from a surface ₁₄Sb ₂₉Te ₅₇Ge to opposed surface ₂₂Sb ₂₂Te ₅₆All even continuous gradual change.

The another kind of method that adopts composition improvement reducing resistance to depart from is to make the layering of high capacity storage medium.That is, can by difference a series of separation, relative thin form the layer, form the high capacity storage medium.For example, the high capacity storage medium can comprise one or more pairs of layer, and every pair is made of different Te-Ge-Sb alloys.Equally, the situation of forming as gradual change can essence reduces any layer the combination that resistance value departs from and all can adopt.These layers can have identical thickness, also different thickness can be arranged.Can adopt any amount of layer, also can in the high capacity storage medium, present the multilayer of same alloy, adjoin each other or mutually away from.But also can adopt the different-alloy of any number of plies to form.A special case forming layering is to comprise Ge in the high capacity storage medium ₁₄Sb ₂₉Te ₅₇And Ge ₂₂Sb ₂₂Te ₅₆Alternating layer right.

Being used to reduce the composition inhomogeneity of the another kind of form that resistance departs from, is to realize with combining of layering of composition by forming gradual change.More particularly, above-mentioned composition gradual change can combine with in the above-mentioned composition layering any one, thereby forms stable high capacity storage medium.Use the high capacity storage medium example of this combination to have: (1) high capacity storage medium comprises Ge ₂₂Sb ₂₂Te ₅₆The layer of a separation, follow by Ge ₁₄Sb ₂₉Te ₅₇And Ge ₂₂Sb ₂₂Te ₅₆Gradual change form.(2) the high capacity storage medium comprises Ge ₁₄Sb ₂₉Te ₅₇A separation the layer and Ge ₁₄Sb ₂₉Te ₅₇With Ge ₂₂Sb ₂₂Te ₅₆Gradual change form.

Referring to Fig. 1, here the sectional view that has shown the structure division of electrically-erasable memory of the present invention, this storer are formed on the semiconductor wafer composed of monocrystalline silicon 10, and this wafer is that the P type mixes, and form P type substrate, be used for all the other elements of deposit schematic structure.Being formed on the P type substrate 10 is n+ raceway groove 12, can adopt the method for knowing in the prior art to carry out diffusing, doping.These n+ raceway grooves run through substrate in the direction perpendicular to drawing, are formed for the cover electrode in the x-y electrode canopy lattice of each memory element addressing, are the y cover in this embodiment.

Formed the crystallization epitaxial loayer 14 of the n type doping of thick about 5000  in the upper end of this n+ canopy lattice structure.Use known mask and doping techniques, in n type epitaxial loayer 14, form P type doping insulated trenches 10.As shown in Figure 1, these P type doping insulated trenches 10 extend to P type substrate 10 always, and extend so that center on fully, insulate and limiting the isolated island 18 of n type epitaxial loayer 14.Isolated island 18 shows clearlyer in the top view of Fig. 2, and wherein P type insulated trenches has formed an insulation grid, limits and the isolated island 18 of the n type epitaxial material that insulated.SiO ₂Insulated trenches can be used for replacing P type doped channel, makes isolated island 18 insulation.Form this SiO ₂The technology of insulated trenches is that the person skilled in art is known.Heat growth SiO ₂Layer is formed on the structure of just having described subsequently, and etching forms the hole 22 on the isolated island 18.Then in 22 restricted portions in hole, form the diffusion region 24 of P+ material, as shown in Figure 1.Semiconductor junction between P+ district and the n type epitaxial loayer has been determined the p-n junction diode, and passes through SiO ₂Each the n type epi region series connection that comes out in the hole 22 of layer 20.

Memory element 30 is deposited in the P+ district 24, forms the series connection of ohm electricity with each diode 26 respectively and contacts.Memory element 30 has by what high corrosion resistant metal (for example molybdenum) was formed and electrically contacts thin bottom 32, in the past, in Ovonic EEPROM, adopt conduction amorphous carbon individual layer as diffusion barrier layer 34 and 38, yet in the structural change type memory element of existing invention, these amorphous carbon layers have obtained changing or replacing.The structure of this change comprises with the amorphous silicon individual layer replaces amorphous carbon layer, perhaps thin silicone layer is arranged between amorphous carbon layer and the storage material layer 36.The top that corrosion resistant metal is formed electrically contacts thin layer 40, is made by molybdenum, and conduction diffusion barrier layer 38 is made by amorphous carbon, amorphous silicon or amorphous carbon/amorphous silicon dual structure.Contact layer 32,34,38 and 40 forms the excellent electric contact with storage material layer 36, and layer 34 and 38 also forms diffusion barrier, and the diffusion and/or other the outside contact canopy grid material contact that are used for suppressing molybdenum enter high capacity chalkogenide storage medium 36.When amorphous silicon layer 34 and 38 was used in combination with amorphous carbon, its thickness was thin comparatively speaking, and typical scope at 50 to 600  is more specifically at 100 to 400 .When layer 34 and 38 used as amorphous silicon separately, its thickness depended on its resistivity at 400 to 2000 .Molybdenum layer 32 and 40 is relatively thick, in the scope of about 1000 to 2000 .

Storage material layer 36 is formed by the multielement semiconductor material, sulfur family material for example disclosed herein.Layer 36 can adopt following method deposit, for example sputter, and evaporation or chemical vapour deposition (CVD), this can be strengthened by plasma technology, for example RF glow discharge.The manufacture method that sulfur family storage medium override of the present invention adopts is RF sputter and evaporation.The typical deposition parameters that is used for RF sputter and evaporation chalcogenated layer 36 is listed in table 2 and 3 respectively.

Table 2

RF sputtering deposit parameter

Parameter	Typical range
Parameter	Typical range	Pressure of foundation sputter gas (Ar) pressure sputtering power frequency deposition speed deposition time thickness underlayer temperature	8×10 ^-7-1×10 ^-640-60 watt of 13-14MHz 0.5-1  of torr 4-8m torr/second 20-25 minute 750-1250  environment-300 ℃

Table 3

The evaporation deposition parameter

Parameter	Typical range
Parameter	Typical range	Pressure of foundation evaporating temperature deposition speed deposition time thickness underlayer temperature	1×10 ^-6-5×10 ^-6Torr 450-600 ℃ of 0.5-3.5 /second 3-20 minute 750-1250  environment-300 ℃

To analyzing according to the film of the listed vaporous parameter deposit of table 3, the experimental data that is obtained shows that the fermi level position of fcc phase has moved the edge (being that fcc shows as the semimetal that activation energy is zero ev mutually) near valence band.Should notice that " as deposit " thin evaporated film is an amorphous state, anneal subsequently so that obtain the Fcc crystalline network.In contrast, the fermi level position of hex crystal structure (it is to realize by importing additional electric pulse) has been shifted to valence band (that is, this position presents the characteristic of " degeneracy semiconductor " or metal) in fact.The film of sputtering deposit is compared with the film of evaporation deposition, and the difference on the conversion characteristic that exists between them, its reason are not understood fully.Experimental data is tended to proof, has been caused the difference of fermi level position by the impurity of the oxygen generation that exists in the sputtered film.Yet, it should be noted that oxygen is present in the cathode targets material.Its existence is recently from analytically finding.Notice that following situation also is important, the thin evaporated film that is deposited on the heated substrate presents anisotropic growth characteristic (see figure 10), wherein dense time deposit the oriented layer of chalcogen.No matter whether this shows Special Significance, but still need confirm concerning electrical applications, yet this class film is hopeful to be used for thermoelectricity (having higher calorific power owing to measure these compositions, promptly big 4 times than bismuth system) or specific semiconductor and supraconductivity.

Storage material layer 36 best deposits are the thickness of about 200  to 5000 , are about 400  to 2500  better, are about 250  to 1250  best.Although lateral dimension is not had physical constraints, the lateral dimension of the hole of semiconductor material 36 or diameter are less than about in the of 1 to 2 micron.Determine that the diameter of the actual conductive path of high conductivity material is significantly less than micron.Therefore pore diameter can be as small as the degree that the restriction of lithography resolution characteristic can allow, and in fact, hole is more little, and it is low more that electricity is changed required energy.In preferred embodiment of the present invention, select pore diameter to make it consistent with the low impedance path diameter, this low impedance path forms when material converts low resistive state to.Therefore, the pore diameter of storage medium 36 is preferably little about 1 micron so that high capacity storage medium 36 is limited in the possible degree of lithography, make material 36 can be between various resistance states actual converted.This has further reduced switching time and has begun to detect the required electric energy of changes in resistance.Term used herein " pore diameter " refers to the lateral cross section size of storage material layer 36, and storage material layer 36 extends under the contact layer, and this contact region is that the p+ layer with accumulation layer 36 and bottom, the conductor 42 on top are formed, as shown in Figure 1.Necessary as the memory element operate as normal, the hole district of memory element 30 is preferably heat-insulating and/or controlled, but except the electrically contacting of upper and lower electrode.This further retrains, limits and controlled from the heat transfer of hole conversion volume and the required electric energy of resistance conversion.This realizes by oxide layer 20 and 39 in example shown in Figure 1, and these layers surround the horizontal periphery of memory element 30.Therefore, for the energy/current/voltage that reduces to set, should adopt little pore diameter to 250 .

Layer

32,34,36,38 and 40 is carried out etching, form oxide layer 39 thereon and, make it above memory element 30, reserve perforate its etching.As an alternative, memory element can adopt two-step etch process to form,

illuvium

32 and 34 at first, and in its top etching,

deposit remainder layer

36,38,40 and be etched into required size respectively then.The total deposited on top that forms by

layer

32,34,36,38 and 40 be the second electrode grid structure, this is formed by aluminium conductor 42, it extends perpendicular to the direction of conductor 12, and the x-y grid of finishing each memory element connects.Covering on the whole integrated structure is top encapsulation layer 44, by suitable seal layer such as Si ₃N ₄Perhaps plastic material such as polyamide are formed, and make sealing structure prevent to cause performance decline and the steam that worsens and other extraneous element to enter.For example can adopt the low-temperature plasma depositing technics to come deposit Si ₃N ₄The sealant polyamide material can rotate deposit and oven dry after deposit according to prior art, thereby forms sealant 44.

Should be noted that traditional CMOS technology can not be used for making the three-dimensional storage array of this class,, thereby can only be used for preparing single layer device because the CMOS technology is that a semiconductor devices that needs is arranged in the integral body of single crystal semiconductor sheet.And (1) CMOS can not produce big array effectively with enough little footprint (actual components size), owing to be present in single plane, CMOS can not be along connecting in the Z direction (2).Therefore, cmos device can not be prepared into the interconnecting line with composite three-dimensional, and this is that senior parallel processing computer is needed.Three-dimension film storage array of the present invention can carry out traditional serial information on the other hand and handle, and also can carry out parallel information and handle.

Parallel processing and multidimensional memory array structure are that to finish complex task fast necessary, Figure recognition for example, classification and combination learning etc.Further using and illustrating of parallel processing is recorded in U.S. Patent application No.594387, submit to October 5 nineteen ninety and transferred the application's assignee, its disclosed content is also incorporated by reference here.Yet, form the integrated morphology fully vertically of memory element and isolating diode for the integrated structure shown in Fig. 1 example, thus reduced by each memory element and diode in conjunction with occupied Substrate Area.This means that the density of memory element on the substrate only is subject to the resolution capability of plate-making art basically.

Except diode 27, the example of Fig. 2 is identical with Fig. 1, and this diode is worked by the Schottky barrier mode, is arranged on n layer 14 and metal level 29 as between the platinum silicide.In others, the structure example of the storage unit/isolated component among Fig. 2 forms by the mode identical with Fig. 1, and components identical is marked with identical reference number.

So the integrated structure that forms is an x-y storage matrix, and it connects as shown in Figure 3, and wherein, between horizontal x line 42 and vertical y line 12, each memory element 30 is connected in series with diode 26.Certainly, other circuit configuration of finishing electrically-erasable memory of the present invention is possible with feasible.A concrete useful configuration is a multistage array of three-dimensional, and the plane of wherein a series of storages or control element and isolating device separately thereof are by stacking mutually.The plane of each memory element and isolating device separately thereof are by stacking mutually.The planar cloth of each memory element is set to the row and column of a series of memory elements, thereby can carry out the x-y addressing.This plane stacking except improving storage density, the interior connection of the Z direction that can also add.This layout is specially adapted to simulate the neural network of true intellectual service computing machine.

Fig. 4 is the conspectus that the part of the memory cell examples of Fig. 1 is imitated.This circuit comprises an x-y grid, and wherein, in the point of crossing of x addressing line 42-and y addressing line 12, each memory element 30 and an isolating diode 26 are electrically connected in series, as shown in the figure.Addressing line 12 is connected with outside addressing circuit with 42 modes by prior art.The x-y matrix of memory element is with the purpose that combines of isolated component, make each read and write in the memory element independently be not subjected in the matrix contiguous or away from memory element in the interference of canned data.

Fig. 5 shows the part sketch of a single crystal semiconductor substrate 50, has formed storage matrix 51 of the present invention on the substrate.On same substrate 50, also form an addressing matrix 52, and suitably be connected with storage matrix 51 by integrated circuit connecting line 53.Addressing matrix 52 comprises signal generation apparatus, is used for determining and controlling setting and the read pulse that puts on storage matrix 51.Certainly, addressing matrix 52 can with solid storage matrix 51 integrated formation simultaneously.

Prior art thinks, has the semiconductor memory of high relatively slewing rate and low switching energy, and for its great majority were used, each memory element needed at least one transistor and a capacitor.Form sort memory in the integrated circuit form, no matter how integrated circuit is arranged, all needs at least three bonding pads that link to each other with other additional complicated part, and this will take certain Substrate Area at least.In the integrated circuit configuration of electrically-erasable memory of the present invention, each memory element only needs two bonding pads, and they can concern manufacturing by orthogonal.In addition, each memory element will connect isolating diode and a pair of contact region thereof, himself is vertical integration fully, can obtain significantly high bit density like this.In fact, the bit density that storer of the present invention provides is greater than available, even greater than the density of solid dynamic RAM (DRAMs), DRAMs easily loses, so it does not have and the invention provides resulting non-volatile advantage.Convert corresponding reduction on the manufacturing cost to by the raising of the resulting bit density of the present invention, this is because the shared chip area of per unit bit of integrated circuit configuration is less.This makes storer of the present invention not only aspect electrical property and storage capacity, and aspect cost, can be in usable range widely with other commercially available memory contention and surpass it.With need the formed semiconductor memory of at least one transistor and capacitor to compare by each bit in the prior art, integrated circuit configuration of the present invention, as shown in Figure 1, under the situation that adopts identical photoetching resolution, can on wafer, form the bit density higher than existing configuration.Except the bit density of Yin Genggao and the cost advantage that provides, compacter between the element, and cause length, electric capacity and other correlation parameter further to reduce to have improved thus performance.

The novel semiconductor material of the application of the invention realizes that the change of fermi level position and the change energy needed of corresponding conductivity have reduced several magnitude.And, believe now, even picojoule energy essential to the invention can also further reduce by shortening electrical pulse time.In addition, reducing of material thickness can reduce further that memory element is set in the required pulse energy of given resistance value.

The following detailed description will illustrate from understand disclosed should the discovery scope, release its manufacture method.Has rhombogen distortion structure (88.2 ° rather than 90 ° NaCl (being face-centered cubic)) by the crystalline solid GeTe of melt growth in room temperature.This structure is being changed into face-centred cubic structure more than 400 ℃.The reason of skew distortion, and particularly distortion and high electricity to lead among the P type GeTe relation between the Ge hole concentration not clear.At this skew distortion crystalline state, GeTe presents conductivity metal, and (≈ 10 ³-10 ⁴) (ohm-cm ^-1).At form of film, GeTe can grow with amorphous phase, crystallizes into face-centred cubic structure about 200 ℃.Because the microstructure of film is stable at this metastable face-centered cubic of room temperature mutually.Yet in about annealing temperature more than 400 ℃, the dense content according to Sb of face-centred cubic structure is changed into stable hexagonal or diamond structure.

In the Ge-Sb-Te ternary system, replace its results of property of Ge among the GeTe and pure GeTe crystal class seemingly with Sb.In bulk, stable room temperature is the hexagonal phase mutually, but believes that at high temperature it changes into the face-centered cubic phase.During annealing, amorphous film about 200 ℃ at first crystallization become the face-centered cubic phase, but when high annealing, it changes into the hexagonal phase again.The temperature that produces this structural transformation depends on the specific composition of film.The thin-film electro characteristic of amorphous and crystallization Ge-Sb-Te material has illustrated.In amorphous state, learn that by the optical absorption measurement optical band gap shows the Sb concentration in 0 to the 35 atom % scope insensitive, measurement is carried out about 0.7ev.Drop to Ge lentamente about the 0.4ev of the electric activation energy of material by amorphous GeTe system ₂₂Sb ₂₂Te ₅₆About the 0.35ev of system.

No matter be the noncrystal membrane of what composition after annealing all crystallization be the face-centered cubic phase.The conductivity of these films is by 10 of amorphous phase ^-3(ohm-cm ^-1) about bring up to 1 (ohm-cm of face-centered cubic crystallization phase ^-1) about.This transformation takes place about 180 ℃.The fermi level position of this face-centered cubic lattice is about 0.18ev, and this approximately is half of optical band gap about the 0.4ev that measures.In the further annealing about to 300 ℃ about 180 ℃, can not change conductivity of electrolyte materials or optical delivery.The infrared ray absorbing of measuring in 1 to 50 micrometer range is negligible, and this shows that in face-centred cubic structure the concentration of free charge charge carrier is quite low.Cause further changing into mutually hexagonal crystal lattice structure at 350 ℃ thermal annealings.At this crystal lattice state, conductivity is further brought up to 100 (ohm-cms ^-1) about, and strong free carrier absorption appears, follow known relationship α=A λ ², α is an absorption coefficient here, and λ is a lambda1-wavelength, and A is the proportionality constant of free carrier quantity.According to our measurement, after the transformation mutually between face-centered cubic and hexagonal attitude produced, the optical band gap of material can marked change.But, measured the strong raising (≈ 25%) of reflectivity.

In order to recycle novel memory cell of the present invention, need carry out following processing, apply quite high energy to material before first the use, material transition is become first crystalline state.The fermi level position of this crystalline state is the order of magnitude about 0.18ev, and this fermi level position with above-mentioned face-centred cubic structure is identical, and conclusion is that material has experienced the transformation mutually from amorphous to face-centered cubic crystal lattice structure.And owing to used additional, less energy, fermi level position has reduced, and this shows that material has experienced further crystal transition, becomes above-mentioned hexagonal crystal lattice phase.By the crystalline texture of this material grains of varying cyclically, enter and the scope by different fermi level position, set up the stable crystalline transition of crystallite semiconductor materials of the present invention.

The reversible variation of the conductivity that this crystallite semiconductor materials is shown appears in a kind of crystallization phase of this material at least.This variation that is approximately the conductivity value of two orders of magnitude is closely corresponding to the difference of the resistance dynamic range of the present invention's electricity memory element, as to the laboratory measurement of massive material.

For material is changed to different Resistance states from crystalline state such as face-centered cubic attitude, need to use the electric pulse of short more high energy.For example, 30 nanoseconds pulse can make the hexagonal crystalline texture of crystallite chalcogenide film material be transformed into face-centered cubic crystalline texture.By measuring the free charge density of annealing front and back, tangible free carrier does not take place absorb.The crystalline film of this prompting face-centred cubic structure has lower thermal excitation free charge (hole) concentration, and this is different from semiconductor material (because Fermi level has moved to contiguous or all entered valence band) the hexagonal phase, that can think the P type, the height degeneracy.

Should be noted that the end points of the dynamic range (determining) of the conductivity that the present invention sets up by fermi level position, not necessarily must be corresponding to the change of the crystalline state between face-centered cubic and the hexagonal crystalline texture.On the contrary, more obviously be such fact, material must be returned to non crystalline structure never, and therefore, the end points of conductivity dynamic range may originate from one or more crystalline textures, and can keep lower energy input thus and be in very high speed.

If consider the disconnection that has between the crystal lattice structure of free charge concentration in a way, there is a mechanism here, can be used to provide to understanding helpful information of existing of multiple stable intermediate state.The existence of external electrical field can cause charge discrepancy and make lattice deformability thus, and this is known.These two kinds of reactions are independently.In order to change the number of cavities in the tellurium one antimony parent, the atom of necessary mobile germanium and/or antimony.Below be possible, when applying the outfield, the reaction of lattice of distortion be interrupt some key and produce additional be subjected to main can energy level (in the lattice higher hole concentration), or influence each other, thereby in band gap, produce or the various attitudes that disappear at the unshared electron pair and/or the said unshared electron pair of the simple mobile nonbonding of its regional area.Under any circumstance, net result does not depend on material amorphous state formula crystalline state in the past.

By experiment, the inventor shows, following factors such as pore-size (diameter, thickness and volume), sulfur family are formed, hot preparation (later stage deposit annealing), the signal pulse duration, be present in the composition impurity as oxygen, crystallite dimension and signal pulse waveform to the amplitude of resistance dynamic range, as described in dynamic range the end points absolute resistance and that device is set in the required voltage of these resistance is all influential.For example, thick relatively chalcogenide film (promptly about 4000 ) will cause the higher setting voltage of needs (and producing higher current density thus in storage medium), and the chalcogenated layer of relative thin (promptly about 250 ) will cause need be lower setting voltage (and current density).Certainly, the possible remarkable meaning that ratio had between the quantity of atom in the quantity of crystallite dimension and surface atom and the piece has been described before this.

The inventor infers, the actual least significant end that is in hexagonal lattice structure of village's material, and therefore, low-down energy input can cause that this phenomenon of remarkable change of fermi level position and resistance value is not surprised.And the inventor infers, from the change of face-centered cubic to six side/rhombogen phase, can be interpreted as removing germanium and/or the antimony atoms that lacks to 2% by crystallization, manages to reach preferred proportion of composing (Te with this ₅₂Ge ₄₈The binary that is the light choosing is formed).Because the minimizing of each atom provides the lattice with an extra holes, this will make every cubic centimetre free charge concentration bring up to 10 ²¹The order of magnitude, this value be can by the heat in this low bandgap material take place not cover.The raising of this free charge concentration is called " autodoping " or " self compensation " here.What be worth extra care is that the band gap that these semiconductors are formed can alloy be widened or further constriction by being melt into other semiconductor material such as silicon, sulphur or carbon.In addition, by being melt into the reduction that alloy also can realize setting electric current with other semiconductor material such as selenium.

Fig. 6 is a diagram, and wherein the resistance of the memory element that is formed by novel semiconductor material of the present invention is marked on the longitudinal axis, and the duration of pulse that applies is that 25 nanoseconds pulse voltage is marked on transverse axis.This figure clearly illustrated, particularly under the situation of specific semiconductor material and device architecture and size, the wide dynamic range of obtainable resistance value.The illustrated resistance dynamic range of this certain device greater than an order of magnitude about.During less than 3 volts of left and right sides, resistance value is constant at input pulse for the data presentation of Fig. 6.When apply 3 deep-sited pulses towards the time, device resistance sharply drops to 6 * 10 ³About ohm, this value is corresponding to the low-resistance end of dynamic range.According to the high voltage pulse that applies, from 4 volts to 9 volts, the device resistance linearity increases to about 7 * 10 ⁴Ohm, this is corresponding to the high resistant end of dynamic range.Notice resistance-voltage curve that this is linear, and need not to be set to again the remarkable ability that " initial state " can carry out along these curve two directions.Because this wide dynamic range, curve linear and, make this semiconductor material can be used to be characterised in that directly to rewrite, the storer of multistage storage capacity along the ability that the curve both direction moves.

Memory element in the dynamic range of resistance, is set in the required signal pulse duration of resistance value of expectation, will depends on aforesaid all factors and signal voltage equally.The typical signal pulse duration will be less than about 250 nanoseconds, preferably less than about 50 nanoseconds.Should emphasize, even the pulse width of 25 nanoseconds of less thaies also depends on the thickness of employed semiconducting alloy and the size and dimension of composition and hole.Believe under the condition of the operation that does not influence storage switch, significantly the chopped pulse duration.In fact, adopt less energy input, can the most suitably improve the cycle life of element.

When needing, can read and regulate the feedback circuit of the resistance of given memory element, can be in conjunction with entering storage system of the present invention.For example, a memory element may be set on the resistance of expectation at first, and after after a while, the resistance of element can depart from the value of original setting slightly.In this case, feedback circuit will calculate and transmit the update signal pulse with required voltage and duration gives memory element, and it is taken back the resistance of pre-selected.And, can have this situation, the setting pulse that is transferred to memory element not with components set on the resistance of expectation.In this situation, feedback circuit will be to the extra signal pulse of element transmission, up to the level that reaches expectation.The total duration of setting/regulating cycle that these are a series of is less than about 1000 nanoseconds, preferably less than about 500 nanoseconds.

Can not overemphasize along the reversible ability that moves up and down of the linear segment of resistance-voltage curve.Shown in arrow among Fig. 6, the signal pulse of a selected voltage will be set in memory element on the resistance of expectation, and no matter how imposing a condition formerly.Thisly provide the direct rewriting of formerly storing data along the reversible locomotivity of curve.The ability of this direct rewriting is impossible for (a-Si) storage medium of the MSM in the prior art and phase transformation.The ability of resistance is significant in the middle of this reversible the setting.A large amount of continuous 5 deep-sited pulses are dashed to have reached with 8 deep-sited pulses and dashed the similar resistance that the back dashes with one 5 deep-sited pulse, and are perhaps identical towards the resistance that the back dashes with one 5 deep-sited pulse with 4 deep-sited pulses.No wonder the physics of the unusual operation of this revolutionary material is explained it is difficulty so.

The dynamic range of resistance also allows wide gray scale and multilevel simulation storage.By wide dynamic range is divided into a series of subranges or rank, realize this multistage storage.This analog storage ability allows a plurality of bit storage of binary information in single memory cell.This multistage storage is finished like this, with analog form a plurality of bits of binary information are simulated, and this analog information storage at single memory cell, thereby, the dynamic range of resistance is divided into 3 or more a plurality of simulation rank, and each storage unit will have

storage

1 and 1/2 or the ability of the binary message of more bits.

Fig. 7 shows with form; Result from electricity and light data that typical Te-Ge-Sb forms, this composition belongs to new range semiconductor material of the present invention.These data result from by sputtering deposit and carry out the sample that later stage deposit thermal annealing prepares subsequently in air.Shown in these data, the preparation amorphous phase has the band gap of about 0.7ev, and fermi level position is approximately 0.37ev, and optical reflectivity is approximately 35%.This material shows as the intrinsic narrow gap semiconductor when amorphous phase.Yet the electricity and the holding property of light of two kinds of crystal lattice crystalline phases that non-crystalline material can be transformed into just have Special Significance.The face-centered cubic that " preparation " has same composition has the band gap of about 0.4ev mutually, fermi level position is about 0.18ev, light reflectivity is 48%, and show as the intrinsic narrow bandgap semiconductor material, and, the band gap that six side's phase samples have is mutually identical with face-centered cubic, but the dynamic range of wide fermi level position is arranged, according to the thermal annealing distributions in 0.0 to 0.18ev.It is about about 48% to 73% light reflectivity that six sides have scope mutually, and shows as narrow band gap, P type degeneracy semiconductor material.The wide dynamic range of the fermi level position of this scope and the electricity that causes (conductivity/resistance) and light (reflectivity) characteristic, facility can be carried out the gray scale electricity and the optical storage of information.The degeneracy effect, promptly to move to valence band edge be significant to fermi level position.In order to measure this effect in low bandgap material, free charge concentration must be very high,

Because this extrinsic effect has been flooded in hot charge generation usually in this material.Thereby this high concentration hole is one of the most remarkable aspect of the present invention.

The conversion modulation institute energy requirement of electrical storage of the present invention is more much smaller than prior art.Based on our understanding, this is not surprised.All existing materials all depend on the transformation of amorphous to crystallization phase, and material of the present invention relies on and to crystallize to that crystallization phase changes and come work or work in monocrystalline, and these change the raising that causes conductivity mutually.

The inventor infers this material real work in the least significant end of hexagonal lattice structure, therefore can cause that to low-down energy input the remarkable change of fermi level position and resistance value is not surprised.And the present invention goes into to infer, from the change of face-centered cubic to six side/rhombogen phase, can be interpreted as removing germanium and/or the antimony atoms that lacks to 2% by crystallization, manages to reach preferred proportion of composing (Te with this ₅₂Ge ₄₈Be that preferred binary is formed).Because the minimizing of each atom provides the lattice with an extra holes, this will make every cubic centimetre free charge concentration bring up to 10 ²¹The order of magnitude, this value be can by the heat in this low bandgap material take place not cover.The raising of this free charge concentration is called " autodoping " or " self compensation " here.What be worth extra care is that the band gap that these semiconductors are formed can be widened or further constriction by alloying.

Observe, the Control for Oxygen Content in the film storage medium crystal size, perhaps in the crystallization control size, played remarkable effect.As mentioned above, atomic quantity in crystal size and the piece intercrystalline and relative scale around the atomic quantity of this crystallization are considered to control successively the fermi level position (and the extrinsic conductivity that causes thus) of semiconductor material usually.In addition, oxygen can be equivalent to foreign atom, and it forms the defect state that a lot of increases are provided for this sulfur family, is used for this expropriation of land change conductivity.The effect that this electrical effect demonstrates other formerly known sulfur family storage mediums with all is significantly different.

As noted above, Fig. 8 is the ternary phase diagram of Ge-Te-Sb semiconducting alloy system.Except the information that discussed the front, wherein binary and ternary phase are by square (■) expression, and this figure gives the information of relevant other alloy fractional condensation.These other alloys are by triangle (▲), rhombus (◆) and round spot (●) expression, and alloy fractional condensation or these phases depend on melt and solidify fast, and this is by line (solid line or the dotted line) expression of extending.The initial composition of two kinds of rich Te melts is by the round spot symbolic representation in the ternary phase diagram.By quick curing, these mixing divide the element T e that congeals into to add phase B, C and D mutually.

Have the melt of the composition on pseudo-binary line right side, represent, represent by the line that this melt is solidified into by in the phasor by diamond symbols.Other mixture solidified of being represented by the triangle in the phasor becomes element Ge with Sb and become A mutually.The all melts of forming near phase A all can find phase A after the curing fast, and the composition of phasor intermediate cam symbolic representation also is like this.Form the melt blend identical, after solidifying fast, form and approach pure phase A with phase A.Has only this this specific character that presents mutually.The alloy of Special Significance is arranged is Ge to being used for improved memory element of the present invention ₂₂Sb ₂₂Te ₅₆, also can be referred to as Ge ₂Sb ₂Te ₅Or 2-2-5.This 2-2-5 alloy divides the phase of congealing into two kinds of different in kinds through solidifying fast, and it forms B (Ge ₂₆Sb ₁₈Te ₅₆) and C (Ge ₁₈Sb ₂₆Te ₅₆) be illustrated in the phasor of Fig. 8.It is Ge that another kind has the alloy of Special Significance ₁₄Sb ₂₉Te ₅₇(also can be described as GeSb ₂Te ₄Or 1-2-4), its composition D is positioned at GeTe-Sb ₂Te ₃Pseudo-binary line.As mentioned above, for forming its high capacity storage medium of forming gradual change, layering or gradual change/layering combination, this 2-2-5 and 1-2-4 alloy acquire a special sense.

Fig. 9 is data and curves figure, and its data are taken from the data of improvement memory element of the present invention, has described stable setting resistance especially.The resistance of memory element is marked on the longitudinal axis, sets pulse voltage and is marked on transverse axis.In order to obtain this data,, shown in transverse axis, memory element is set on the selected resistance by input pulse voltage.The input pulse duration is 30 nanoseconds, and rising and fall time are 3 nanoseconds.After setting selected resistance, the actual resistance of element is read 1000 times.A readout of/10th is marked on 3 curves.The composition of memory element that is used for producing the experimental data of Fig. 9 is gradual change.In this embodiment, the high capacity storage medium is continuous evenly gradual change between above-mentioned 1-2-4 and 2-2-5Ge-Sb-Te alloy.

Read over Fig. 9, can be clear that, the setting resistance value that memory element of the present invention had presents little resistance value in during being studied and departs from (exceeding the predetermined limit of error), if any.Represented a kind of fundamental characteristics in the ability of not having under the situation about departing from the resistance value of setting preliminary election substantially, the memory element resistance depart from the loss that (limit of error that promptly exceeds permission) will cause canned data substantially.Here the term of being quoted " rise time " is meant that signal is initial and reaches time interval between moment of peak signal power, and signal power increases continuously during this period.Similarly, the term of quoting here " fall time " is meant moment that peak signal power is ended and the signal time interval between finally stopping, and signal power descends continuously during this.

Figure 10 has shown the atomic structure of Ge-Sb-Te ternary alloy three-partalloy and the atomic structure of Ge-Te bianry alloy.Two kinds in three kinds of ternary alloy three-partalloys is that above-mentioned 1-2-4 (the composition D in the phasor of Fig. 8) and 2-2-5 forms.The third ternary alloy three-partalloy is Ge ₈Sb ₃₃Te ₅₉, be also referred to as GeSb ₄Te ₇Or 1-4-7.This 1-4-7 alloy is corresponding to the composition E in the ternary phase diagram of Fig. 8.In the atomic structure of these alloys, empty circles is represented the Ge atom, and the striped circle is represented the Sb atom, and the strokes and dots circle is represented the Te atom.As shown in figure 10, when at the center of area method crystal structure, the atom configuration of each alloy is made of orderly atom circulation layer.The fcc configuration forms three kinds of dissimilar layers, and they are designated as A, B and C in Figure 10.The layer of B and C type is three atomic layers, and the layer of category-A type is 7 atomic layers.

As basic storage medium and be used for element modified storage medium of the present invention, 1-4-7 shown in Figure 10 and 2-2-5 alloy are significant.Transition metal is combined in the whole square formation of Te-Ge-Sb quite equably with Sb (if present) and has strengthened electronics/atomic structure, reduce required switching current thus and improved the thermal stability that data are preserved, the analysis showed that now, Se has replaced Te in structure, but do not know the exact position of transition metal, in view of this transition metal seems and the chalcogen bonding.

In addition, as mentioned above, when Ge-Sb-Te alloy material evaporation deposition on hot substrate the time, deposition of materials is the anisotropy form.That is when deposit in such a way, the crystallization of alloy material is directed, and the layer of constituting atom unit is arranged essentially parallel to substrate surface and arranges.Certainly, the anisotropy that this will cause electric current to flow, but the long-term possibility of atom in the material arranged is provided, so that use setting and reset pulse, thereby reach lower setting and release current, voltage and/or energy in the low-resistance direction.

Figure 11 a, 11b and 11c are three-dimensional curve diagrams, describe device resistance (1 kilohm) and input respectively and set each relation in pulse height (milliampere) and pulse rise time, pulse fall time or the pulse width (nanosecond), Figure 11 a has described corresponding to different pulse heights, device resistance as the function of pulse rise time (as defined above), here be nanosecond pulse fall time, and pulse width is 27 nanoseconds and adds pulse rise time.Figure 11 b has described corresponding to different pulse heights, and as the device resistance of the function of pulse fall time (as defined above), be 3 nanoseconds pulse rise time here, and pulse width is 30 nanoseconds.Figure 11 c has described corresponding to different pulse heights, and as the device resistance of the function of pulse width, pulse is here risen and is 3 nanoseconds fall time.

As from these figure visible and above-mentioned, by regulating impulse width, rise time and fall time, the electrical characteristics of this memory element (are the absolute end points of amplitude, resistance of resistance dynamic range, the gradient of resistance-pulse height curve etc., can be adapted to satisfy particular current/voltage needs.Should be noted that in the pulse width range of having tested all provide essentially identical result greater than about 30 nanoseconds width.This dependence true and that paired pulses rises and fall time is weak combines, and makes and can draft pulse parameter in width range.

Figure 12 a and 12b are data and curves figure, and these data are respectively not use the composition change and using composition to change stablizing under the situation of setting resistance value, taking from the data of memory element.In these figure, device resistance is marked on the longitudinal axis, and the time that originates in the setting of memory element is marked on transverse axis.The data that Figure 12 a describes are taken from 5 kinds of different memory elements, all are to be prepared by the high capacity storage medium that list-Ge-Sb-Te alloy forms.These memory elements are set at the resistance of preliminary election, after the different time, and the resistance value of measuring sensor.These data clearly illustrate that these memory elements (promptly adopting composition to change) present higher resistance value and depart from.The data that Figure 12 b describes are taken from 12 kinds of different memory elements, they form the high capacity storage medium preparation of gradual change continuously and equably by those from a Ge-Sb-Te alloy (1-2-4) to the 2nd Ge-Sb-Te alloy (2-2-5), more specifically, first of the 1-2-4 alloy independently the layer be deposit.On the top of this 1-2-4 layer, all even of composition continuously changes through the whole thickness of 1000  of sulfur family material, forms so that present 2-2-5 in another surface of thickness.Notice that this easily realizes by using its evaporation or its sputtering target.By importing 5 to 11 volts pulse, these memory elements are set in resistance value dynamic ranges on the preliminary election resistance.And, measure the resistance value of memory element through behind the different time.Data among Figure 12 b clearly illustrate that, comprise and adopt the memory element of forming the high capacity storage medium that changes, compare with not adopting the memory element of forming change, present stable in fact in time resistance value.The inventor can't explain to form to change to make and set the stable mechanism of resistance.This mechanism may belong to the model of the material growth nucleation of deposit subsequently simply, and perhaps " growth increases sharply and distributes ", this mechanism also may complicated distortion to the storage medium crystalline network.Regardless of mechanism, meaning of the present invention is to have realized to form and changes, and the setting resistance of storage medium is stablized.

Figure 13 is data and curves figure, and these data are taken from memory element, and the nominal chemical composition that this element has is (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Ni ₅Se ₅, do not have membrane silicon layer at contact layer.Among Figure 13, device resistance is marked on the longitudinal axis, writes/wipes cycle index and be marked on transverse axis.The conversion of element is as follows, use to continue 40 nanoseconds the pulse of 3 volts, 2 milliamperes electric currents with components set in high value, use lasting 400 nanoseconds the pulse of 1.9 volts, 1 milliampere electric currents with components set in low resistance.This figure shows that when using the commutation pulse of low relatively electric current, the conversion between two detectable resistances can be said to be steadily, only is 10 but write/wipe cycle life ⁵Write/wipe about cycle index.

Figure 14 is data and curves figure, and these data are taken from the high capacity storage medium, and this material comprises having nominal chemical composition (Te ₅₆Ge ₂₂Sb ₂₂) ₉₀Ni ₅Se ₅, and the thin film amorphous silicon contact layer of 200  is arranged, be arranged between high capacity storage medium and the amorphous carbon layer.Device resistance is marked on the longitudinal axis among Figure 14, writes/wipes cycle index and be marked on transverse axis.The conversion of element is as follows, use to continue the pulse of 25 nanoseconds 4.2 volts, 1.5 milliamperes electric currents, with components set in high value, use lasting 400 nanoseconds the pulse of 2.0 volts, 0.5 milliampere electric currents with components set in low resistance.This figure shows that when using the commutation pulse of obviously low electric current, the conversion between two detectable resistances is stable, writes/wipe the life-span to be at least 10 ⁶About cycle index.

Relatively use and the not device of utilization structure change prove that the device with silicon contact layer is improved on a plurality of physics/electrical characteristics.Improved conversion stability, that is the noise level of data (promptly under given input pulse, expecting the difference between resistance and the actual resistance) has reduced significantly.Be accompanied by the raising of conversion stability, the absolute amplitude ground between high resistant and the low resistance has improved.In addition, owing to added the silicon contact layer, required electric current has descended 25 to 50%.At last, the cycle life of the element of structural change has improved at least one order of magnitude.

By using material of monopolizing disclosed herein and device architecture, developed that a kind of electricity can wipe, the memory element that can directly rewrite, have fast reading and writing speed, near the ability of the non-volatile and random access reprogramming of the speed EEPROM of solid random access memory (SRAM) device, the close prices harddisk memory of per million store bytes.

The branch of the free charge concentration modulation capability that material of the present invention has may cause economically influence in field of semiconductor devices.Comment like that as the background technology of front part, on behalf of the 5th class electric charge carrier, electric charge carrier modulation disclosed herein modulate, and it has been represented and the departing from substantially of prior art.Briefly, though material of the present invention after removing the outfield, fermi level position, conductivity and free charge concentration also are maintained fixed.Therefore, it is possible setting up new series semiconductor device, wherein can use by three-dimensional or bidimensional, and this device is preprogrammed into the resistivity value of preliminary election.The two, program voltage and/or electric current are low significantly, and reaction velocity is fast significantly.This is because semiconductor material of the present invention has by caused proper velocity of the modulation that results from one or more different crystalline phases and energy ability.

Notice that reading over this instructions will understand, we can see the performance trend of the memory element that generally is relevant to pore diameter.When we use the device of binary form, during across the wafer sort device, we see closes and opens the resistance ratio and normally improve, and the pore diameter of this wafer is from being a bit larger tham one micron to not fenestration system ground distribution.If pore diameter for example is controlled at one micron to less than in 1/2nd microns the scope, existence is improved the chance of our device performance.Because bulk factor importantly in our device programming, for example current density and energy density, reducing of the device volume that is reduced to produce by pore diameter will cause the raising of sensitivity and speed.

Relevant with the programming of Ovonic.EEPROM have a threshold transition incident, thereby, wish that the Ovonic.EEPROM program voltage will show sulfur family alloy firm thickness dependence as other threshold transition.In fact, at two-way EEPROM, threshold transition voltage plays the effect of distinguishing the incident of reading from programmed events, eliminates and reads disturbance, and good opereating specification is provided when data read.When applying electric field when low, our device shows linear resistance property, strengthens resistance with electric field then and descends gradually, up to threshold voltage.In case surpass threshold voltage, device presents negative resistance, be transformed into " dynamically " state that high electricity is led.When withdrawing external electric field, device returns the resistance states of non-volatile programming, and during the state, its value depends on electric current/energy distribution that device experiences in " the storage equilibration time " of device is promptly dynamic.Although threshold voltage depends on device resistance, for all device resistance, the device current when being in threshold voltage is but constant relatively.Linear approximation method to thickness, threshold voltage relation shows its scale factor less than 1, and it provides a wide opereating specification in the device with same nominal thickness.

When thickness of detector reduces, the absolute resistance value of device will descend pro rata.Yet, when same thickness, can wish that contact resistance surpasses the less resistance value of storage medium.For the amorphous carbon electrode of the test component that is generally used for us, this contact resistance effect will be significantly less than than low conductivity silicon compound electrode material, for example palladium silicide or tungsten silicide, they are used for wafer more traditionally and make device.As mentioned above, because carbon can prevent the phase counterdiffusion, it is selected for use the earliest, yet, for the use of contact, tungsten silicide for example, tungsten will provide additional P track to the diffusion of chalkogenide, thereby strengthen electric conversion, as described here.

Can recognize, do openly with the detailed example form illustrated and occur that its purpose is detailed and intactly discloses the present invention here, details can not be interpreted as the restriction to correct scope of the present invention like this, and its definition is accompanying Claim.

Claims

1. the memory element (30) of an electricity operation comprises:

A substrate;

One that forms more than described substrate electrically contacts bottom (32);

At the described bottom diffusion barrier layer (34) that electrically contacts formation more than the bottom (32);

Go up the high capacity storage medium (36) that forms at described bottom diffusion barrier layer (34), described high capacity storage medium (36) is formed by the semiconductor material that comprises at least a chalcogen, but and can between the state of at least two electro-detection, switch according to the electric signal of selected input, wherein, but in the state of each described electro-detection, the described high capacity storage medium of at least a portion (36) is a crystal state; Described high capacity storage medium (36), electric signal according to described input, in the whole dynamic range of resistance value, has the multidigit storage capacity, with no matter the previous resistance of described storage medium (36) how, described high capacity storage medium (36) can directly be set at any one resistance in described dynamic range, write or be wiped free of thereby directly cover, do not need to be set to earlier a specific starting value or wipe resistance value earlier;

The top diffusion barrier layer (38) that more than described high capacity storage medium (36), forms;

The top electric contacting layer (40) that more than described top diffusion barrier layer (38), forms; With

The top encapsulation layer (44) that on described top layer electric contacting layer (40), forms.

2. according to the memory element of claim 1, it is characterized in that described high capacity storage medium (36) can be provided with each described resistance value, wherein after described input signal was ended, described high capacity storage medium (36) remained on described resistance value.

3. according to the memory element of claim 1, the thickness that is characterised in that described high capacity storage medium (36) is at 500 to 5000 .

4. according to the memory element of claim 1, be characterised in that the electric signal according to described input, the dynamic range of the described resistance value of described high capacity storage medium (36) has at least 4 detectable different stages.

5. according to the memory element of claim 1, wherein said high capacity storage medium (36) is the material that is selected from by in one group of material of Se, Te, Ge, Sb and composition thereof or alloy composition.

6. according to the memory element of claim 1, it is characterized in that described high capacity storage medium (36) is the material that is selected from by one group of material of Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and composition thereof or alloy composition.

7. according to the memory element of claim 6, it is characterized in that each described memory element appears in the whole described high capacity storage medium (36).

8. according to the memory element of claim 1.Be characterised in that described high capacity storage medium (36) comprises at least a transition metal.

9. according to the memory element of claim 1, be characterised in that described high capacity storage medium (36) comprises at least a element that is selected from by one group of material of Cr, Fe, Ni and composition thereof or alloy composition.

10. according to the memory element of claim 1, wherein said high capacity storage medium (36) comprises Te, Ge and Sb, and its ratio is Te _aGe _bSb _100-(a+b), footnote is an atomic percent, the total amount of the component of composition is 100%, and 40≤a≤58,8≤b≤40.

11., be characterised in that described bottom diffusion barrier layer (34) and top diffusion barrier layer (38) comprise silicon materials according to the memory element of claim 1.

12., be characterised in that described bottom diffusion barrier layer (34) and top diffusion barrier layer (38) comprise material with carbon element according to the memory element of claim 1.

13., be characterised in that describedly to electrically contact bottom (32) and described top electric contacting layer (40) comprises Mo according to the memory element of claim 1.

14. according to the memory element of claim 11, be characterised in that described silicon materials are amorphous states when initial, wherein a part of described silicon materials can crystallization in beginning formation/handoff procedure.

15. according to the memory element of claim 12, be characterised in that described material with carbon element is an amorphous state when initial, wherein a part of described material with carbon element can crystallization in beginning formation/handoff procedure.

16. memory element according to claim 1, be characterised in that described high capacity storage medium (36) comprises that the position component that is used to change wherein is so that the basicly stable device in selected resistance of its resistance, after input signal was ended, described high capacity storage medium was suitable for maintaining selected resistance and can drift about.

17., be characterised in that the described device that is used for changing the position component of high capacity storage medium (36) comprises the element that adds wide bandwidth to described storage medium (36) according to the memory element of claim 16.

18., be characterised in that the described device that is used for changing the position component of high capacity storage medium (36) comprises the increase covalent bond according to the memory element of claim 16.

19. memory element according to claim 16, be characterised in that described high capacity storage medium (36) comprises at least a composition atomic element that comprises lone pair electrons, the described device that is used for changing the position component of high capacity storage medium (36) comprises that the local environment of adjusting described lone pair electrons is to increase or to remove defect state in the band gap of semiconductor material.

20., be characterised in that the described device that is used to change component comprises the composition gradual change that makes described high capacity storage medium (36) or makes it form layering to change according to the memory element of claim 16.

21., be characterised in that described composition gradual change comprises by Ge according to the memory element of claim 20 ₁₄Sb ₂₉Te ₅₇Gradual change is to Ge ₂₂Sb ₂₂Te ₅₆Composition.

22. according to the memory element of claim 20, wherein said composition layering comprises independently Ge ₁₄Sb ₂₉Te ₅₇And Ge ₂₂Sb ₂₂Te ₅₆Layer.

23. according to the memory element of claim 20, wherein said composition layering combines with the composition gradual change, comprises one deck Ge ₂₂Sb ₂₂Te ₅₆, and Ge ₁₄Sb ₂₉Te ₅₇To Ge ₂₂Sb ₂₂Te ₅₆Gradual change form perhaps one deck Ge ₁₄Sb ₂₉Te ₅₇Layer, and Ge ₁₄Sb ₂₉Te ₅₇To Ge ₂₂Sb ₂₂Te ₅₆Gradual change form.

24. according to the memory element of claim 1, wherein said high capacity storage medium is operated and is arranged on diameter less than in 2 microns the hole.

25. according to the memory element of claim 1, the electrical input signal of wherein said selection is at least one electric signal pulse, pulse voltage is between the 1-25 volt.

26. according to the memory element of claim 25, the electric signal of wherein said selection input is at least one electric signal pulse, pulse current is between 0.5 and 1 milliampere.

27. according to the memory element of claim 1, be characterised in that described electrical input signal is a plurality of electric signal pulses, and wherein provide a feedback loop, guarantee that described memory element is arranged on selected resistance to cause extra electric signal.

28. according to the memory element of claim 1, be characterised in that described high capacity storage medium (36) by anisotropically deposit, composition atomic element wherein appears in the discrete layer.

29. memory element according to claim 1, be characterised in that described high capacity storage medium (36) and described contact region (32,34,38,40) form memory element and be shown as matrix array, wherein the wherein memory element in each described memory element and the described array provides isolating device addressable ground to isolate, each memory element in the described array can be set to any resistance in the described dynamic range by described electrical input signal, no matter the previous resistance of described storage medium (36) how.

30., be characterised in that described dynamic range and described multidigit ability can store at least 1.5 binary messages in single memory element (30) according to the memory element of claim 1.

31., be characterised in that described isolating device is diode or transistor according to the memory element of claim 29.