CN100369426C - Method for judging clock source ring in sychronous digital transmission network - Google Patents
Method for judging clock source ring in sychronous digital transmission network Download PDFInfo
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Abstract
The present invention discloses a method for judging the cyclization of clock sources, which comprises the following steps: net element clock sources are defined as clock source heads or clock source tails; clock source segments are formed by the clock source head and the clock source tail and net elements between the clock source head and the tail; all net element clock sources in a subnet are segmented according to the clock source heads in the subnet, and ID numbers are distributed to different clock sources. If all or part of the net element clock sources on certain clock source segment are connected in the form of head to tail, the cyclization of the net element clock sources is judged. The method of the present invention uses a provisional list and adopts the way of recursion to search the upstream net element clock sources of the currently processed clock sources, the cyclization errors of the subnet clock sources can be trapped in time without analyzing a large quantity of data, and debugging is carried out in time so as to avoid subnet abnormality caused by not trapping the cyclization errors of the clock sources in time due to analysis errors. With the method of the present invention, the cyclization states in the subnet can be observed, and the organizing states of various clock source segments of the subnet can be observed.
Description
Technical field
The present invention relates to a kind of method of in SDH (Synchronous Digital Hierarchy SDH (Synchronous Digital Hierarchy)) optical transport network, judging network element clock source Cheng Huan.
Background technology
If a son has the present clock source of a plurality of network elements to join end to end on the net, the present clock source Cheng Huan of these network elements then, clock source Cheng Huanhui causes the Signal Degrade on the subnet, therefore must forbid the generation of this phenomenon.At present, method for synchronous in synchronous digital hierarchy transport (SDH net) transmission equipment has following several: 1) use SSMB: reach in the ITU related specifications all on the books at home in this method, after network element adopts a clock source, can be unavailable to the mouth of the light in the same way tranmitting data register in this clock source, other light mouth sends the clock quality in selected clock source, this method can prevent adjacent network element clock Cheng Huan, but can't detect the deterioration and the non-adjacent network element clock Cheng Huan of clock.2) use the multi-frame of idle 4 compositions of SSMB and S1: number of patent application is that 96194572 Chinese invention patent discloses the simultaneous techniques in a kind of SDH network, the patent No. is 6,185,216 U.S. Patent Publication name be called the patent of Synchronization in an SDH network, all adopt this method, in the multi-frame information of idle 4 compositions of S1, comprised clock the numbering of all network element of process, a network element is when preparing to adopt certain clock source, if the sign of oneself is arranged in this clock source multi-frame information of discovery, clock Cheng Huan then is described.But the realization of this method comparatively bothers, and needs the visit of hardware supports to idle 4 of S1, and to receive enough at least 165 frame data could be as a complete Frame.
More than the method for two kinds of prior aries all be that clock source at the network element aspect becomes ring to judge, carry out on the logic analysis judgement basis in the data that the webmaster aspect also only rests on the operator and provides according to system, do not provide a kind of graphical method to show each clock source tissue situation in the subnet intuitively, find out the mistake of clock source Cheng Huan.
Summary of the invention
The technical problem to be solved in the present invention is, a kind of method of judging clock source Cheng Huan in synchronous digital hierarchy transport is provided, can overcome and to carry out the one-tenth ring judgement of clock source according to the mass data that professional knowledge utilizes system to provide, become the wrong defective of ring and can not observe the clock source intuitively, adopt this method directly to judge whether Cheng Huan of clock source by figure.
The above-mentioned technical problem of the present invention solves like this, constructs a kind ofly directly to judge the whether method of Cheng Huan of clock source by figure; It is several that the clock source roughly can be divided into invalid clock, internal clock, external clock, line clock.In order to judge whether Cheng Huan of clock source, the present invention introduces the notion of clock source, clock source tail, clock source section.If this network element clock source is not to come upstream network element, claim that then (if network element clock Source Type is invalid clock, internal clock, external clock, then this network element clock source is the clock source for the clock source of all continuous downstream clock sources and courses in this network element clock source here.If this network element clock source is last the clock source in the clock source and course of continuous downstream, then claim the clock source tail of this network element clock source for all continuous downstream clock sources and courses.Network element between clock source, clock source tail and clock source, the clock source tail constitutes clock source section;
Segmentation is carried out according to the clock source in the subnet in all network element clock sources in the subnet, give one of different clock source section ID number, if the clock source of all or some network element on the section of a certain clock source joins end to end then the clock source Cheng Huan of these network elements, constitute into the ring section, being arranged to ring section ID is 0xFF+ clock source section ID, and the present clock source that becomes the ring section to go up each network element is the clock source on this one-tenth ring section, is again clock source tail;
In said method, utilize tabulation temporarily, adopt recursion method to search the upstream network element clock source in current processing clock source:
When the subnet initialization, a global clock source section ID is set and is initialized as 0, it is 0 that each network element present clock source section ID is set, and judges according to transmitting the clock Source Type whether each network element present clock source is the clock source, if clock source sign then is set.
To the present clock source of each network element in the subnet, carry out following operation:
1: the current processing clock of initialization source is the present clock source of this network element, and current processing clock source section is the clock source section ID in this current clock source.Be provided with one tabulates in order to preserve all the clock sources, downstream on the section of clock source, place, current processing clock source temporarily.
2: the following operation of circulation:
3: if current processing clock source section ID then carries out and finishes greater than not having the member in the zero still interim tabulation; If current processing clock source section ID is greater than zero and in the tabulation member is arranged temporarily, the clock source section ID that setting is kept at all the clock sources, downstream in the interim tabulation is current processing clock source section ID, last clock source, downstream in the interim tabulation is set, first member in the interim tabulation is a clock source tail tag will, if current processing clock source section is not to become to encircle the reset clock source tail tag will in current processing clock source of Duan Ze, carries out and finish; Otherwise continue.
4: if current processing clock source is the clock source, then global clock source section ID is increased by 1, the clock source section ID that all clock sources, downstream in current processing clock source section ID and the interim tabulation are set is global clock source section ID, last clock source, downstream in the interim tabulation is set, first member in the promptly interim tabulation is a clock source tail tag will, carries out and finishes; Otherwise continue.
5: if current processing clock source equals clock source, a certain downstream in the interim tabulation, then global clock source section ID is increased by 1, the clock source section ID in all clock sources, downstream (comprising this clock source, downstream) that this clock source position, downstream begins in the tabulation is set to 0xFF+ global clock source section ID temporarily, and their clock source and clock source tail tag will is set, last clock source, downstream in the interim tabulation is set, first member in the promptly interim tabulation is a clock source tail tag will, carries out and finishes; Otherwise continue.
6: current processing clock source is kept in the interim tabulation, (this moment, current processing clock source was not the clock source, the upstream clock source is necessarily arranged), search the upstream clock source, it is this upstream clock source that current processing clock source is set, current processing clock source section ID is the clock source section ID in this upstream clock source, the present clock source that circulation execution in step 2 is handled all network elements;
7: discharge member in the interim tabulation, processing finishes.
To the present clock source of each network element in the subnet through after the as above operation, if the clock source section ID in a certain network element present clock source, represents then that this clock source is on a certain one-tenth ring section greater than 0xFF.
The inventive method utilization is tabulated temporarily, adopts recursion method to search the upstream network element clock source in current processing clock source.The operator need not to analyze lot of data, can in time catch the one-tenth ring mistake in subnet clock source, and in time carry out misarrangement, avoids causing subnet unusual owing to profiling error fails in time to catch clock source one-tenth ring mistake; Employing the present invention not only can see the one-tenth ring situation in the subnet, can also see the situation of organizing of the various clocks of subnet source section.
Description of drawings
Fig. 1 is the block diagram that adopts definition SDH clock source in this method;
Fig. 2 adopts this method to judge the flow chart of clock source Cheng Huan;
Fig. 3 is the detail flowchart of steps A among Fig. 2.
Embodiment
Below in conjunction with Fig. 1, Fig. 2, Fig. 3 this method is described in further detail:
Among Fig. 1 dotted line represent the clock source and course to, should all need carry out once at the present clock source of each network element from the step of committed step 2 beginning among Fig. 2.
Suppose that network element present clock source processing sequence is Ne1, Ne2, Ne3, Ne4, Ne5, Ne6, Ne7, Ne8, Ne9, Ne10, Ne11, Ne12, Ne13.Initialization global clock source section ID is 0, after carrying out initialization according to the clock Source Type, the clock source sign in Ne2, Ne6, Ne7 clock source wherein is set, the clock source in each network element clock source that resets, clock source tail tag will, the clock source section ID in each network element clock source is initialized as 0.Then the later step of committed step 2 is carried out in each network element clock source successively.
To Ne1 present clock source:
First circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, interim tabulation is for empty, and interim tabulation is put in the present clock source, and current processing clock source becomes the upstream clock source--Ne8 present clock source.To the present clock source of Ne8, carry out second circulation.
Second circulation: current processing clock source section ID is 0, non-clock source, current processing clock source, current processing clock source is not equal to clock source, arbitrary downstream in the interim tabulation, interim tabulation is put in Ne8 present clock source, and current processing clock source becomes the upstream clock source---Ne7 present clock source.To the present clock source of Ne7, carry out the 3rd circulation.
The 3rd circulation: current processing clock source section ID is 0, current processing clock source is the clock source, section ID adds 1 with the global clock source, and with the clock source section ID of global clock source section ID assignment to the present clock source of Ne1, Ne8 in the clock source section ID in Ne7 present clock source, the tabulation temporarily, the clock source tail tag will in the present clock source of Ne1 is set, end loop.
Through after top three circular treatment, the present clock source of Ne7, Ne8, Ne1 constitutes a clock source section, and its section ID is 1, and wherein Ne7 is the clock source, and Ne1 is a clock source tail.This moment, global clock source section ID was 1.
To Ne2 present clock source:
First circulation: because current processing clock source section ID is 0, current processing clock source is the clock source, and section ID adds 1 with the global clock source, and with the clock source section ID of global clock source section ID assignment to Ne2 present clock source, end loop.
Through after the top circular treatment, the clock source section ID in the present clock source of Ne2 is 2, and is the clock source of this clock source section 2.This moment, global clock source section ID was 2.
To Ne3 present clock source:
First circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, interim tabulation interim tabulation is put in Ne3 present clock source, and current processing clock source becomes the upstream clock source for empty---Ne2 present clock source.To the present clock source of Ne2, carry out second circulation.
Second circulation: current processing clock source section ID is 2, see the circular treatment result in " to Ne2 present clock source ", with the clock source section ID assignment in the Ne3 present clock source in the tabulation temporarily is current processing clock source section ID value 2, and the clock source tail tag will in Ne3 present clock source is set, the clock source tail tag will in the current processing clock of the Ne2 that resets source, end loop.
After top secondary cycle processing, in conjunction with the circular treatment result in " to Ne2 present clock source ", the present clock source of Ne2, Ne3 constitutes a clock source section, and its section ID is 2, and wherein Ne2 is the clock source, and Ne3 is a clock source tail.This moment, global clock source section ID was 2.
To Ne4 present clock source:
First circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, interim tabulation interim tabulation is put in Ne4 present clock source, and current processing clock source becomes the upstream clock source for empty---Ne3 present clock source.To the present clock source of Ne3, carry out second circulation.
Second circulation: current processing clock source section ID is 2, see the circular treatment result in " to Ne3 present clock source ", with the clock source section ID assignment in the Ne4 present clock source in the tabulation temporarily is current processing clock source section ID value 2, and the clock source tail tag will in Ne4 present clock source is set, the clock source tail tag will in the current processing clock of the Ne3 that resets source, end loop.
After top secondary cycle processing, in conjunction with the circular treatment result in " to Ne2 present clock source " and " to Ne3 present clock source ", the present clock source of Ne2, Ne3, Ne4 constitutes a clock source section, and its section ID is 2, wherein Ne2 is the clock source, and Ne4 is a clock source tail.This moment, global clock source section ID was 2.
To Ne5 present clock source:
First circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, interim tabulation interim tabulation is put in Ne5 present clock source, and current processing clock source becomes the upstream clock source for empty---Ne4 present clock source.To the present clock source of Ne4, carry out second circulation.
Second circulation: current processing clock source section ID is 2, see the circular treatment result in " to Ne4 present clock source ", with the clock source section ID assignment in the Ne5 present clock source in the tabulation temporarily is current processing clock source section ID value 2, and the clock source tail tag will in Ne5 present clock source is set, the clock source tail tag will in the current processing clock of the Ne4 that resets source, end loop.
After top secondary cycle processing, circular treatment result in conjunction with " to Ne2 present clock source ", " to Ne3 present clock source " and " to Ne4 present clock source ", the present clock source of Ne2, Ne3, Ne4, Ne5 constitutes a clock source section, its section ID is 2, wherein Ne2 is the clock source, and Ne5 is a clock source tail.This moment, global clock source section ID was 2.
To Ne6 present clock source:
First circulation: because current processing clock source section ID is 0, current processing clock source is the clock source, and section ID adds 1 with the global clock source, and with the clock source section ID of global clock source section ID assignment to Ne6 present clock source, end loop.
Through after the top circular treatment, the clock source section ID in the present clock source of Ne6 is 3, and the clock source of this clock source section 3.This moment, global clock source section ID was 3.
To Ne7 present clock source:
First circulation: because current processing clock source section ID is 1, end loop;
To Ne8 present clock source:
First circulation: because current processing clock source section ID is 1, end loop;
To Ne9 present clock source:
First circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, interim tabulation interim tabulation is put in Ne9 present clock source, and current processing clock source becomes the upstream clock source for empty---Ne7 present clock source.To the present clock source of Ne7, carry out second circulation.
Second circulation: current processing clock source section ID is 1, see the circular treatment result in " to Ne7 present clock source ", with the clock source section ID assignment in the Ne9 present clock source in the tabulation temporarily is current processing clock source section ID value 1, and the clock source tail tag will in Ne9 present clock source is set, the clock source tail tag will in the current processing clock of the Ne7 that resets source, end loop.
After top secondary cycle processing, in conjunction with the circular treatment result in " to Ne7 present clock source ", the present clock source of Ne7, Ne9 constitutes a clock source section, and its section ID is 1, and wherein Ne7 is the clock source, and Ne9 is a clock source tail.This moment, global clock source section ID was 3.
To Ne10 present clock source:
First circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, interim tabulation interim tabulation is put in Ne10 present clock source, and current processing clock source becomes the upstream clock source for empty---Ne13 present clock source.To the present clock source of Ne13, carry out second circulation.
Second circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, current processing clock source is not equal to clock source, arbitrary downstream in the interim tabulation, interim tabulation is put in Ne13 present clock source, and current processing clock source becomes the upstream clock source---Ne12 present clock source.To the present clock source of Ne12, carry out the 3rd circulation.
The 3rd circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, current processing clock source is not equal to clock source, arbitrary downstream in the interim tabulation, interim tabulation is put in Ne12 present clock source, and current processing clock source becomes the upstream clock source---Ne11 present clock source.To the present clock source of Ne11, carry out the 4th circulation.
The 4th circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, current processing clock source is not equal to clock source, arbitrary downstream in the interim tabulation, interim tabulation is put in Ne11 present clock source, and current processing clock source becomes the upstream clock source---Ne10 present clock source.To the present clock source of Ne10, carry out the 5th circulation.
The 5th circulation: because current processing clock source section ID is 0, non-clock source, current processing clock source, current processing clock source equals first member Ne10 present clock source in the interim tabulation, section ID adds 1 with the global clock source, and the clock source section ID assignment in the present clock source of Ne10, Ne13, Ne12, Ne11 is global clock source section ID+0xFF in will tabulating temporarily, and their clock source and clock source tail tag will, end loop is set.
Present clock source through Ne10, Ne11, Ne12, Ne13 after top five circular treatment constitutes an one-tenth ring section, and its section ID is 4+0xFF, and wherein each network element present clock source not only is the clock source but also be clock source tail.This moment, global clock source section ID was 4.
To Ne11 present clock source:
First circulation: because current processing clock source section ID is 4+0xFF, end loop;
To Ne12 present clock source:
First circulation: because current processing clock source section ID is 4+0xFF, end loop;
To Ne13 present clock source:
First circulation: because current processing clock source section ID is 4+0xFF, end loop;
Through after the above-mentioned processing to each network element present clock source, in Fig. 1, Ne7, Ne8, Ne1 constitute a clock source section (SectionID=1), and Ne7 is the clock source, and Ne1 is a clock source tail; Ne2, Ne3, Ne4, Ne5 constitute a clock source section (SectionID=2), and Ne2 is the clock source, and Ne5 is a clock source tail; Ne6 constitutes a clock source section (SectionID=3) separately; Ne7, Ne9 constitute a clock source section (SectionID=1), and Ne10, Ne11, Ne12, Ne13 constitute a clock source and become ring section (SectionID=255+4), and wherein each network element is the clock source, is again clock source tail.
Clock source on the clock source section of attention: SectionID=1 has: the present clock source of Ne7, Ne8, Ne1, Ne9, because their clock source is same, i.e. and the present clock source of Ne7.Clock source on the clock source section of SectionID=3 has only the present clock source of a Ne6, because Ne6 is invalid clock source.
Though the present invention only provides a preferred embodiment that the present invention is described,, under the condition that does not depart from judgement principle of the present invention, by revise, change, change, substitute and equivalence wherein a certain step method also within the scope of the invention.
Claims (2)
1. a method of judging clock source Cheng Huan in synchronous digital hierarchy transport is characterized in that, comprises the steps:
1.1) definition network element clock source:
If this network element clock source is not from upstream network element, then define the clock source of this network element clock source for all continuous downstream clock sources and courses, if network element clock Source Type is invalid clock, internal clock, external clock, then this network element clock source is the clock source;
If this network element clock source is last the clock source in the clock source and course of continuous downstream, then define the clock source tail of this network element clock source for all continuous downstream clock sources and courses;
All network elements between clock source, clock source tail and clock source, the clock source tail are clock source section;
1.2) segmentation is carried out according to the rule of step 1 definition in all network element clock sources in the subnet, give one of different clock source section ID number;
1.3) if the present clock source of some network elements is clock source on this clock source section on the section of a certain clock source, be again clock source tail, it is 0xFF+ clock source section ID that this clock source section ID then is set;
1.4) if all the clock sources on the section of a certain clock source or the clock source of some network element join end to end, then judge the clock source Cheng Huan of these network elements, constituted one-tenth ring section; If the clock source section ID in a certain network element present clock source, represents then that this clock source is therein on one one-tenth ring section greater than 0xFF.
2. according to the described method of in synchronous digital hierarchy transport, judging clock source Cheng Huan of claim 1, it is characterized in that described step 1.2) in further comprise the steps:
2.1) when the subnet initialization, a global clock source section ID is set and is initialized as 0, it is 0 that each network element present clock source section ID is set, according to transmitting the clock Source Type, judge whether each network element present clock source is the clock source, if then be set to clock source sign;
2.2) to the present clock source of each network element in the subnet, carry out following operation:
2.2.1) the current processing clock of initialization source is the present clock source of this network element, current processing clock source section ID is the clock source section ID in this current clock source, is provided with one and tabulates in order to preserve all the clock sources, downstream on the section of clock source, place, current processing clock source temporarily;
2.2.2) carry out following steps the present clock source of this network element handled: if 2.2.2.1) current processing clock source section ID is greater than zero, but do not have the member in the interim tabulation, then execution in step 2.2.2.6); If current processing clock source section ID is greater than zero, and in the interim tabulation member is arranged, the clock source section ID that setting is kept at all the clock sources, downstream in the interim tabulation is current processing clock source section ID, last clock source, downstream in the interim tabulation is set, first member in the promptly interim tabulation is a clock source tail tag will, if current processing clock source section is not to become to encircle the reset clock source tail tag will in current processing clock source of Duan Ze, execution in step 2.2.2.6); Otherwise continue;
2.2.2.2) if current processing clock source is the clock source, then global clock source section ID is increased by 1, the clock source section ID that all clock sources, downstream in current processing clock source section ID and the interim tabulation are set is global clock source section ID, last clock source, downstream in the interim tabulation is set, first member in the promptly interim tabulation is a clock source tail tag will, execution in step 2.2.2.6); Otherwise continue;
2.2.2.3) if current processing clock source equals clock source, a certain downstream in the interim tabulation, then global clock source section ID is increased by 1, with all clock sources, downstream of beginning, this clock source position, downstream in the tabulation temporarily, comprise this clock source, downstream, clock source section ID be set to 0xFF+ global clock source section ID, and their clock source and clock source tail tag will is set, last clock source, downstream in the interim tabulation is set, first member in the promptly interim tabulation is a clock source tail tag will, execution in step 2.2.2.6); Otherwise continue;
2.2.2.4) current processing clock source is kept in the interim tabulation, search the upstream clock source, it is this upstream clock source that current processing clock source is set, current processing clock source section ID is the clock source section ID in this upstream clock source;
2.2.2.5) repeat circulation step 2.2.2)
2.2.2.6) discharge member in the interim tabulation, execution in step 2.2);
2.3) the processing end.
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| CNB021507104A CN100369426C (en) | 2002-11-22 | 2002-11-22 | Method for judging clock source ring in sychronous digital transmission network |
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| CN1770701A (en) * | 2004-11-03 | 2006-05-10 | 华为技术有限公司 | Clock track realizing method in MESH network |
| CN109194435B (en) * | 2018-09-07 | 2020-11-24 | 瑞斯康达科技发展股份有限公司 | Method, system and terminal for avoiding digital synchronous network clock ring formation |
| CN112311575B (en) * | 2019-07-31 | 2022-06-03 | 烽火通信科技股份有限公司 | Clock ring forming detection method and system in optical transmission network management |
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| US5734687A (en) * | 1992-11-09 | 1998-03-31 | Nokia Telecommunications Oy | Hierarchical synchronization method and a telecommunications system employing message-based synchronization |
| CN1187272A (en) * | 1995-06-06 | 1998-07-08 | Gpt有限公司 | Synchronization in an SDH network |
| JP2000244436A (en) * | 1999-02-17 | 2000-09-08 | Fujitsu Ltd | Subordinate synchronization device and sdh device with the same |
| US6173023B1 (en) * | 1997-10-20 | 2001-01-09 | Fujitsu Limited | Synchronization equipment |
| CN1352500A (en) * | 2000-11-06 | 2002-06-05 | 深圳市中兴通讯股份有限公司 | Automatic clock line protecting method in implementing digital transmission group net |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5734687A (en) * | 1992-11-09 | 1998-03-31 | Nokia Telecommunications Oy | Hierarchical synchronization method and a telecommunications system employing message-based synchronization |
| CN1187272A (en) * | 1995-06-06 | 1998-07-08 | Gpt有限公司 | Synchronization in an SDH network |
| US6173023B1 (en) * | 1997-10-20 | 2001-01-09 | Fujitsu Limited | Synchronization equipment |
| JP2000244436A (en) * | 1999-02-17 | 2000-09-08 | Fujitsu Ltd | Subordinate synchronization device and sdh device with the same |
| CN1352500A (en) * | 2000-11-06 | 2002-06-05 | 深圳市中兴通讯股份有限公司 | Automatic clock line protecting method in implementing digital transmission group net |
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