CN100367150C - Time pulse adjusting device and method - Google Patents
Time pulse adjusting device and method Download PDFInfo
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- CN100367150C CN100367150C CNB2003101006810A CN200310100681A CN100367150C CN 100367150 C CN100367150 C CN 100367150C CN B2003101006810 A CNB2003101006810 A CN B2003101006810A CN 200310100681 A CN200310100681 A CN 200310100681A CN 100367150 C CN100367150 C CN 100367150C
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Abstract
The present invention provides a time pulse adjusting device and a method. The time pulse adjusting device is used for executing one overfrequency action. The time pulse adjusting device mainly comprises a temporary storage, a phase-locked loop and a control circuit, wherein the temporary storage is used for storing many time pulse signals; the phase-locked loop is coupled with the temporary storage to respectively output the time pulse signals; the control circuit is used for controlling the phase-locked loop to respectively and orderly execute the overfrequency action on each time pulse signals. The method comprises the following steps that the frequency of the first time pulse signal is gradually increased; when a host board can not normally work, the host board is reset, and the frequency of the first time pulse signal at that time, is recorded; after a preset safety value is subtracted from the frequency of the first time pulse signal, the frequency of the first time pulse signal is stored, wherein a time pulse wafer repeats the steps to orderly adjust the frequency of the time pulse signals.
Description
Technical field
The invention relates to a kind of technical field of motherboard overclocking, refer to that especially a kind of motherboard that is used for is to carry out the clock pulse adjusting gear and the method for overclocking action.
Background technology
General known personal host computer plate has a clock pulse wafer, with provide different clock pulses to the central processing unit on this motherboard (Central Processor Unit, CPU), use with other wafer and bus.Because each wafer all has the margin (tolerance) of considering its frequency of operation when design, thus overclocking action on the personal host computer plate, can be carried out, with the frequency of operation of raising system, and then the usefulness of elevator system.
Fig. 1 is the structural drawing of general personal host computer plate, and it comprises a central processing unit 110, a north bridge (north bridge) wafer 120, a south bridge (south bridge) wafer 130 and a clock pulse wafer 140.When carrying out the overclocking action as desire, set its inner Watch Dog Timer (watch dog timer) 141 prior to this clock pulse wafer 140, start this inside Watch Dog Timer 141 thereafter, carry out the overclocking action again, this clock pulse wafer 140 exports mainboard system to after an output clock pulse is improved some again, whether works as machine to check this mainboard system.
For example do on the central processing unit of this clock pulse wafer 140 with 100MHz to export this mainboard system again to after clock pulse CPU_CLK is increased to 101MHz.Simultaneously, this central processing unit 110 execution one Basic Input or Output System (BIOS) (Basic Input Output System, BIOS) program, with SCLK and SDATA signal via this south bridge wafer, and this Watch Dog Timer 141 of resetting.When if the CPU_CLK of 101MHz can accept, 110 of this central processing units can be before these Watch Dog Timer 141 timing end, this Watch Dog Timer 141 of resetting, 140 of this clock pulse wafers are made as 101MHz with a safe clock pulse FsafeMHz, this clock pulse wafer 140 is increased to 102MHz with the CPU_CLK of 101MHz again, and exports this mainboard system to.
When if the CPU_CLK of 102MHz is unacceptable, this moment is because this south bridge wafer can't have been exported correct SCLK and SDATA signal, this Watch Dog Timer 141 so can't reset, so this Watch Dog Timer 141 can be ended in timing, this moment, 140 of this clock pulse wafers were made as FsafeMHz (101MHz) with this CPU_CLK, restarted this mainboard system.
Yet, known clock pulse wafer 140 is when overclocking is moved, the various output time pulse signals that it provided are to interrelate, if that is when adjusting Accelerated Graphics Port clock pulse AGP_CLK failure, also allow other output time pulse signal (for example CPU_CLK) can't continue to carry out the overclocking action simultaneously.Therefore, wafer, bus or the other electron component of the time pulse signal of all reception clock pulse wafer 140 outputs all can only operate on the work time pulse to the minimum element of the frequency margin of time pulse signal.And these Watch Dog Timer 141 timing times are oversize, make when this clock pulse wafer 140 is carried out continuous overclocking, and need many times of cost, therefore, the design of the frequency multiplying method of known clock pulse wafer still has many disappearances and gives improved necessity.
Summary of the invention
The object of the present invention is to provide a kind of clock pulse adjusting gear and method, it can carry out the overclocking action respectively to the different time pulse signals of clock pulse wafer output, and reduces the clock pulse wafer and carry out the required time of continuous overclocking.
According to purpose of the present invention, a kind of clock pulse method of adjustment is proposed, be used to make a clock pulse wafer to carry out overclocking action, this clock pulse wafer is arranged on the motherboard, and in order to export a plurality of time pulse signals, this method comprises:
Increase progressively the frequency of one first time pulse signal;
When this motherboard can't operate as normal, this motherboard of resetting, and the record frequency of this first time pulse signal at that time; And
After the frequency of this first time pulse signal deducted a default safety value, store the frequency of this first time pulse signal;
Wherein, this clock pulse wafer repeats above-mentioned steps, to adjust the frequency of these a plurality of time pulse signals in regular turn.
This clock pulse wafer is adjusted the frequency of these a plurality of time pulse signals earlier in regular turn with one first order, adjust the frequency of these a plurality of time pulse signals more in regular turn with one second order.
Also comprise: whether frequency that simultaneously will these a plurality of time pulse signals increases by a particular value, to test this motherboard still can operate as normal.
According to another object of the present invention, a kind of clock pulse adjusting gear is proposed, be used to carry out overclocking action, a this clock pulse adjusting gear and a central processing unit and a south bridge wafer couple, and this clock pulse adjusting gear, this central processing unit and this south bridge wafer system are arranged on the motherboard, and this clock pulse adjusting gear mainly comprises:
One working storage is in order to store a plurality of time pulse signals;
One phase-locked loop couples with this working storage, in order to export these a plurality of time pulse signals respectively; And
One control circuit is carried out this overclocking action to every this time pulse signal respectively in regular turn in order to control this phase-locked loop.
When desire is carried out this overclocking action to one first time pulse signal, this working storage is exported the predeterminated frequency of this first time pulse signal to this phase-locked loop, and when this first time pulse signal being carried out the action of this overclocking when this motherboard can't operate as normal, the frequency of this first time pulse signal is at that time deducted after the default safety value, be stored in this working storage.
According to the serial bus signal of this control circuit detecting, and judge that this motherboard can't operate as normal less than this south bridge wafer output.
This clock pulse adjusting gear also comprises a timer, couples with this control circuit, by a serial bus signal this timer of can't resetting of this south bridge wafer of detecting, and judges that this motherboard can't operate as normal.
These a plurality of time pulse signals export a central processing unit or an AGP bus or a pci bus respectively to.
This control circuit is carried out this overclocking action to these a plurality of time pulse signals in regular turn with one first order earlier, in regular turn these a plurality of time pulse signals is carried out this overclocking action with one second order again.
This control circuit simultaneously will these a plurality of time pulse signals frequency increase by a particular value, to test this motherboard whether still can operate as normal.
Description of drawings
Fig. 1 is the application system structural drawing of clock pulse method of adjustment of the present invention.
Fig. 2 adjusts the calcspar of wafer for clock pulse of the present invention.
Fig. 3 is the process flow diagram of clock pulse method of adjustment of the present invention.
Embodiment
The applied environment of relevant clock pulse adjusting gear of the present invention and method, still please refer to the structural drawing of motherboard shown in Figure 1, in the present embodiment, motherboard comprises a central processing unit 110, a north bridge wafer 120, a south bridge wafer 130 and a clock pulse wafer 140, and this central processing unit 110 is connected to this north bridge wafer 120 via a regional bus 111.This north bridge wafer 120 is connected to this south bridge wafer 130 via a pci bus 122, and and has an Accelerated Graphics Port (Accelerated Graphics Port, AGP) 121.130 of this south bridge wafers are via this clock pulse wafer 140 of SM serial bus access.This SM serial bus is made up of a SCLK and SDATA signal.
Aforementioned clock pulse wafer 140 is as a clock pulse adjusting gear, Fig. 2 shows the calcspar of this clock pulse wafer 140, and it has a Watch Dog Timer 141, a PLL device the 142, the 1st to N working storage (N is a positive integer) 143, one control circuit 144 and a flag 145.This PLL device 142 is in order to produce N group output time pulse signal, the 1st to N working storage 143 for this PLL device 142 according to its value corresponding this N group output time pulse signal (CPU_CLK for example that produces, AGP_CLK, PCI_CLK ...), so that the work time pulse of central processing unit 110, Accelerated Graphics Port 121 and pci bus 122 etc. on this motherboard to be provided respectively, the 1st is set to a predetermined value respectively to N working storage 143 when power supply is started shooting.
These control circuit 144 controls the 1st to N working storage 143 moves to carry out overclocking.This Watch Dog Timer 141 provides a clocking capability, and south bridge wafer 130 can be via SCLK and SDATA signal, with this flag 145 of access and this Watch Dog Timer 141.
When clock pulse wafer 140 carried out overclocking, this flag 145 was set as 0, and when this clock pulse wafer 140 was finished the overclocking action, this flag 145 was set as 1.So when desire was carried out the overclocking action, central processing unit 110 was carried out a bios program, to read flag 145 in this clock pulse wafer 140 by the serial bus of this south bridge wafer by north bridge wafer 120.If flag 145 is 0 o'clock, represent that this overclocking action do not finish as yet, this bios program continues to read this flag 145, this moment, the SCLK and the SDATA signal of serial bus also continued to exist, if flag 145 is 1 o'clock, represent that this overclocking action finishes, this bios program finishes the action of reading this flag 145.Carry out in this overclocking course of action and adjust wafer 140 at this clock pulse, if electronic equipment on this motherboard is arranged because of overclocking excessively can't operate as normal the time, this south bridge wafer 130 can't produce SCLK and SDATA signal, and make this clock pulse wafer 140 be able to learn by judging SCLK and SDATA signal whether to exist whether operate as normal of motherboard.
Above stated specification is with this flag 145 of this bios program access, and makes this south bridge wafer 130 produce SCLK and SDATA signal.So can also this Watch Dog Timer 141 of this bios program access, and produce SCLK and SDATA signals by this south bridge wafer 130, according in order to judge whether operate as normal of this motherboard.
Fig. 3 is the process flow diagram of clock pulse method of adjustment of the present invention, as shown in the figure, it carries out overclocking according to the pairing i output time pulse signal adjustment of i=1-N ordered pair i working storage, at first, in step S301, (for example: CPU_CLK) carry out the overclocking action judge whether the i time pulse signal, if not, then execution in step S315 is supplied to corresponding electronic equipment (CPU) on the motherboard to be driven this PLL device 142 by control circuit 144 values according to this i working storage with the output time pulse signal.If in step S303, judge whether the value of i working storage is its predetermined value (100MHz) again.If represent this i time pulse signal overclocking not as yet, so execution in step S305 carries out overclocking with a beginning to the i time pulse signal.
In step S305, the value of this i working storage is increased progressively (for example increasing by an increment size 1MHz), and these control circuit 144 values according to this i working storage drive this PLL device 142, with the frequency of heightening corresponding output time pulse signal (CPU_CLK) to 101MHz.Wherein, this increment size can be a preset value or the user is set.Step S306 judges whether SCLK and SDATA signal exist, when if the output time pulse signal (CPU_CLK) of this 101MHz still can make each electronic equipment operate as normal on this motherboard, then this south bridge wafer 130 still can produce SCLK and SDATA signal, the expression motherboard is operate as normal still, so resumes step S305, value with this i working storage increases progressively (for example increasing by an increment size 1MHz) again, this control circuit 144 is again according to the value of this i working storage, drive this PLL device 142, to 102MHz, so repeatedly increase the frequency of heightening this output time pulse signal (CPU_CLK) with the frequency of heightening corresponding output time pulse signal (CPU_CLK).
And if the output time pulse signal (CPU_CLK) of this 102MHz makes central processing unit 110 on this motherboard can't operate as normal the time, then this south bridge wafer 130 can't produce SCLK and SDATA signal, so execution in step S309, with the value (102MHz) that keeps this i working storage, and produce a replacement signal with each electronic equipment on this motherboard of resetting by clock pulse wafer 140.
Execution in step S301 again after resetting in step S301, moves owing to before i time pulse signal carried out overclocking, is not to be its predetermined value (100MHz) so will judge the value (102MHz) of i working storage in step S303, so execution in step S311.
In step S311, because the output time pulse signal (CPU_CLK) of this 102MHz can make the central processing unit 110 on this motherboard can't operate as normal, so the value of this i working storage (for example: 1MHz) is reduced by a default safety value, this control circuit 144 is just according to the value of this i working storage, drive this PLL device 142, with the frequency of turning down corresponding output time pulse signal (CPU_CLK) to 101MHz, to guarantee to make central processing unit 110 operate as normal on this motherboard, in view of the above, finish overclocking to i output time pulse signal, (for example: the i+1 time pulse signal) carry out overclocking (step S313), continue again until the overclocking of finishing all output time pulse signals to next output time pulse signal.
Because the running clock pulse frequency of wafer, bus or other electron component on the motherboard might be not independent separately, and have relevant mutually situation again.Therefore, when this control circuit 144 after respectively in regular turn to the 1st to N output time pulse signal overclocking, can repeat above-mentioned steps again, distinguish again, and, the 1st to N output time pulse signal carried out the overclocking action preferably with different orders.Afterwards, also can be respectively increase by a particular value to the N working storage, carry out aforesaid overclocking step again the 1st.Mode to be heightening the frequency of corresponding output time pulse signal thus, and then tests this motherboard maximum operation frequency.
As shown in the above description, the technology of the present invention is in regular turn each electronic equipment on the motherboard to be carried out overclocking respectively, it is different from known technology is that output time pulse signal with all electronic equipments carries out overclocking together, and for example cause: when adjusting the AGP_CLK failure, also allow other output time pulse signal (for example CPU_CLK) also can't continue to carry out the overclocking action.And the technology of the present invention is to carry out the overclocking action to each output time pulse signal respectively, and reaches this motherboard frequency optimum traffic.Simultaneously, known technology uses this Watch Dog Timer 141 to judge whether operate as normal of this motherboard, but these Watch Dog Timer 141 timing times are oversize, make when this clock pulse wafer 140 is carried out continuous overclocking need many times of cost, whether the present invention is existed by the serial bus signal that detects this south bridge wafer 130 (SCLK and SDATA signal), and judge whether operate as normal of this motherboard, institute's spended time is few far beyond known technology, and this can save many times when carrying out continuous overclocking.
The foregoing description only is to give an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (9)
1. a frequency adjusting method is used to make a clock pulse wafer to carry out overclocking action, and this clock pulse wafer is arranged on the motherboard, and in order to export a plurality of time pulse signals, this method comprises:
Increase progressively the frequency of one of them time pulse signal of these a plurality of time pulse signals;
When this motherboard can't operate as normal, this motherboard of resetting, and the record frequency of one of them time pulse signal of these a plurality of time pulse signals at that time; And
After the frequency of one of them time pulse signal of these a plurality of time pulse signals deducted a default safety value, store the frequency of one of them time pulse signal of these a plurality of time pulse signals;
This clock pulse wafer repeats above-mentioned steps, to adjust the frequency of these a plurality of time pulse signals according to one first order; And
This motherboard is according to the frequency work of these stored a plurality of time pulse signals.
2. the method for claim 1 is characterized in that, this clock pulse wafer is adjusted the frequency of these a plurality of time pulse signals earlier in regular turn with this first order, adjusts the frequency of these a plurality of time pulse signals more in regular turn with one second order.
3. whether the method for claim 1 is characterized in that, also comprises: by a serial bus signal of the south bridge wafer output of detecting this motherboard, to test this motherboard still can operate as normal.
4. frequency adjusting device, be used to carry out overclocking action, a this clock pulse adjusting gear and a central processing unit and a south bridge wafer couple, and this clock pulse adjusting gear, this central processing unit and this south bridge wafer be arranged on the motherboard, and this clock pulse adjusting gear mainly comprises:
One working storage, in order to store a plurality of numerical value, these a plurality of numerical value are the frequency of corresponding a plurality of time pulse signals respectively;
One phase-locked loop, in order to respectively according to this a plurality of numerical value that are stored in this working storage to export these a plurality of time pulse signals; And
One control circuit is carried out the action of this overclocking obtaining a new time pulse signal to these a plurality of time pulse signals in order to control this phase-locked loop respectively with one first order, and will be stored into corresponding to the numerical value of this new time pulse signal in this working storage.
5. frequency adjusting device as claimed in claim 4, it is characterized in that, when desire is carried out this overclocking action to one first time pulse signal, this working storage is exported the predeterminated frequency of this first time pulse signal to this phase-locked loop, and when this first time pulse signal being carried out the action of this overclocking when this motherboard can't operate as normal, the frequency of this first time pulse signal is at that time deducted after the default safety value, to obtain this new time pulse signal, and will be stored into corresponding to the numerical value of this new time pulse signal in this working storage, this motherboard is operated according to the numerical value that is stored into this working storage.
6. frequency adjusting device as claimed in claim 5 is characterized in that, according to the serial bus signal of this control circuit detecting less than this south bridge wafer output, and judges that this motherboard can't operate as normal.
7. frequency adjusting device as claimed in claim 5, it is characterized in that this clock pulse adjusting gear also comprises a timer, couple with this control circuit, by a serial bus signal this timer of can't resetting of this south bridge wafer of detecting, and judge that this motherboard can't operate as normal.
8. frequency adjusting device as claimed in claim 4 is characterized in that, these a plurality of time pulse signals export a central processing unit, an AGP bus and a pci bus respectively to.
9. frequency adjusting device as claimed in claim 4 is characterized in that, this control circuit is carried out this overclocking action to these a plurality of time pulse signals in regular turn with this first order earlier, in regular turn these a plurality of time pulse signals is carried out this overclocking action with one second order again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101006810A CN100367150C (en) | 2003-10-13 | 2003-10-13 | Time pulse adjusting device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101006810A CN100367150C (en) | 2003-10-13 | 2003-10-13 | Time pulse adjusting device and method |
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| Publication Number | Publication Date |
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| CN1607486A CN1607486A (en) | 2005-04-20 |
| CN100367150C true CN100367150C (en) | 2008-02-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2003101006810A Expired - Lifetime CN100367150C (en) | 2003-10-13 | 2003-10-13 | Time pulse adjusting device and method |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101561691B (en) * | 2008-04-15 | 2012-05-23 | 联阳半导体股份有限公司 | Method and device for regulating system frequency of storage device |
| CN110753255B (en) * | 2018-07-24 | 2022-07-29 | 扬智科技股份有限公司 | Transmission stream receiving device and clock frequency setting method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6385735B1 (en) * | 1997-12-15 | 2002-05-07 | Intel Corporation | Method and apparatus for limiting processor clock frequency |
| CN1368684A (en) * | 2001-01-31 | 2002-09-11 | 伟格科技股份有限公司 | Frequency multiplying method and system for CPU |
| CN1372189A (en) * | 2001-02-26 | 2002-10-02 | 微星科技股份有限公司 | Method for instant raising CPU frequency |
| CN1379327A (en) * | 2001-04-06 | 2002-11-13 | 华邦电子股份有限公司 | Device and method for automatically measuring stable working frequency |
-
2003
- 2003-10-13 CN CNB2003101006810A patent/CN100367150C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6385735B1 (en) * | 1997-12-15 | 2002-05-07 | Intel Corporation | Method and apparatus for limiting processor clock frequency |
| CN1368684A (en) * | 2001-01-31 | 2002-09-11 | 伟格科技股份有限公司 | Frequency multiplying method and system for CPU |
| CN1372189A (en) * | 2001-02-26 | 2002-10-02 | 微星科技股份有限公司 | Method for instant raising CPU frequency |
| CN1379327A (en) * | 2001-04-06 | 2002-11-13 | 华邦电子股份有限公司 | Device and method for automatically measuring stable working frequency |
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| CN1607486A (en) | 2005-04-20 |
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