CN100364050C - Method for preapring nano size pit on gallium arsenide substrate - Google Patents
Method for preapring nano size pit on gallium arsenide substrate Download PDFInfo
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- CN100364050C CN100364050C CNB2005100843573A CN200510084357A CN100364050C CN 100364050 C CN100364050 C CN 100364050C CN B2005100843573 A CNB2005100843573 A CN B2005100843573A CN 200510084357 A CN200510084357 A CN 200510084357A CN 100364050 C CN100364050 C CN 100364050C
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Abstract
This invention relates to a method for preparing nm pits on a GaAs substrate including the following steps: 1, taking a semi-insulating GaAs single wafer as the substrate, 2, heterogeneously and epitaxially growing InAs strain self-assembled nm points, 3, extending the GaAs thin layer to cover part of said InAs nm points, 4, annealing for the first time, 5, reducing the temperature of the substrate to below 400deg.C, 6, rising the temperature of the substrate to 500-530deg.C, 7, annealing the second time to form nm pits on the substrate.
Description
Technical field
The invention provides a kind of method of preapring nano size pit on gallium arsenide substrate, be meant especially a kind ofly partly to cover the indium arsenide nano dot, and, heat up again after the cooling then, then Tui Huo growing method at high annealing with GaAs.
Background technology
Semi-conducting material and nano material are two big emphasis and hot fields of present material science.The Quantum Properties of nano material and the characteristic of being with of semi-conducting material are combined, and are a very important branch of semiconductor physics fields, also are important channels of making the new function device.The photoelectric device that utilizes the low dimension semiconductor heterojunction material to make, as laser, the performance of detector obtains swift and violent raising, and comes into the market rapidly, is widely used.Therefore, the preparation nano semiconductor material is to still all having crucial meaning to practical application to material science.
The preparation nano semiconductor material usually need epitaxial growth on patterned substrate.Behind the hole of preparing nano-scale on the gallium arsenide substrate, we have obtained a gallium arsenide patternedization substrate that is thick with the nano-scale hole, and further epitaxial growth has the nanostructure of unique optical properties on this substrate, as nano dot.Because these pittings are to the influence of gallium arsenide surface stress distribution, further epitaxially grown nano dot is expected to ordering growth under its surfacial pattern influence.
Up to now, the method for preapring nano size pit on gallium arsenide substrate mainly is the method for direct photoetching, and this method efficient is low, introduces dislocation defects easily, and the cost height.The method of the preapring nano size pit on gallium arsenide substrate that the present invention proposes has been utilized self-organizing method, compares with the method for direct photoetching, and the make efficiency height, defective is few, and cost is low, does not still have report at present both at home and abroad.
Summary of the invention
The object of the present invention is to provide a kind of method of preapring nano size pit on gallium arsenide substrate, its indium arsenide nano dot alternating temperature annealing method is the indium arsenide nano dot of growing on gallium arsenide substrate earlier, and part covers the method that changes temperature and annealing then again; Its advantage is the make efficiency height, and defective is few, and cost is low.Gallium arsenide substrate with the preparation of indium arsenide nano dot alternating temperature annealing method can be as the patterned substrate of making novel nano semiconductor material.
The technical scheme of claimed invention
The method of a kind of preapring nano size pit on gallium arsenide substrate of the present invention is characterized in that, comprises the steps:
Step 1: with the semi-insulating GaAs single-chip is substrate;
Step 2: heteroepitaxial growth indium arsenide strain self-assembled nanometer point;
Step 3: the epitaxial GaAs thin layer makes its part cover above-mentioned indium arsenide nano dot;
Step 4: annealing for the first time, annealing temperature is 500-530 ℃;
Step 5: underlayer temperature is cooled to below 400 ℃;
Step 6: underlayer temperature is warmed up to 500-530 ℃;
Step 7: annealing for the second time forms the nano-scale hole on gallium arsenide substrate.
Wherein the temperature of annealing is 500-530 ℃ for the first time.
Wherein the deposition of heteroepitaxy indium arsenide is the 1.7-3 molecular monolayer.
Wherein the temperature of heteroepitaxy indium arsenide is 500-530 ℃.
Wherein the thickness of GaAs thin layer is 1-5nm.
Wherein annealing time is 1-3 minute for the first time.
Wherein annealing time is 1-5 minute for the second time.
The significant effect that is had is compared in invention with background technology
The method for preparing nano-scale hole on the gallium arsenide substrate with photoetching is compared, and the sample of indium arsenide nano dot alternating temperature annealing method growth is to utilize the preparation of strain self assembly effect in molecular beam epitaxy system, so method is simple, the make efficiency height, and defective is few, and cost is low.Gallium arsenide patternedization substrate with the preparation of indium arsenide nano dot alternating temperature annealing method is expected to be used to make novel nano semiconductor material.
Description of drawings
For further specifying feature of the present invention and technical scheme, below in conjunction with embodiment and accompanying drawing the present invention is done a detailed description, wherein:
Fig. 1 is the atomic force microscope picture in the nano-scale hole on the gallium arsenide substrate of indium arsenide nano dot alternating temperature annealing method preparation;
Fig. 2 is the sectional view of a typical nano-scale hole along [1-10] and [110] direction.
Embodiment
A kind of method of preapring nano size pit on gallium arsenide substrate is characterized in that, comprises the steps:
Step 1: with the semi-insulating GaAs single-chip is substrate;
Step 2: heteroepitaxial growth indium arsenide strain self-assembled nanometer point, this is heterogeneous
The deposition of extension indium arsenide is the 1.7-3 molecular monolayer, this heteroepitaxy indium arsenide
Temperature be 500-530 ℃;
Step 3: the epitaxial GaAs thin layer makes its part cover above-mentioned indium arsenide nanometer
Point, the thickness of this GaAs thin layer are 1-5nm;
Step 4: annealing for the first time, this temperature of annealing for the first time is 500-5
30 ℃, this, annealing time was 1-3 minute first time;
Step 5: underlayer temperature is cooled to below 400 ℃;
Step 6: underlayer temperature is warmed up to 500-530 ℃;
Step 7: annealing for the second time, this second time, annealing time was 1-5 minute, forms nano-scale and cheat (as shown in Figure 1 and Figure 2) on gallium arsenide substrate.
Embodiment
(1) capital equipment of realization invention
Molecular beam epitaxy system
Oil-sealed rotary pump+diffusion vacuum pump (or other vacuum equipment)
Temperature control system
(2) according to the concrete condition of growth apparatus, the growing technology route is suitably adjusted.
Example
(1) capital equipment of realization invention
The Riber32 molecular beam epitaxy system
Oil-sealed rotary pump+diffusion vacuum pump (or other vacuum equipment)
Temperature control system
(2) be substrate with semi-insulating GaAs (001) monocrystalline;
(3) utilize molecular beam epitaxy system epitaxial growth 200nm GaAs buffer layer on gallium arsenide substrate;
(4) exist, 500 ℃, 4.0 * 10
-6The As of Torr
2Heteroepitaxial growth 2.7 molecular monolayer (ML) indium arsenide in the atmosphere, the high-energy electron diffiraction systematic observation is to the formation of self-assembled nanometer point;
(5) the GaAs thin layer of epitaxial thickness 2nm makes its part cover above-mentioned indium arsenide nano dot;
(6) 500 ℃ of annealing 40 seconds;
(7) underlayer temperature is cooled to 400 ℃;
(8) underlayer temperature is warmed up to 500 ℃;
(9) 500 ℃ of annealing 120 seconds.
On gallium arsenide substrate, form nano-scale hole (as shown in Figure 1 and Figure 2).
Claims (6)
1. the method for a preapring nano size pit on gallium arsenide substrate is characterized in that, comprises the steps:
Step 1: with the semi-insulating GaAs single-chip is substrate;
Step 2: heteroepitaxial growth indium arsenide strain self-assembled nanometer point;
Step 3: the epitaxial GaAs thin layer makes its part cover above-mentioned indium arsenide nano dot;
Step 4: annealing for the first time, annealing temperature is 500-530 ℃;
Step 5: underlayer temperature is cooled to below 400 ℃;
Step 6: underlayer temperature is warmed up to 500-530 ℃;
Step 7: annealing for the second time forms the nano-scale hole on gallium arsenide substrate.
2. the method for preapring nano size pit on gallium arsenide substrate according to claim 1 is characterized in that, wherein the deposition of heteroepitaxial growth indium arsenide is the 1.7-3 molecular monolayer.
3. the method for preapring nano size pit on gallium arsenide substrate according to claim 1 is characterized in that, wherein the temperature of heteroepitaxial growth indium arsenide is 500-530 ℃.
4. the method for preapring nano size pit on gallium arsenide substrate according to claim 1 is characterized in that, wherein the thickness of GaAs thin layer is 1-5nm.
5. the method for preapring nano size pit on gallium arsenide substrate according to claim 1 is characterized in that, wherein annealing time is 1-3 minute for the first time.
6. the method for preapring nano size pit on gallium arsenide substrate according to claim 1 is characterized in that, wherein annealing time is 1-5 minute for the second time.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100843573A CN100364050C (en) | 2005-07-19 | 2005-07-19 | Method for preapring nano size pit on gallium arsenide substrate |
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| CNB2005100843573A CN100364050C (en) | 2005-07-19 | 2005-07-19 | Method for preapring nano size pit on gallium arsenide substrate |
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| CN1901139A CN1901139A (en) | 2007-01-24 |
| CN100364050C true CN100364050C (en) | 2008-01-23 |
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| CN101409229B (en) * | 2007-10-12 | 2012-01-04 | 台达电子工业股份有限公司 | Epitaxial substrate and manufacturing method thereof, and method for manufacturing LED device |
| CN112420511A (en) * | 2020-11-23 | 2021-02-26 | 陕西科技大学 | Annealing treatment method of GaAs substrate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003318114A (en) * | 2002-04-23 | 2003-11-07 | Sumitomo Mitsubishi Silicon Corp | Epitaxial wafer manufacturing method and epitaxial wafer |
| CN1489189A (en) * | 2002-09-04 | 2004-04-14 | Lg. ������Lcd��ʽ���� | Method for making platfond-shape film transistor with low-temp. polysilicon |
| US20050051861A1 (en) * | 2003-09-09 | 2005-03-10 | Industrial Technology Research Institute | Avalanche photo-detector with high saturation power and high gain-bandwidth product |
| US6872970B2 (en) * | 2001-10-10 | 2005-03-29 | Cambridge Display Technology Limited | Photoresponsive devices |
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- 2005-07-19 CN CNB2005100843573A patent/CN100364050C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6872970B2 (en) * | 2001-10-10 | 2005-03-29 | Cambridge Display Technology Limited | Photoresponsive devices |
| JP2003318114A (en) * | 2002-04-23 | 2003-11-07 | Sumitomo Mitsubishi Silicon Corp | Epitaxial wafer manufacturing method and epitaxial wafer |
| CN1489189A (en) * | 2002-09-04 | 2004-04-14 | Lg. ������Lcd��ʽ���� | Method for making platfond-shape film transistor with low-temp. polysilicon |
| US20050051861A1 (en) * | 2003-09-09 | 2005-03-10 | Industrial Technology Research Institute | Avalanche photo-detector with high saturation power and high gain-bandwidth product |
Non-Patent Citations (2)
| Title |
|---|
| 半导体纳米结构的可控生长. 王占国.人工晶体学报，第31卷第3期. 2002 * |
| 纳米半导体材料的制备技术. 王占国.微纳电子技术，第1期. 2002 * |
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