CN100361014C - Liquid crystal display panel, active element array substrate and its mfg. method - Google Patents
Liquid crystal display panel, active element array substrate and its mfg. method Download PDFInfo
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- CN100361014C CN100361014C CNB2005100719190A CN200510071919A CN100361014C CN 100361014 C CN100361014 C CN 100361014C CN B2005100719190 A CNB2005100719190 A CN B2005100719190A CN 200510071919 A CN200510071919 A CN 200510071919A CN 100361014 C CN100361014 C CN 100361014C
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Abstract
The present invention relates to a liquid crystal display panel, an active element array basal plate and a manufacturing method of the active element array basal plate. The active element array basal plate comprises a basal plate, scanning wires, data wires, picture element units and dielectric layers, wherein the scanning wires are arranged on the basal plate; the data wires are arranged on the basal plate; the picture element unit units and the dielectric layers are arranged on the basal plate; the picture element units are electrically connected with the corresponding scanning wires and the data wires; each picture element unit comprises an active element and a picture element electrode which is electrically connected with the active element, and each picture element electrode is provided with a plurality of first slits. In addition, the dielectric layers are covered on the first slits, and are provided with a plurality of second slits for exposing parts of regions of each picture element electrode.
Description
Technical field
The present invention relates to a kind of display panels (LCD panel), particularly relate to a kind of multi-field vertical assigned LCD panel (Multi-domain Vertical Alignment-LCD, MVA-LCDpanel).
Background technology
Existing market all develops towards height contrast (contrast ratio), the counter-rotating of no GTG (grays cale inversion), high brightness (brightness), high color saturation (color saturation), rapid reaction (response) and wide viewing angle directions such as (viewing angle) for Thin Film Transistor-LCD (TFT-LCD).Common wide viewing angle technology comprises at present: stable twisted nematic liquid crystal (TN) adds view film (wide viewing film), copline suitching type (In-Plane Switching, IPS) LCD, limit suitching type (fringe fieldswitching) LCD and multidomain vertical alignment type (MVA) LCD.With the multi-field vertical assigned LCD panel is example, it can be by some alignment pattern (alignment patterning), as orientation protrusion (alignment protrusion) or slit (slit), so that the liquid crystal molecule in each picture element is multi-direction arrangement, and then obtaining several different orientation fields (domain).After will being specified in relevant for the detailed structure of multi-field vertical assigned LCD panel.
Fig. 1 and Fig. 1 ' illustrate sectional view and the vertical view into a kind of traditional multifield vertical directional liquid crystal display panel respectively.Please refer to Fig. 1, traditional multifield vertical directional liquid crystal display panel 100 comprises thin-film transistor array base-plate 110, colored optical filtering substrates 120 and liquid crystal layer 130.Wherein, liquid crystal layer 130 is to be disposed between thin-film transistor array base-plate 110 and the colored optical filtering substrates 120.
Please be simultaneously with reference to Fig. 1 and Fig. 1 ', in multifield vertical directional liquid crystal display panel 100, thin-film transistor array base-plate 110 comprises substrate 112, plurality of scanning wirings 114 and many data wirings 116 and a plurality of picture elements unit 118.Wherein, scan wiring 114, data wiring 116 and picture element unit 118 all are disposed on the substrate 112, and scan wiring 114, data wiring 116 are and corresponding picture element unit 118 electrically connects.In addition, picture element unit 118 comprises thin film transistor (TFT) 118a and pixel electrode 118b, and wherein pixel electrode 118b electrically connects with thin film transistor (TFT) 118a, and pixel electrode 118b has slit S1.
Shown in Fig. 1 and Fig. 1 ', colored optical filtering substrates 120 comprises substrate 122, colored filter film 124, common electrode 126 and a plurality of orientation protrusion P.Wherein, colored filter film 124 is to be disposed on the substrate 122, and common electrode 126 is to be disposed on the colored filter film 124, and orientation protrusion P is disposed on the common electrode 126.It should be noted that slit S1 on the thin-film transistor array base-plate 110 and the orientation protrusion P on the colored optical filtering substrates 120 are in order to LCD alignment, to form multiple field (multi-domain) in multifield vertical directional liquid crystal display panel 100.
Fig. 2 and Fig. 2 ' illustrate sectional view and the vertical view into the traditional multifield vertical directional liquid crystal display panel of another kind respectively.The multifield vertical directional liquid crystal display panel 100 that is illustrated among the multifield vertical directional liquid crystal display panel 100 ' that is illustrated among Fig. 2 and Fig. 1 is similar, and only main difference is the design of colored optical filtering substrates 120 '.Can know by Fig. 2 and Fig. 2 ' and to learn that colored optical filtering substrates 120 ' comprises substrate 122, colored filter film 124 and common electrode 126.Wherein, colored filter film 124 is to be disposed on the substrate 122, and common electrode 126 is to be disposed on the colored filter film 124, and common electrode 126 has a plurality of slit S2.Herein, slit S1 on the thin-film transistor array base-plate 110 and the slit S2 on the colored optical filtering substrates 120 ' equally can be in order to LCD alignment, to form multiple field (multi-domain) in multifield vertical directional liquid crystal display panel 100 '.
In above-mentioned multifield vertical directional liquid crystal display panel, the contraposition accurately to group time of thin-film transistor array base-plate and colored optical filtering substrates, otherwise the distance between the alignment pattern (slit, orientation protrusion) can't accurately be controlled.When the problem of mis-alignment (mis-alignment) took place between the alignment pattern, the reaction time of multifield vertical directional liquid crystal display panel and visual angle will be affected, even problems such as image residue might take place.
Summary of the invention
The objective of the invention is to, a kind of active component array base board of new structure is provided, technical matters to be solved is to make its slit with two kinds of different alignment functions (alignment function), thereby is suitable for practicality more.
Another object of the present invention is to, a kind of display panels of new structure is provided, technical matters to be solved is to make its display quality not be vulnerable to the influence to the group precision of substrate, thereby is suitable for practicality more.
A further object of the present invention is, a kind of manufacture method of active component array base board of and existing process-compatible is provided, thereby is suitable for practicality more.
The present invention proposes a kind of active component array base board, and it comprises substrate, be disposed at scan wiring on the substrate, be disposed at data wiring on the substrate, be disposed at the picture element unit on the substrate and be disposed at dielectric layer on the substrate.Wherein, the picture element unit is to electrically connect with corresponding scan wiring and data wiring, and each picture element unit comprises active member and the pixel electrode that electrically connects with this active member, and each pixel electrode has at least one first slit.In addition, dielectric layer is to cover this first slit, and the dielectric layer in each picture element unit has at least one second slit, to expose the subregion of each pixel electrode.
The present invention proposes a kind of display panels, and it comprises aforesaid active component array base board, subtend substrate and liquid crystal layer.Wherein, the subtend substrate has the common electrode layer, and liquid crystal layer is to be disposed between the common electrode of active component array base board and subtend substrate.
In an embodiment of the present invention, one of them for example is serrate slit (jagged slit) at least for first slit and this second slit.
In an embodiment of the present invention, can further comprise light shield layer in each picture element unit, and this light shield layer is second slit below that is disposed at dielectric layer.In addition, the material of aforementioned light shield layer for example is a conductor, so light shield layer and pixel electrode can constitute reservior capacitor (storage capacitor).
In an embodiment of the present invention, can further comprise reservior capacitor in each picture element unit, this reservior capacitor is second slit below that is disposed at dielectric layer.For instance, reservior capacitor for example comprises the top electrode that is disposed at the bottom electrode on the substrate and is positioned at the bottom electrode top.Wherein, top electrode is to be connected with the pixel electrode electric polarity.In addition, the material of aforementioned top electrode and/or bottom electrode for example is a light screening material.
In an embodiment of the present invention, the specific inductive capacity of dielectric layer for example is less than 3.5, and the thickness of dielectric layer for example is between 1 micron to 2 microns.In addition, the top width of aforementioned second slit is the bottom width greater than this second slit.
The present invention proposes a kind of manufacture method of active component array base board, comprises the following steps.At first, form plurality of scanning wirings, many data wirings and a plurality of active member on substrate, wherein active member is to electrically connect with corresponding scan wiring and data wiring.Then, form a plurality of pixel electrodes that electrically connect with active member on substrate, wherein each pixel electrode has at least one first slit.Afterwards, form a dielectric layer on substrate, to cover first slit, wherein the dielectric layer on each pixel electrode has at least one second slit, to expose the subregion of each pixel electrode.
In an embodiment of the present invention, the formation method of scan wiring, this data wiring and this active member comprises the following steps.At first, form one first conductor layer on substrate, this first conductor layer comprises scan wiring and a plurality of gate that is connected with scan wiring.Then, on substrate, form a gate insulation layer, to cover first conductor layer.Afterwards, on gate insulation layer, form a plurality of channel layers, and channel layer is to be positioned at the gate top.At last, form one second conductor layer on gate insulation layer, this second conductor layer comprises data wiring and a plurality of source/drain that is connected with data wiring, and source/drain is the subregion that covers channel layer.
In an embodiment of the present invention, when forming scan wiring, data wiring and active member, more comprise forming a reservior capacitor.For example, the bottom electrode of reservior capacitor for example can be made with scan wiring and gate.
In another embodiment of the present invention, the bottom electrode of reservior capacitor for example can be made with scan wiring and gate, and the top electrode of reservior capacitor for example can be made with data wiring, source/drain.In addition, top electrode for example is further to electrically connect with corresponding pixel electrode.
In an embodiment of the present invention, before forming pixel electrode, can further form a protective seam, to cover scan wiring, data wiring and active member.
Show in the panel at liquid crystal face of the present invention, be to adopt first slit in the pixel electrode and second slit in the dielectric layer respectively liquid crystal to be carried out orientation on its active component array base board, because first slit and second slit all are to be made on the same substrate, therefore the relative position of first slit and second slit can be controlled accurately, and then makes the liquid crystal face show that the display quality of panel is not vulnerable to the influence to the group precision of substrate.
The present invention compared with prior art has tangible advantage and beneficial effect.Via as can be known above-mentioned, the invention relates to a kind of display panels, active component array base board and manufacture method thereof.This active component array base board, it comprises substrate, be disposed at scan wiring on the substrate, be disposed at data wiring on the substrate, be disposed at the picture element unit on the substrate and be disposed at dielectric layer on the substrate.Wherein, the picture element unit is to electrically connect with corresponding scan wiring and data wiring, and each picture element unit comprises active member and the pixel electrode that electrically connects with this active member, and each pixel electrode has a plurality of first slits.In addition, dielectric layer is to cover this first slit, and dielectric layer has a plurality of second slits, to expose the subregion of each pixel electrode.
By technique scheme, display panels of the present invention, active component array base board and manufacture method thereof have following advantage at least:
1. multifield vertical directional liquid crystal display panel of the present invention is not vulnerable to the influence to the group precision of substrate on display quality.
2. multifield vertical directional liquid crystal display panel of the present invention has preferable contrast and high aperture opening ratio.
3. active element array substrate manufacturing method of the present invention and existing process-compatible can not cause the burden on the cost.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 and Fig. 1 ' illustrate sectional view and the vertical view into a kind of traditional multifield vertical directional liquid crystal display panel respectively.
Fig. 2 and Fig. 2 ' illustrate sectional view and the vertical view into the traditional multifield vertical directional liquid crystal display panel of another kind respectively.
Fig. 3 and Fig. 1 ' illustrate respectively and are sectional view and vertical view according to the multifield vertical directional liquid crystal display panel of first embodiment of the invention.
Fig. 4 A to Fig. 4 F illustrates and is the making process flow diagram according to the first embodiment of the invention thin-film transistor array base-plate.
Fig. 4 A ' illustrates vertical view into Fig. 4 A to Fig. 4 F respectively to Fig. 4 F '.
Fig. 5 and Fig. 5 ' illustrate respectively and are sectional view and vertical view according to the multifield vertical directional liquid crystal display panel of second embodiment of the invention.
Fig. 6 A to Fig. 6 F illustrates and is the making process flow diagram according to the second embodiment of the invention thin-film transistor array base-plate.
Fig. 6 A ' illustrates vertical view into Fig. 6 A to Fig. 6 F respectively to Fig. 6 F '.
Fig. 7 and Fig. 7 ' illustrate respectively and are sectional view and vertical view according to the multifield vertical directional liquid crystal display panel of third embodiment of the invention.
Fig. 8 A to Fig. 8 F illustrates and is the making process flow diagram according to the third embodiment of the invention thin-film transistor array base-plate.
Fig. 8 A ' illustrates vertical view into Fig. 8 A to Fig. 8 F respectively to Fig. 8 F '.
100,100 ': multifield vertical directional liquid crystal display panel
110: thin-film transistor array base-plate 112,122: substrate
114,214: scan wiring 116,216: data wiring
118,218,218 ': picture element unit 118a, 218a: thin film transistor (TFT)
118b, 218b: pixel electrode 120,120 ', 220: colored optical filtering substrates
124,224: colored filter film 126,226: common electrode
130,230: liquid crystal layer
200,200 ', 200 ": multifield vertical directional liquid crystal display panel
210: active component array base board 212,222: substrate
214: scan wiring 215: gate insulation layer
216: data wiring 217: protective seam
218,218 ', 218 ": picture element unit 218a: active member
218b: pixel electrode 218c: bottom electrode or light shield layer
218d: top electrode 219: dielectric layer
220: subtend substrate 224: colored filter film
226: common electrode 230: liquid crystal layer
Cst: reservior capacitor M1: first conductor layer
M2: the second conductor layer P: orientation protrusion
S1, S2: slit S3: first slit
S3: second slit
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of display panels, active component array base board and manufacture method thereof, structure, manufacture method, step, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
First embodiment
Fig. 3 and Fig. 3 ' illustrate respectively and are sectional view and vertical view according to the multifield vertical directional liquid crystal display panel of first embodiment of the invention.Please refer to Fig. 3 and Fig. 3 ', the multifield vertical directional liquid crystal display panel 200 of present embodiment comprises active component array base board 210, subtend substrate 220 and liquid crystal layer 230.Wherein, liquid crystal layer 230 is to be disposed between active component array base board 210 and the subtend substrate 220.
Please be simultaneously with reference to Fig. 3 and Fig. 3 ', in multifield vertical directional liquid crystal display panel 200, active component array base board 210 comprises substrate 212, plurality of scanning wirings 214 and many data wirings 216, a plurality of picture elements unit 218 and dielectric layers 219.Wherein, scan wiring 214, data wiring 216, picture element unit 218 and dielectric layer 219 all are disposed on the substrate 212, and scan wiring 214, data wiring 216 are and corresponding picture element unit 218 electrically connects.More particularly, scan wiring 214 for example is to extend along column direction in parallel with each other, and data wiring 216 for example is to extend along line direction in parallel with each other, and to define a plurality of picture elements zone in substrate 212, picture element unit 218 then is to be disposed in each picture element zone.
In the present embodiment, picture element unit 218 comprises active member 218a and pixel electrode 218b, and wherein pixel electrode 218b electrically connects with active member 218a, and pixel electrode 218b has at least one first slit S3.For instance, the active member 218a of present embodiment can be the thin film transistor (TFT) of any kenel, and as amorphous silicon film transistor or low-temperature polysilicon film transistor, and the framework of this thin film transistor (TFT) can be top gate kenel or end gate kenel.Certainly, the active member 218a of present embodiment can also be other on-off elements with three terminals.
Illustrate as Fig. 3, the dielectric layer 219 of present embodiment is the first slit S3 that covers pixel electrode 218b, and the dielectric layer 219 in each picture element unit 218 has at least one second slit S4, to expose the subregion of each pixel electrode 218b.Because the first slit S3 of pixel electrode 218b is covered by dielectric layer 219, and the subregion of pixel electrode 218b can expose by the second slit S4, so the first slit S3 and the second slit S4 can be variant for the influence degree of the liquid crystal layer 230 of its top.On the other hand, the aforesaid first slit S3 and this second slit S4 for example can be the zigzag slit (jagged slit) or the slit (slit) of general strip, or the slit of other Any shape (slit), as long as can produce the slit of orientation effect to liquid crystal layer 230.Wherein, this first slit S3 can be identical or inequality with the shape of this second slit S4.Please refer to Fig. 3 ', it is the slit (slit) that shows general strip, and does not show zigzag slit (jaggedslit).
Referring again to Fig. 3 and Fig. 3 ', the subtend substrate 220 of present embodiment for example is colored optical filtering substrates (color filter substrate), and it comprises substrate 222, colored filter film 224 and common electrode 226.Wherein, colored filter film 224 is to be disposed on the substrate 222, and common electrode 226 is to be disposed on the colored filter film 224.In the present embodiment, owing to need not make any alignment pattern (orientation protrusion or slit) on the subtend substrate 220, and all alignment pattern (the first slit S3 and the second slit S4) all are made on the active component array base board 210, therefore, distance between the first slit S3 and the second slit S4 can be accurately controlled, and can not be subjected to the influence to the group precision of substrate.In other words, present embodiment can be by the first slit S3 on the active component array base board 210 and the second slit S4 to LCD alignment, to form multiple field in multifield vertical directional liquid crystal display panel 200.
Fig. 4 A to Fig. 4 F illustrates and is the making process flow diagram according to the first embodiment of the invention thin-film transistor array base-plate, and Fig. 4 A ' illustrates vertical view into Fig. 4 A to Fig. 4 F respectively to Fig. 4 F '.Please refer to Fig. 4 A and Fig. 4 A ', at first, form the first conductor layer M1 on substrate 212, this first conductor layer M1 comprises a plurality of scan wirings 214 and a plurality of gate G that is connected with scan wiring 214.Then, on substrate 212, form a gate insulation layer 215, to cover the first conductor layer M1.
Then please refer to Fig. 4 B and Fig. 4 B ', after gate insulation layer 215 forms, on gate insulation layer 215, form a plurality of channel layer Ch, and each channel layer Ch is positioned at corresponding gate G top.In the present embodiment, channel layer Ch for example is amorphous silicon material or other semiconductor materials, and its top optionally forms an ohmic contact layer (ohmic contact layer).
Then please refer to Fig. 4 C and Fig. 4 C ', after channel layer Ch completes, on gate insulation layer 215, form the second conductor layer M2, this second conductor layer M2 comprises a plurality of data wirings 216 and a plurality of source S, drain D, and source S is to be connected with data wiring 216, and source S is the subregion that covers corresponding channel layer Ch with drain D, and active member 218a (thin film transistor (TFT)) so completes.In the present embodiment, the second conductor layer M2 for example is molybdenum/aluminium/molybdenum composite conductor layer (Mo/Al/Mo) or other conductor material.。
Then please refer to Fig. 4 D and Fig. 4 D ', after forming the second conductor layer M2, then form protective seam 217, to cover scan wiring 214, data wiring 216 and active member 218.By Fig. 4 D and Fig. 4 D ' as can be known, protective seam 217 has contact hole 217a, to expose the subregion of drain D.In the present embodiment, the material of protective seam 217 can be silicon dioxide, silicon nitride or other dielectric materials.
Then please refer to Fig. 4 E and Fig. 4 E ', after forming protective seam 217, then form pixel electrode 218b, and formed pixel electrode 218b has the first slit S3.In the present embodiment, the material of pixel electrode 218b for example is indium tin oxide (ITO), indium-zinc oxide (IZO) or other conductive materials.
Please refer to Fig. 4 F and Fig. 4 F ' at last, after forming pixel electrode 218b, then form dielectric layer 219 in substrate 212 tops, to cover the first slit S3 among the pixel electrode 218b, wherein dielectric layer 219 has a plurality of second slit S4, to expose the subregion of each pixel electrode 218b.In the present embodiment, dielectric layer 219 for example is the dielectric material of low-k, and its specific inductive capacity for example is less than 3.5, and its thickness is between 1 micron to 2 microns.Can know by Fig. 4 F and to learn that the top width W1 of the second slit S4 is the bottom width W2 greater than this second slit S4.
Second embodiment
Fig. 5 and Fig. 5 ' illustrate respectively and are sectional view and vertical view according to the multifield vertical directional liquid crystal display panel of second embodiment of the invention.Please refer to Fig. 5 and Fig. 5 ', the multifield vertical directional liquid crystal display panel 200 of the multifield vertical directional liquid crystal display panel 200 ' of present embodiment and first embodiment is similar, the main difference of the two is: in the picture element unit 218 ' of present embodiment except comprising active member 218a and pixel electrode 218b, also can further comprise light shield layer 218c, and light shield layer 218c is the second slit S4 below that is disposed at dielectric layer 219.In a preferred embodiment, the width of light shield layer 218c is the width greater than the second slit S4, but not as limit.It should be noted that the light leakage phenomena that light shield layer 218c can effectively avoid the second slit S4 to be caused, and then improve the contrast (contrast ratio) of multifield vertical directional liquid crystal display panel 200 '.
Hold above-mentionedly, the light shield layer 218c material that present embodiment adopted can be conductor, dielectric material, or other can cover the material of the light that backlight sends.When light shield layer 218c was conductor, light shield layer 218c can constitute reservior capacitor Cst with pixel electrode 218b.In other words, the light shield layer 218c that is positioned at second slit S4 below not only has the effect of shading, it also can be in order to the bottom electrode as reservior capacitor Cst, can save the shared area of reservior capacitor on this display panels by this design, therefore, can further promote the aperture opening ratio (aperture ratio) of multifield vertical directional liquid crystal display panel 200 '.
Fig. 6 A to Fig. 6 F illustrates and is the making process flow diagram according to the second embodiment of the invention thin-film transistor array base-plate, and Fig. 6 A ' illustrates vertical view into Fig. 6 A to Fig. 6 F respectively to Fig. 6 F '.The making flow process of present embodiment thin-film transistor array base-plate is similar to first embodiment, and only main difference is: the light shield layer of present embodiment (bottom electrode) 218c makes in the lump with scan wiring 214 and gate G.Herein, present embodiment only is described as follows at the difference part, is not just repeating to Fig. 6 F ' relevant for Fig. 6 B to Fig. 6 F and Fig. 6 B '.
Please refer to Fig. 6 A and Fig. 6 A ', form the first conductor layer M1 on substrate 212, this first conductor layer M1 comprises scan wiring 214, a plurality of gate G that is connected with scan wiring 214 and bottom electrode 218c.Then, on substrate 212, form a gate insulation layer 215, to cover the first conductor layer M1.It should be noted that bottom electrode 218c for example has a plurality of branches, the design of this kind bottom electrode 218c helps to increase the storage capacitors value.
The 3rd embodiment
Fig. 7 and Fig. 7 ' illustrate respectively and are sectional view and vertical view according to the multifield vertical directional liquid crystal display panel of third embodiment of the invention.Please refer to Fig. 7 and Fig. 7 ', the multifield vertical directional liquid crystal display panel 200 of present embodiment " similar with the multifield vertical directional liquid crystal display panel 200 ' of second embodiment; the main difference of the two is: the picture element unit 218 of present embodiment " in except comprising active member 218a, pixel electrode 218b and light shield layer (bottom electrode) 218c, also can further comprise top electrode 218d.Top electrode 218d is disposed between the second slit S4 of light shield layer (bottom electrode) 218c and dielectric layer 219, and top electrode 218d is contact hole 217b and pixel electrode 218b electric connection by protective seam 217.In a preferred embodiment, the width of top electrode 218d is the width greater than the second slit S4, but not as limit.It should be noted that light shield layer (bottom electrode) 218c and top electrode 218d not only can constitute reservior capacitor Cst, and the light leakage phenomena that can avoid the second slit S4 to be caused, and then improve the contrast of multifield vertical directional liquid crystal display panel 200 '.
Fig. 8 A to Fig. 8 F illustrates and is the making process flow diagram according to the third embodiment of the invention thin-film transistor array base-plate, and Fig. 8 A ' illustrates vertical view into Fig. 8 A to Fig. 8 F respectively to Fig. 8 F '.The making flow process of present embodiment thin-film transistor array base-plate is similar to second embodiment, and only main difference is: the top electrode 218d of present embodiment makes (shown in Fig. 8 C and Fig. 8 C ') in the lump with data wiring 216, source S and drain D.In addition; for top electrode 218d can be electrically connected with pixel electrode 218b; present embodiment is when making protective seam 217; top electrode 218d forms contact hole 217a and contact hole 217b (shown in Fig. 8 D and Fig. 8 D ') simultaneously, so that can electrically connect by contact hole 217b and pixel electrode 21 8b.Herein, present embodiment only is described as follows at the difference part, is not just repeating to Fig. 6 B ', Fig. 6 E to Fig. 6 F and Fig. 6 E ' to Fig. 6 F ' relevant for Fig. 6 A to Fig. 6 B, Fig. 6 A '.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (16)
1, a kind of active component array base board is characterized in that it comprises:
One substrate;
Plurality of scanning wirings is disposed on this substrate;
Many data wirings are disposed on this substrate;
A plurality of picture elements unit, be disposed on this substrate, and electrically connect with corresponding this scan wiring and this data wiring, wherein each picture element unit comprise an active member and one with the pixel electrode of this active member electric connection, and each pixel electrode has at least one first slit; And
One dielectric layer is disposed on this substrate, and wherein this dielectric layer is to cover this first slit, and this dielectric layer in each picture element unit has at least one second slit, to expose the subregion of each pixel electrode.
2, active component array base board according to claim 1 is characterized in that one of them is the serrate slit at least for wherein said first slit and this second slit.
3, active component array base board according to claim 1, it is characterized in that wherein each picture element unit more comprises a light shield layer, be disposed at this second slit below of this dielectric layer, and the material of this light shield layer comprises conductor, and this light shield layer and this pixel electrode constitute a reservior capacitor.
4, active component array base board according to claim 1, the specific inductive capacity that it is characterized in that wherein said dielectric layer are less than 3.5, and the thickness of this dielectric layer is between 1 micron to 2 microns.
5, active component array base board according to claim 1 is characterized in that the bottom width of the top width of wherein said second slit greater than this second slit.
6, a kind of display panels is characterized in that it comprises:
One active component array base board comprises:
One substrate;
Plurality of scanning wirings is disposed on this substrate;
Many data wirings are disposed on this substrate;
A plurality of picture elements unit, be disposed on this substrate, and electrically connect with corresponding this scan wiring and this data wiring, wherein each picture element unit comprise an active member and one with the pixel electrode of this active member electric connection, and each pixel electrode has at least one first slit;
One dielectric layer is disposed on this substrate, and wherein this dielectric layer is to cover this first slit, and this dielectric layer in each picture element unit has at least the second slit, to expose the subregion of each pixel electrode;
One subtend substrate has and uses electrode layer altogether; And
One liquid crystal layer is disposed between this common electrode of this active component array base board and this subtend substrate.
7, display panels according to claim 6 is characterized in that one of them is the serrate slit at least for wherein said first slit and this second slit.
8, display panels according to claim 6, it is characterized in that wherein each picture element unit more comprises a light shield layer, be disposed at this second slit below of this dielectric layer, and the material of this light shield layer comprises conductor, and this light shield layer and this pixel electrode constitute a reservior capacitor.
9, display panels according to claim 6, the specific inductive capacity that it is characterized in that wherein said dielectric layer are less than 3.5, and the thickness of this dielectric layer is between 1 micron to 2 microns.
10, display panels according to claim 6 is characterized in that the bottom width of the top width of wherein said second slit greater than this second slit.
11, a kind of manufacture method of active component array base board is characterized in that it may further comprise the steps:
Form plurality of scanning wirings, many data wirings and a plurality of active member on a substrate, wherein this active member is to electrically connect with this corresponding scan wiring and this data wiring;
Form a plurality of pixel electrodes that electrically connect with this active member on this substrate, wherein each pixel electrode has at least one first slit; And
Form a dielectric layer on this substrate, to cover this first slit, wherein this dielectric layer on each pixel electrode has at least one second slit, to expose the subregion of each pixel electrode.
12, the manufacture method of active component array base board according to claim 11 is characterized in that wherein the formation method of those scan wirings, those data wirings and those active members comprises:
Form one first conductor layer on this substrate, wherein this first conductor layer comprises those scan wirings and a plurality of gate that is connected with those scan wirings;
On this substrate, form a gate insulation layer, to cover this first conductor layer;
Form a plurality of channel layers on this gate insulation layer, wherein those channel layers are to be positioned at those gate tops; And
Form one second conductor layer on this gate insulation layer, wherein this second conductor layer comprises those data wirings and a plurality of source/drain that is connected with this data wiring, and those source/drain are the subregions that cover those corresponding channel layers.
13, the manufacture method of active component array base board according to claim 11 is characterized in that when forming those scan wirings, those data wirings and those active members, more comprises forming a plurality of reservior capacitors.
14, the manufacture method of active component array base board according to claim 13 is characterized in that the formation method of wherein said those scan wirings, those data wirings, those active members and this reservior capacitor comprises:
Form one first conductor layer on this substrate, wherein this first conductor layer comprises those scan wirings, a plurality of gates that are connected with those scan wirings and a plurality of bottom electrode;
On this substrate, form a gate insulation layer, to cover this first conductor layer;
Form a plurality of channel layers on this gate insulation layer, wherein those channel layers are to be positioned at this gate top; And
On this gate insulation layer, form one second conductor layer, wherein this second conductor layer comprises those data wirings and a plurality of source/drain that is connected with those data wirings, and those source/drain are the subregions that cover those corresponding channel layers, and each bottom electrode is formation one reservior capacitor with corresponding pixel electrode.
15, the manufacture method of active component array base board according to claim 13 is characterized in that wherein said scan wiring, this data wiring, this active member comprise with the formation method of this reservior capacitor:
Form one first conductor layer on this substrate, wherein this first conductor layer comprises those scan wirings, a plurality of gates that are connected with this scan wiring and a plurality of bottom electrode;
On this substrate, form a gate insulation layer, to cover this first conductor layer;
Form a plurality of channel layers on this gate insulation layer, wherein those channel layers are to be positioned at those gate tops; And
On this gate insulation layer, form one second conductor layer, wherein this second conductor layer comprises those data wirings, a plurality of source/drain that are connected with those data wirings and a plurality of top electrode, and those source/drain are the subregions that cover those corresponding channel layers, and each bottom electrode is formation one reservior capacitor with corresponding top electrode.
16, the manufacture method of active component array base board according to claim 11 is characterized in that before forming those pixel electrodes, more comprised forming a protective seam, to cover those scan wirings, those data wirings and those active members.
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| JPH06273798A (en) * | 1993-03-23 | 1994-09-30 | Fujitsu Ltd | Liquid crystal display panel |
| CN1290920A (en) * | 1999-10-01 | 2001-04-11 | 三星电子株式会社 | Wide view angle liquid crystal display |
| CN1359026A (en) * | 2000-10-10 | 2002-07-17 | 现代显示器科技公司 | Dispersion field switching mode LCD |
| CN1350196A (en) * | 2000-10-25 | 2002-05-22 | 达碁科技股份有限公司 | Wide-viewing angle liquid crystal display |
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