CN100358140C - Method and structure for improving adhesion between intermetal dielectric layer and cap layer - Google Patents
Method and structure for improving adhesion between intermetal dielectric layer and cap layer Download PDFInfo
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- CN100358140C CN100358140C CNB2005100660483A CN200510066048A CN100358140C CN 100358140 C CN100358140 C CN 100358140C CN B2005100660483 A CNB2005100660483 A CN B2005100660483A CN 200510066048 A CN200510066048 A CN 200510066048A CN 100358140 C CN100358140 C CN 100358140C
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Abstract
A semiconductor interconnect structure including a semiconductor substrate, a semiconductor active device formed in the substrate, a layer of low-k dielectric material, a first patterned conducting layer, a second patterned conducting layer, and a cap layer formed thereon. The low-k material layer is formed over the semiconductor device. The first conducting line is formed in the low-k material layer and connected to the semiconductor active device. The second conducting line is formed in the low-k material layer but not electrically connected to the semiconductor active device. The cap layer is formed over the low-k material layer, the first and second conducting lines. The cap layer includes silicon and carbon. Since the adhesion strength between the cap layer and the patterned conducting layer is greater than the adhesion strength between the cap layer and the low-k material layer, the addition of second patterned conducting layer would eliminate the overall possibility of delamination between the surface where cap layer is in contact with the low-k material and the first and the second patterned conducting layers.
Description
Technical field
The present invention relates to structure of a kind of semiconductor interconnect (interconnect) and forming method thereof by and large, particularly about a kind of semiconductor interconnect structure and avoid the method for delamination between its cover layer and dielectric layer.
Background technology
Be to adopt advanced low-k materials in many semiconductor elements as inner metal dielectric layer (intermetal dielectric layer; IMD) to lower the electric capacity between between plain conductor.The dielectric material of general so-called low-k is meant to have the dielectric constant that is lower than silica or on the whole less than the material of dielectric constant 4.0, and in general, advanced low-k materials is than tool porousness (porous) and soft (soft) and fragile (weak) for silica, and has usually for contiguous structure and rete higher coefficient of thermal expansion (thermal expansion rate) and lower heat conductivity (thermal conductivity) are arranged.Above-mentioned character may cause between low dielectric constant material layer structure adjacent thereto or rete relatively poor tack being arranged, and therefore, needing usually provides a cover layer to avoid taking place the doubt of delamination (delamination) between inner metal dielectric layer.
Fig. 1 is the example of semiconductor interconnect structure 20 of part in the prior art, for the section in interstage of on an inner metal dielectric layer 28, forming a cover layer 24 graphic.Inner metal dielectric layer 28 is the dielectric materials layers 30 that comprise a low-k, is formed at wherein and the dielectric materials layer 30 of this low-k is the patterned conductive layer 31 with copper metal.The material of cover layer 24 is to comprise silicon and carbon.Inner metal dielectric layer 28 is to be formed at semiconductor active member 42 tops, and this semiconductor active member 42 then is formed at or wherein at semiconductor-based the end 40.In this example, above-mentioned patterned conductive layer 31 is to be electrically connected to active member 42 via the contact plunger 43 of another conductive path.
As is well known, most materials volume when heating can expand, yet even increasing same temperature but still is expanded in various degree, through planting phenomenon thus, our definable goes out thermal coefficient of expansion (thermal expansion coefficient), and any material all has its distinctive coefficient.If the long-pending coefficient of expansion of a kind of hot body of material is to differ from another kind of material attached to it, then the adhesive force (adhesion strength) between above-mentioned both storerooms will weaken after some heat cycle to some extent, this is because when heating or when cooling off, and volume is with each self-expanding or be contracted in various degree and cause.In known internal connection-wire structure shown in Figure 1, patterned conductive layer 31 is irregular being separated by, and 31 of each patterned conductive layers are to have interval region 50.Because the dielectric materials layer 30 of low-k and the thermal coefficient of expansion of cover layer 24 are that difference is very far away, therefore when applying external stress in cover layer 24, cover layer 24 will tend to from inner metal dielectric layer 28 (mainly the dielectric materials layer 30 by low-k is constituted) layering.General external stress is the thermal cycle that comes from the production process, also or from the subsequent chemistry mechanical lapping processing procedure via the heat that produced of friction, and put on the upper surface of semiconductor interconnect structure 20.Therefore, the dealer need seek a kind ofly to avoid or significantly reduce in the semiconductor interconnect structure 20, in cover layer 24 and 28 delaminations that taken place of inner metal dielectric layer.
Summary of the invention
Above institute's problems outlined and demand are to solve via the present invention institute.According to characteristics of the present invention, it provides a kind of semiconductor interconnect structure, comprises: the dielectric materials layer of semiconductor substrate, semiconductor active member, a low-k, one first patterned conductive layer, one second patterned conductive layer and a cover layer.This semiconductor element is formed at and/or on it at above-mentioned the semiconductor-based end, and the dielectric materials layer of above-mentioned low-k then is positioned on this semiconductor element.First patterned conductive layer is formed in the dielectric materials layer of above-mentioned low-k, and be electrically connected to above-mentioned semiconductor active member, second patterned conductive layer then is formed in the dielectric materials layer of this low-k, with as an inactive layer (dummy layer), and be not electrically connected to semi-conductive active member.Cover layer is formed on the dielectric materials layer of above-mentioned low-k, and is positioned at the top of first and second patterned conductive layer.In certain embodiments, cover layer is preferable to comprise silicon and carbon, and wherein on the whole the shared atomic fraction of carbon is higher than 30%.According to the observation, adhesive force between cover layer and above-mentioned first and second patterned conductive layer is big than the adhesive force of the dielectric material interlayer of cover layer and above-mentioned low-k, although therefore second patterned conductive layer is not electrically connected to the semiconductor active member, and there is no the function that provides electricity to be connected, the existence of right this second patterned conductive layer really can be in order to lowering excessive stress, and avoid the phenomenon of surface generation delamination of the dielectric material interlayer of cover layer and low-k.
Moreover, although cover layer not with surperficial tangible contact of the dielectric materials layer and first patterned conductive layer of low-k, the adding of its second patterned conductive layer still can be in order to avoid taking place the possibility of delamination.In this example, a barrier layer (barrierlayer) (not showing in Fig. 2) can be formed between the dielectric materials layer of cover layer and low-k.
According to another characteristics of the present invention, it provides a kind of semiconductor interconnect structure, comprises: semiconductor substrate, semiconductor active member, an inner metal dielectric layer and a cover layer.This semiconductor element is formed at and/or on it at above-mentioned the semiconductor-based end.Inner metal dielectric layer comprises the dielectric materials layer of a low-k, and it is formed at the top of semiconductor active member.One first patterned conductive layer is formed in the dielectric materials layer of above-mentioned low-k, and is electrically connected to above-mentioned semiconductor active member, the preferable copper that comprises of first patterned conductive layer.One second patterned conductive layer also is formed in the dielectric materials layer of above-mentioned low-k, so is not electrically connected to any semiconductor active member, and this second patterned conductive layer is an idle lead, the preferable copper that comprises of second patterned conductive layer.Cover layer is preferable to comprise silicon and carbon, and is formed at the top of above-mentioned inner metal dielectric layer.Because the adhesive force between cover layer and above-mentioned second patterned conductive layer is big than the adhesive force of the dielectric material interlayer of cover layer and above-mentioned low-k, therefore the adding of second patterned conductive layer can be in order to lowering excessive stress, and avoid surface between cover layer and inner metal dielectric layer that the phenomenon of delamination takes place.
In addition, although cover layer is not done contacting of essence with the surface of the inner metal dielectric layer top and first patterned conductive layer, the possibility that the adding of second patterned conductive layer still can avoid delamination to take place.In this example, a barrier layer (barrier layer) (not shown) can form between cover layer and dielectric layer with low dielectric constant.
Semiconductor interconnect structure of the present invention, one of above-mentioned at least first and second patterned conductive layer comprises copper.
Semiconductor interconnect structure of the present invention, this second patterned conductive layer comprise at least one on the whole be linear, rectangle or circular fragment.
Semiconductor interconnect structure of the present invention, this second patterned conductive layer are one to have the patterned layer of a little linear or long broken line shape.
Semiconductor interconnect structure of the present invention, the dielectric materials layer of above-mentioned low-k have the dielectric constant of a dielectric constant less than silica.
Semiconductor interconnect structure of the present invention, the dielectric materials layer of this low-k comprises silicon and carbon.
Semiconductor interconnect structure of the present invention, above-mentioned semiconductor interconnect structure are positioned at one on the neighboring area of semiconductor wafer.
On the whole semiconductor interconnect structure of the present invention, the width of this neighboring area are 10% of above-mentioned semiconductor wafer width.
According to the present invention's another characteristics again, it provides a kind of method of improving the tack between between cover layer and inner metal dielectric layer in the semiconductor interconnect structure.The method comprises the following steps, right and nonessential according to order as described here or successively.At first, the one low dielectric constant dielectric materials layer as inner metal dielectric layer is formed at one to be arranged on the semiconductor active member at the semiconductor-based end, then in the dielectric materials layer of above-mentioned low-k, form one first patterned conductive layer, and be electrically connected to semi-conductive active member, also in this low dielectric constant dielectric materials layer, form second patterned conductive layer as inactive layer in addition, and be not electrically connected to any semiconductor active member, then on above-mentioned inner metal dielectric layer, form a cover layer, preferable silicon and the carbon of comprising of this cover layer at last.Because the adding of second patterned conductive layer, will make the overall adhesion of dielectric material interlayer of cover layer and low-k compared to ought only there being first patterned conductive layer to be present in situation in the dielectric materials layer of this low-k for greatly.
The method of avoiding taking place between cover layer and dielectric layer in the semiconductor interconnect structure delamination of the present invention, this first and second patterned conductive layer comprises copper.
The method of avoiding taking place between cover layer and dielectric layer in the semiconductor interconnect structure delamination of the present invention, this cover layer comprises silicon and carbon.
The method of avoiding taking place between cover layer and dielectric layer in the semiconductor interconnect structure delamination of the present invention, this low dielectric constant dielectric materials layer comprises silicon and carbon.
Description of drawings
Fig. 1 is the example of the semiconductor interconnect structure of part in the prior art, and is graphic for form the section in tectal interstage on inner metal dielectric layer;
Fig. 2 is in the first embodiment of the invention, the cut-away section of semiconductor internal connection-wire structure diagram, and the internal connection-wire structure shown in it is to form the tectal interstage on inner metal dielectric layer;
Fig. 3 is the side cut-away view of the semiconductor interconnect structure of part in the prior art, and it shows that one has the patterned conductive layer of dual-damascene structure;
Fig. 4 shows the part side cut-away view of the semiconductor interconnect structure of second embodiment of the invention;
Fig. 5 is the part side cut-away view of the semiconductor interconnect structure of third embodiment of the invention;
Fig. 6 is the vertical view of semiconductor wafer, and it is the semiconductor interconnect structure of describing among the embodiment of the present invention;
Fig. 7 a to Fig. 7 e is the cross-section illustration that illustrates partially patterned conductive layer for example.
Embodiment
By and large, the present invention be in an embodiment, provide a kind of in semiconductor interconnect structure structure and the method in order to the adhesive force between the cover layer of promoting inner metal dielectric layer and being in contact with it.Fig. 2 is in the first embodiment of the invention, the cut-away section of semiconductor internal connection-wire structure 20 diagram, and the internal connection-wire structure 20 shown in it is the interstages that form a cover layer 24 on an inner metal dielectric layer 28.In first embodiment, inner metal dielectric layer 28 is to comprise to have the dielectric materials layer 30 that one first patterned conductive layer 31 is formed at low-k wherein.The material of cover layer 24 is preferable silicon and the carbon of comprising.Inner metal dielectric layer 28 is the tops that are formed at semiconductor active member 42, and this semiconductor active member 42 then is formed on the semiconductor substrate 40 and/or wherein.In first embodiment, semiconductor active member 42 can be a transistor with gate electrode, and semiconductor active member 42 to be the similar components that need be electrically connected to other imitate so that electricity to be provided, and can in other embodiment, change to for example including but not limited to gate electrode, transistor, electric capacity, resistance, conductor or above-mentioned combination.First patterned conductive layer 31 is to connect by pathway contact plunger 43 and be electrically connected to semiconductor element 42 for example, as shown in Figure 2.Add second patterned conductive layer 32 in the structure, it is not to be electrically connected to other semi-conductive active member, is not connected in the semiconductor active member 42 that has been connected by first patterned conductive layer in above-mentioned at least.The effect of second patterned conductive layer 32 is as same idle conductive layer, but and this idle conductive layer 32 is that ground connection is to avoid producing stray electric field (stray electric field).As detailed in the following, add the possibility that delamination can take place in order to the surface of avoiding 28 of cover layer 24 and inner metal dielectric layers idle conductive layer 32.
The dielectric materials layer 30 of low-k is to can be any suitable advanced low-k materials, including but not limited to for example: Black Diamond, mix fluorine silex glass (FSG), silicon oxide carbide (SiO
xC
y), spin-on glasses (spin-on-glass; SOG), the SILK that produced of spin-coating macromolecule (spin-on-polymer), Dow chemical
TM, FLARE that Honeywell produced
TM, JSR Micro, the LKD that Inc. produced (low-kdielectric), silicon oxide carbide (SiCOH), amorphous silicon hydrogen (amorphous hydrogenated silicon through hydrogenation; A-Si:H), silicon oxynitride (SiO
xN
y), carborundum (SiC), oxygen-doped carbofrax material (SiCO), mix hydrogen carbofrax material (SiCH), above-mentioned compound (compound), compound (composite) or its composition (composition).Cover layer 24 can be made of the suitable material of any multiple different silicon-containing and carbon, including but not limited to for example: the silicon nitride (SixNyCx) of the carbofrax material (SiCN) of carborundum (SiC), nitrating, the silico-carbo compound with at least 30% carbon atom branch rate, carbon dope, the compound or the composition of above-mentioned material.Patterned conductive layer the 31, the 32nd can be made of various suitable electric conducting materials, including but not limited to for example: the compound of metal nitride, metal alloy, copper, copper alloy, aluminium, aluminium alloy, gold, billon, above-mentioned material or its combination.In a preferred embodiment, second patterned conductive layer 32 is preferable use and first conductive layer, 31 identical materials and step and form, yet in other embodiments, second patterned conductive layer 32 also can be formed by the material that differs from first patterned conductive layer 31.Contact plunger 43 preferablely is made of the copper metal, but also can be formed by other material.Although generally be used to connect the contact plunger 43 of semiconductor active member 42 and be and use a material that differs from first patterned conductive layer 31 usually, yet those skilled in the art can expect that contact plunger 43 also can use and first patterned conductive layer, 31 identical materials, are connected to the lead (for example single inlay structure, dual-damascene structure) of semiconductor active member 42 with manufacturing.
In the process that forms semiconductor interconnect structure 20, in inner metal dielectric layer 28, form before the patterned conductive layer 31 and 32, its may need to slow down or even stop the etching phenomenon at the interface of inner metal dielectric layer 28 and dielectric layer 44, therefore, also may will another dielectric layer (not showing among Fig. 2) be set between inner metal dielectric layer 28 and dielectric layer 44, it has with respect to the higher resistance of inner metal dielectric layer 28 so that the etched preferable ability that hinders to be provided, and some dielectric layer has for example silicon nitride, carborundum, silicon oxynitride (SiON), the combination of silica material of carbon dope (SiOC) or above-mentioned material is the suitable selection of dielectric layer material for this reason.
In a preferred embodiment of the present invention, the dielectric materials layer 30 of low-k is by Applied Materials the Black Diamond that Inc. produced
TMConstitute, patterned conductive layer 31,32 then is made up of copper or copper alloy (the preferable barrier layer that also comprises does not show), cover layer 24 be preferably carborundum (as Applied Materials, the BLOk that Inc. produced
TM).And find via test, be arranged in the Black Diamond material (advanced low-k materials 30) and the BLOk of inner metal dielectric layer 28
TMReducible copper conductive layer 31,32 and the BLOk of being weaker than of adhesive force between the material (carborundum cover layer 24)
TMFive times of adhesive force between the material (carborundum cover layer 24).For example, a known structure (the not idle conductive layer 32 of tool), it has by BLOk
TMThe cover layer 24 that material constituted, first conductive layer 31 that copper constituted and by Black Diamond
TMThe dielectric materials layer 30 of the low-k that is constituted carries out four-point bending test (four-point be nding test), the about 24.80J/m of adhesive force that is measured in copper/BLOk interface with this structure
2, the adhesive force that Black Diamond/BLOk interface is measured is then made an appointment with only 5.01J/m
2Therefore, can be according to embodiments of the invention by increasing idle conductive layer 32 to increase the interface scope of copper/carborundum, and thereby reduce the adhesive force of low-k inner metal dielectric layer/carborundum dielectric scope, have the inner metal dielectric layer 28 of low-k and the whole boundary strength between the carborundum cover layer 24 to strengthen widely.
Among Fig. 2, the width of the tangent plane of second patterned conductive layer 32 and quantity (observed along its side cut-away view) also are the keys of promoting the adhesive force usefulness of 28 of cover layer 24 and inner metal dielectric layers.At first, second patterned conductive layer 32 and first patterned conductive layer 31 are to form in the same process step usually, therefore the width of the tangent plane of second patterned conductive layer 32 is that on the whole the width with the tangent plane of first patterned conductive layer 31 is identical, or is butted on greatly in 20% the range of variation.Moreover, although representing the scope of cover layer and Metal Contact, the adding of second patterned conductive layer 32 increases, and then increase its adhesive force, yet quantity that is increased or scope too then will cause other problem, this is too much because work as the metallic region that is exposed in the inner metal dielectric layer 28, it is then follow-up when the cmp processing procedure is implemented on the surface of dielectric layer 28 between inner metal layer, to heal in the corrosion that metallic region produced and to become serious, and cause with successive process in the cover layer 24 that deposited the tack of extreme difference is arranged.
Among the present invention, the idle conductive layer 32 in the inner metal dielectric layer 28 also need be done suitably to divide to be equipped with to take into account above-mentioned considering: minimum corrosion possibility and maximum adhesive force synergy.Between two patterned conductive layers 31, if the summation area that cover layer contacts with idle conductive layer 32 is between 20～80% with respect to the scope ratio of the gross area of 31 of two patterned conductive layers, then the enhancing of adhesive force will be quite remarkable, and the possibility of corrosion is also still permissible.Specifically, with usefulness, be on the whole being that 50% scope ratio is the best.
Fig. 3 is the part side cut-away view of known semiconductor internal connection-wire structure 20, and it is to show that one has the patterned conductive layer 31 of dual-damascene structure.Fig. 4 then shows the part side cut-away view of the semiconductor interconnect structure 20 of second embodiment of the invention.This second embodiment comes down to be same as first embodiment (Fig. 2), except wherein being has to small part first patterned conductive layer 31 formation as dual-damascene structures (view 4).The idle conductive layer 32 of patterning more than one or one can form dual-damascene structure in other embodiment, as long as it is not electrically connected with semiconductor active member 42.
Fig. 5 is the part side cut-away view of the semiconductor interconnect structure 20 of third embodiment of the invention, and it has the idle conductive layer 32 of patterning to increase the adhesive force between inner metal dielectric layer 28 and the cover layer 24.In this 3rd embodiment, first patterned conductive layer 31 is that directly (for example using the copper metal) is electrically connected to semiconductor active member 42.
This structure that comprises the idle conductive layer of patterning is can be in order to promote the adhesive force between inner metal dielectric layer and the cover layer, and under following two kinds of situations is special needs: one of them is the outer peripheral areas that is used for semiconductor wafer, another then be used for semiconductor interconnect than the upper strata.At first, the outer peripheral areas of semiconductor wafer always suffers maximum stress changes in the manufacture process of semiconductor wafer, thereby needs a kind of design of adhesive force of effective reinforcing membrane interlayer especially.
With reference to Fig. 6, the outer peripheral areas 52 of semiconductor wafer 50 is to be defined as by one to have 10% arrowband or the zone that width W is about or is a bit larger tham semiconductor wafer 50 width.Semiconductor wafer 50 mentioned herein is possible for rectangle is not to be square, so the width W of outer peripheral areas can be and occupy 10% of semiconductor wafer one or other direction size, or is 10% of the mean value that occupies above-mentioned direction size.Moreover, in the manufacture process of semiconductor wafer, when cutting into slices or separate, corner 54 places of semiconductor wafer 50 then always suffer with respect to other scope of outer peripheral areas 52 bigger stress is arranged, and therefore structure applications of the present invention has best effect herein.
As mentioned above, arrowband or zone 52 can comprise or only comprise most semiconductor interconnect structures 20, and each semiconductor interconnect structure 20 is and be arranged in semiconductor wafer 50 1 or above electric linking to each other of other element, this semiconductor wafer 50 is as same special circuit or block and effect in the lump, for example a memory, processor, counter, voltage source or like that.Be positioned on the outer peripheral areas 52 or semiconductor interconnect structure wherein 20, owing to make in semiconductor wafer 50 or on it in process of multicomponent, pressure builds up rising, thereby suffers very high stress usually for it.Owing to add the idle conductive layer 32 of patterning in internal connection-wire structure 20, so the adhesive force between inner metal dielectric layer and the cover layer increases, and the problem of delamination also can be kept away and removed.
When this comprise structure in order to the idle conductive layer that increases the adhesive force between inner metal dielectric layer and cover layer be used for semiconductor interconnect than the upper strata time, also have suitable effectiveness.Semiconductor interconnect structure is often to form several layers not according to its design, in manufacture process, the rete that is positioned at than the top is to suffer to be positioned at the stress suffered than the rete of below more than it, therefore the present invention is preferably the intraconnections rete that is applied in than the top, for example, to go up two-layer intraconnections (for example top layer and the rete that is positioned at its below) most be to be that the best implements part of the present invention to semiconductor wafer.
Although patterned conductive layer the 31, the 32nd shows the lines as separating in the side cutaway view of Fig. 2, Fig. 4 and Fig. 5, it is that the actual patterned back of conductive layer forms as having the fragment of the linear or rectangle more than one or.Fig. 7 a to Fig. 7 e is the last diagrammatic sketch that illustrates some patterned conductive layers for example, and each long broken line also cuts open and shows in the side among displayed map 2, Fig. 4 and Fig. 5 among Fig. 7 a to Fig. 7 e.Usually the shape with several independent lines shown in Fig. 7 a perhaps has several lines fragments shown in Fig. 7 b, and the shape that at least two lines fragment essence connects is the most normal use.In some cases, the approximate shapes of conductive layer patternable such as rectangle is also or as the shape of sphering, for example respectively shown in Fig. 7 c and Fig. 7 d.And the long broken line of similar amplification or the shape of dotted line among conductive layer even patternable such as Fig. 7 e sometimes, and all fragments are to be preferably simultaneously to make.All the above embodiments are only in order to the part difference of patterned conductive layer of the present invention to be described, and are not in order to limit the present invention.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
20: internal connection-wire structure
24: cover layer
28: inner metal dielectric layer
30: dielectric materials layer
31: patterned conductive layer
32: idle conductive layer
40: semiconductor base
42: the semiconductor active member
43: contact plunger
44: dielectric layer
50: semiconductor wafer
52: the outer peripheral areas of semiconductor wafer
54: the corner W of wafer conductor: the width of semiconductor wafer outer peripheral areas
Claims (14)
1, a kind of semiconductor interconnect structure is characterized in that described semiconductor interconnect structure comprises:
The semiconductor substrate;
The semiconductor active member, it is arranged in this semiconductor-based end;
The dielectric materials layer of one low-k, it is positioned at this semiconductor active member top;
One first patterned conductive layer be arranged in the dielectric materials layer of this low-k, and this first patterned conductive layer is electrically connected with this semiconductor active member;
One second patterned conductive layer is arranged in the dielectric materials layer of this low-k, and wherein this second patterned conductive layer is not electrically connected with above-mentioned semiconductor active member, and this second patterned conductive layer is an idle lead; And
One cover layer is positioned at the top of dielectric materials layer and this first and second patterned conductive layer of this low-k.
2, semiconductor interconnect structure according to claim 1 is characterized in that: one of above-mentioned at least first and second patterned conductive layer comprises copper.
3, semiconductor interconnect structure according to claim 1 is characterized in that: this second patterned conductive layer comprises at least one be linear, rectangle or circular fragment.
4, semiconductor interconnect structure according to claim 1 is characterized in that: this second patterned conductive layer is one to have the patterned layer of a little linear or long broken line shape.
5, semiconductor interconnect structure according to claim 1 is characterized in that: this cover layer comprises silicon and carbon.
6, semiconductor interconnect structure according to claim 5 is characterized in that: this cover layer comprises at least 30% carbon content.
7, semiconductor interconnect structure according to claim 1 is characterized in that: the dielectric materials layer of above-mentioned low-k has the dielectric constant of a dielectric constant less than silica.
8, semiconductor interconnect structure according to claim 1 is characterized in that: the dielectric materials layer of this low-k comprises silicon and carbon.
9, semiconductor interconnect structure according to claim 1 is characterized in that: above-mentioned semiconductor interconnect structure is positioned at one on the neighboring area of semiconductor wafer.
10, semiconductor interconnect structure according to claim 9 is characterized in that: the width of this neighboring area is 10% of an above-mentioned semiconductor wafer width.
11, a kind of method of avoiding taking place between cover layer and dielectric layer in the semiconductor interconnect structure delamination is characterized in that the described method of avoiding delamination takes place between cover layer and dielectric layer in the semiconductor interconnect structure comprises:
Top in the semiconductor active member forms a low dielectric constant dielectric materials layer as above-mentioned dielectric layer, and this semiconductor active member is arranged in the semiconductor substrate;
Form one first patterned conductive layer in this low dielectric constant dielectric materials layer, this first patterned conductive layer is electrically connected to this semiconductor active member;
Form one second patterned conductive layer in this low dielectric constant dielectric materials layer, this second patterned conductive layer is not electrically connected to above-mentioned semiconductor active member; And
On dielectric layer, this first patterned conductive layer and this second patterned conductive layer, form a cover layer.
12, the method for avoiding taking place between cover layer and dielectric layer in the semiconductor interconnect structure delamination according to claim 11, it is characterized in that: this first and second patterned conductive layer comprises copper.
13, the method for avoiding taking place between cover layer and dielectric layer in the semiconductor interconnect structure delamination according to claim 11, it is characterized in that: this cover layer comprises silicon and carbon.
14, the method for avoiding taking place between cover layer and dielectric layer in the semiconductor interconnect structure delamination according to claim 11, it is characterized in that: this low dielectric constant dielectric materials layer comprises silicon and carbon.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US56436504P | 2004-04-22 | 2004-04-22 | |
| US60/564,365 | 2004-04-22 | ||
| US10/967,009 | 2004-10-15 |
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| CN100358140C true CN100358140C (en) | 2007-12-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102163588A (en) * | 2010-02-16 | 2011-08-24 | 台湾积体电路制造股份有限公司 | Conductive pillar structure for semiconductor substrate and method of manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8202783B2 (en) * | 2009-09-29 | 2012-06-19 | International Business Machines Corporation | Patternable low-k dielectric interconnect structure with a graded cap layer and method of fabrication |
| US9029260B2 (en) * | 2011-06-16 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap filling method for dual damascene process |
| US11127632B1 (en) * | 2020-03-19 | 2021-09-21 | Nanya Technology Corporation | Semiconductor device with conductive protrusions and method for fabricating the same |
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| JP2000332015A (en) * | 1999-05-12 | 2000-11-30 | United Microelectronics Corp | Manufacture of copper capping layer |
| US6468894B1 (en) * | 2001-03-21 | 2002-10-22 | Advanced Micro Devices, Inc. | Metal interconnection structure with dummy vias |
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| JPH10294366A (en) * | 1997-04-21 | 1998-11-04 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| US6071809A (en) * | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102163588A (en) * | 2010-02-16 | 2011-08-24 | 台湾积体电路制造股份有限公司 | Conductive pillar structure for semiconductor substrate and method of manufacture |
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| CN1691320A (en) | 2005-11-02 |
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