CN100357884C - 用于处理指令的方法、处理器以及系统 - Google Patents
用于处理指令的方法、处理器以及系统 Download PDFInfo
- Publication number
- CN100357884C CN100357884C CNB2005100819663A CN200510081966A CN100357884C CN 100357884 C CN100357884 C CN 100357884C CN B2005100819663 A CNB2005100819663 A CN B2005100819663A CN 200510081966 A CN200510081966 A CN 200510081966A CN 100357884 C CN100357884 C CN 100357884C
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- CN
- China
- Prior art keywords
- instruction
- resource
- processor
- resources
- hardware
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/965,143 | 2004-10-14 | ||
| US10/965,143 US7237094B2 (en) | 2004-10-14 | 2004-10-14 | Instruction group formation and mechanism for SMT dispatch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1760826A CN1760826A (zh) | 2006-04-19 |
| CN100357884C true CN100357884C (zh) | 2007-12-26 |
Family
ID=36317706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100819663A Expired - Fee Related CN100357884C (zh) | 2004-10-14 | 2005-07-08 | 用于处理指令的方法、处理器以及系统 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7237094B2 (https=) |
| JP (1) | JP2006114036A (https=) |
| CN (1) | CN100357884C (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108400866A (zh) * | 2018-03-01 | 2018-08-14 | 中国人民解放军战略支援部队信息工程大学 | 一种粗粒度可重构密码逻辑阵列 |
Families Citing this family (52)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7836276B2 (en) * | 2005-12-02 | 2010-11-16 | Nvidia Corporation | System and method for processing thread groups in a SIMD architecture |
| US8860737B2 (en) * | 2003-10-29 | 2014-10-14 | Nvidia Corporation | Programmable graphics processor for multithreaded execution of programs |
| US8174531B1 (en) | 2003-10-29 | 2012-05-08 | Nvidia Corporation | Programmable graphics processor for multithreaded execution of programs |
| JPWO2006134693A1 (ja) * | 2005-06-15 | 2009-01-08 | 松下電器産業株式会社 | プロセッサ |
| US7434032B1 (en) | 2005-12-13 | 2008-10-07 | Nvidia Corporation | Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators |
| KR100837400B1 (ko) * | 2006-07-20 | 2008-06-12 | 삼성전자주식회사 | 멀티스레딩/비순차 병합 기법에 따라 처리하는 방법 및장치 |
| US9069547B2 (en) | 2006-09-22 | 2015-06-30 | Intel Corporation | Instruction and logic for processing text strings |
| US20080229062A1 (en) * | 2007-03-12 | 2008-09-18 | Lorenzo Di Gregorio | Method of sharing registers in a processor and processor |
| US7707390B2 (en) * | 2007-04-25 | 2010-04-27 | Arm Limited | Instruction issue control within a multi-threaded in-order superscalar processor |
| JP5093237B2 (ja) * | 2007-06-20 | 2012-12-12 | 富士通株式会社 | 命令処理装置 |
| US20090210664A1 (en) * | 2008-02-15 | 2009-08-20 | Luick David A | System and Method for Issue Schema for a Cascaded Pipeline |
| US7865700B2 (en) | 2008-02-19 | 2011-01-04 | International Business Machines Corporation | System and method for prioritizing store instructions |
| US7984270B2 (en) | 2008-02-19 | 2011-07-19 | International Business Machines Corporation | System and method for prioritizing arithmetic instructions |
| US8095779B2 (en) * | 2008-02-19 | 2012-01-10 | International Business Machines Corporation | System and method for optimization within a group priority issue schema for a cascaded pipeline |
| US7882335B2 (en) * | 2008-02-19 | 2011-02-01 | International Business Machines Corporation | System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline |
| US20090210666A1 (en) * | 2008-02-19 | 2009-08-20 | Luick David A | System and Method for Resolving Issue Conflicts of Load Instructions |
| US7877579B2 (en) * | 2008-02-19 | 2011-01-25 | International Business Machines Corporation | System and method for prioritizing compare instructions |
| US7870368B2 (en) | 2008-02-19 | 2011-01-11 | International Business Machines Corporation | System and method for prioritizing branch instructions |
| US20090210672A1 (en) * | 2008-02-19 | 2009-08-20 | Luick David A | System and Method for Resolving Issue Conflicts of Load Instructions |
| US7996654B2 (en) * | 2008-02-19 | 2011-08-09 | International Business Machines Corporation | System and method for optimization within a group priority issue schema for a cascaded pipeline |
| US8108654B2 (en) * | 2008-02-19 | 2012-01-31 | International Business Machines Corporation | System and method for a group priority issue schema for a cascaded pipeline |
| GB2466984B (en) * | 2009-01-16 | 2011-07-27 | Imagination Tech Ltd | Multi-threaded data processing system |
| US8108655B2 (en) * | 2009-03-24 | 2012-01-31 | International Business Machines Corporation | Selecting fixed-point instructions to issue on load-store unit |
| US8127115B2 (en) * | 2009-04-03 | 2012-02-28 | International Business Machines Corporation | Group formation with multiple taken branches per group |
| GB2469822B (en) * | 2009-04-28 | 2011-04-20 | Imagination Tech Ltd | Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor |
| US8291169B2 (en) | 2009-05-28 | 2012-10-16 | International Business Machines Corporation | Cache line use history based done bit modification to D-cache replacement scheme |
| US8332587B2 (en) * | 2009-05-28 | 2012-12-11 | International Business Machines Corporation | Cache line use history based done bit modification to I-cache replacement scheme |
| JP5463076B2 (ja) * | 2009-05-28 | 2014-04-09 | パナソニック株式会社 | マルチスレッドプロセッサ |
| US8171224B2 (en) * | 2009-05-28 | 2012-05-01 | International Business Machines Corporation | D-cache line use history based done bit based on successful prefetchable counter |
| US8140760B2 (en) * | 2009-05-28 | 2012-03-20 | International Business Machines Corporation | I-cache line use history based done bit based on successful prefetchable counter |
| CN101957744B (zh) * | 2010-10-13 | 2013-07-24 | 北京科技大学 | 一种用于微处理器的硬件多线程控制方法及其装置 |
| US9304774B2 (en) * | 2011-02-04 | 2016-04-05 | Qualcomm Incorporated | Processor with a coprocessor having early access to not-yet issued instructions |
| US9465755B2 (en) | 2011-07-18 | 2016-10-11 | Hewlett Packard Enterprise Development Lp | Security parameter zeroization |
| TWI447646B (zh) | 2011-11-18 | 2014-08-01 | Asmedia Technology Inc | 資料傳輸裝置及多個指令的整合方法 |
| US8856193B2 (en) * | 2011-12-20 | 2014-10-07 | Sap Se | Merge monitor for table delta partitions |
| US9798548B2 (en) * | 2011-12-21 | 2017-10-24 | Nvidia Corporation | Methods and apparatus for scheduling instructions using pre-decode data |
| CN102662632B (zh) * | 2012-03-14 | 2015-04-08 | 北京思特奇信息技术股份有限公司 | 一种利用信号量实现的序列号生成方法和生成器 |
| US9513915B2 (en) | 2012-03-28 | 2016-12-06 | International Business Machines Corporation | Instruction merging optimization |
| US9405701B2 (en) | 2012-03-30 | 2016-08-02 | Intel Corporation | Apparatus and method for accelerating operations in a processor which uses shared virtual memory |
| US9336057B2 (en) | 2012-12-21 | 2016-05-10 | Microsoft Technology Licensing, Llc | Assigning jobs to heterogeneous processing modules |
| US9665372B2 (en) * | 2014-05-12 | 2017-05-30 | International Business Machines Corporation | Parallel slice processor with dynamic instruction stream mapping |
| CN105446700B (zh) * | 2014-05-30 | 2018-01-02 | 华为技术有限公司 | 一种指令执行方法以及顺序处理器 |
| US9715392B2 (en) * | 2014-08-29 | 2017-07-25 | Qualcomm Incorporated | Multiple clustered very long instruction word processing core |
| US9720696B2 (en) | 2014-09-30 | 2017-08-01 | International Business Machines Corporation | Independent mapping of threads |
| US9977678B2 (en) | 2015-01-12 | 2018-05-22 | International Business Machines Corporation | Reconfigurable parallel execution and load-store slice processor |
| US10133576B2 (en) | 2015-01-13 | 2018-11-20 | International Business Machines Corporation | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries |
| US11275590B2 (en) * | 2015-08-26 | 2022-03-15 | Huawei Technologies Co., Ltd. | Device and processing architecture for resolving execution pipeline dependencies without requiring no operation instructions in the instruction memory |
| US10423423B2 (en) | 2015-09-29 | 2019-09-24 | International Business Machines Corporation | Efficiently managing speculative finish tracking and error handling for load instructions |
| US20170300361A1 (en) * | 2016-04-15 | 2017-10-19 | Intel Corporation | Employing out of order queues for better gpu utilization |
| US11314516B2 (en) * | 2018-01-19 | 2022-04-26 | Marvell Asia Pte, Ltd. | Issuing instructions based on resource conflict constraints in microprocessor |
| CN112445619A (zh) * | 2020-11-30 | 2021-03-05 | 海光信息技术股份有限公司 | 在多线程系统中动态共享有序资源的管理系统和方法 |
| US11656877B2 (en) * | 2021-03-31 | 2023-05-23 | Advanced Micro Devices, Inc. | Wavefront selection and execution |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1429361A (zh) * | 2000-03-24 | 2003-07-09 | 英特尔公司 | 用于在一个多线程处理器内在多个线程之间划分资源的方法和装置 |
| US6601120B1 (en) * | 2000-07-13 | 2003-07-29 | Silicon Graphics, Inc. | System, method and computer program product for implementing scalable multi-reader/single-writer locks |
| US6658447B2 (en) * | 1997-07-08 | 2003-12-02 | Intel Corporation | Priority based simultaneous multi-threading |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5337415A (en) * | 1992-12-04 | 1994-08-09 | Hewlett-Packard Company | Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency |
| US5828895A (en) * | 1995-09-20 | 1998-10-27 | International Business Machines Corporation | Methods and system for predecoding instructions in a superscalar data processing system |
| US5958042A (en) * | 1996-06-11 | 1999-09-28 | Sun Microsystems, Inc. | Grouping logic circuit in a pipelined superscalar processor |
| US6163840A (en) * | 1997-11-26 | 2000-12-19 | Compaq Computer Corporation | Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline |
-
2004
- 2004-10-14 US US10/965,143 patent/US7237094B2/en not_active Expired - Fee Related
-
2005
- 2005-07-08 CN CNB2005100819663A patent/CN100357884C/zh not_active Expired - Fee Related
- 2005-10-06 JP JP2005294193A patent/JP2006114036A/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6658447B2 (en) * | 1997-07-08 | 2003-12-02 | Intel Corporation | Priority based simultaneous multi-threading |
| CN1429361A (zh) * | 2000-03-24 | 2003-07-09 | 英特尔公司 | 用于在一个多线程处理器内在多个线程之间划分资源的方法和装置 |
| US6601120B1 (en) * | 2000-07-13 | 2003-07-29 | Silicon Graphics, Inc. | System, method and computer program product for implementing scalable multi-reader/single-writer locks |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108400866A (zh) * | 2018-03-01 | 2018-08-14 | 中国人民解放军战略支援部队信息工程大学 | 一种粗粒度可重构密码逻辑阵列 |
| CN108400866B (zh) * | 2018-03-01 | 2021-02-02 | 中国人民解放军战略支援部队信息工程大学 | 一种粗粒度可重构密码逻辑阵列 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1760826A (zh) | 2006-04-19 |
| JP2006114036A (ja) | 2006-04-27 |
| US7237094B2 (en) | 2007-06-26 |
| US20060101241A1 (en) | 2006-05-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071226 Termination date: 20110708 |