CN100353356C - Data configuration system - Google Patents
Data configuration system Download PDFInfo
- Publication number
- CN100353356C CN100353356C CNB2004100554564A CN200410055456A CN100353356C CN 100353356 C CN100353356 C CN 100353356C CN B2004100554564 A CNB2004100554564 A CN B2004100554564A CN 200410055456 A CN200410055456 A CN 200410055456A CN 100353356 C CN100353356 C CN 100353356C
- Authority
- CN
- China
- Prior art keywords
- configuration module
- configuration
- module
- data
- order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The present invention discloses a data configuration system which relates to chip technology. The data configuration system can thoroughly eliminate the problem of overmany data output lines of a master configuration module, and can solve the problems of too long decode module delay, insufficient driving of multiplexer, difficulties in design and wire laying resulted from overcrowded registers, etc. The data configuration system has the advantages that the master configuration module is in annular connection with slave configuration modules, and the master configuration module is connected with the slave configuration module only by read-write data lines, so the design complexity of a chip system is effectively reduced.
Description
Technical field
The present invention relates to chip technology, particularly the data configuration technology.
Background technology
Along with developing rapidly of VLSI (very large scale integrated circuit), transistor size integrated in the single chip is more and more, and its function that can realize also becomes increasingly complex.Particularly, more and more higher to the requirement of single chip processing power along with the continuous maturation of digital signal processor (DigitalSignal Process is called for short " DSP ") and integrated circuit SOC (system on a chip) (System On Chip is called for short " SOC ") technology.Make chip normally carry out work, need carry out necessary configuration each register of its inside and list item according to intended function.
The method that tradition is configured chip internal is to adopt a module that all registers and list item are configured.Fig. 1 is traditional structural representation that chip internal is configured, as shown in the figure.This structure has only been described the interlock circuit structure of central processing unit (Central Processing Unit is called for short " CPU ") when carrying out write operation, mainly comprises central processing unit 10, chip 11.Wherein, comprise configuration module 12 and module group 17 and list item group 18 in the chip 11.Configuration module 12 comprises pretreatment unit 13, address decoding unit 14, multiplexer 15 and registers group 16 again.
Because the configuration order that central processing unit 10 sends comprises address and data usually, pretreatment unit 13 is used for the address of configuration order and data separating, those of ordinary skill in the art should be understood that this processing unit can utilize an impact damper to realize.Impact damper at first receives the whole piece configuration order and with its storage, extracts respectively according to the position of address and data then, thereby finish separating of address and data.
There are certain mutual relationship in registers group 16 and module group 17, the module 1 in the 1 respective modules group 17 of the register in the registers group 16 for example, register 2 respective modules 2, register n respective modules n etc.
Each module and the function thereof of the modular structure synoptic diagram that tradition is configured chip internal have been briefly introduced above.Below its concrete layoutprocedure will be described simply.
When the configuration order of central processing unit 10 arrives configuration module 12, at first analyze by 13 pairs of these configuration orders of pretreatment unit, configuration order is decomposed into address and two parts of data.The address is sent to address decoding unit 14 by address wire and deciphers then, data then are sent to multiplexer 15 by data line, utilize the output of address decoding unit 14 that multiplexer 15 is controlled, thereby data are outputed to relevant register or list item.If output to register, then register will be configured corresponding module according to the corresponding relation between registers group 16 and the module group 17.If output to list item, then directly each list item is configured.
By above-mentioned layoutprocedure as can be seen, write operation of every execution all will at first carry out decoded operation to the address, and the number of register or list item is many more, and decoded operation is just complicated more, and its decoding postpones also big more; Because multiplexer 15 directly is configured register or list item by data line, when the number of register and list item is a lot, will cause multiplexer 15 driving force deficiencies, for example: data line is 32, one when having 100 registers or list item, and multiplexer 15 just needs 3200 outputs, along with the register number increases, the output of multiplexer also is on the increase, and this certainly will cause the difficulty of multiplexer 15 designs more and more higher; When the register number more for a long time, require integrated so multiregister in same module, will certainly cause that register density is too high, causes back end design and difficult wiring; When register or list item number change to some extent, need redesign configuration module, this obviously is unfavorable for design and safeguards.Therefore traditional design that the chip configuration scheme no longer is applicable to complex chip.
In order to address the above problem, a solution had once been proposed, this solution is that classic method is made amendment, and adopts classification to be configured.
Fig. 2 is the structural representation that chip internal is carried out hierarchical arrangement, as shown in the figure.This structure mainly comprises central processing unit 20, chip 21.Its chips 21 comprises main configuration module 22 and from configuration module 23,24,25, wherein, belongs to the submodule of outside other modules from configuration module.
Each module and the function thereof of the structural representation of hierarchical arrangement have simply been described above.Below the detailed process of its configuration will be described briefly.
When the configuration order of central processing unit 20 arrives chip 21, at first transferring to main configuration module 22 handles, according to the address information that is comprised in the configuration order, at first select appropriate module, suppose to find be to be configured from configuration module 23 corresponding modules, then select from configuration module 23, continue the address information of configured separate order from configuration module 23, thereby the corresponding registers or the list item of this inside modules is configured.
By foregoing description as can be seen, hierarchical arrangement is that with the difference of conventional arrangement it adopts a plurality of configuration modules that the register or the list item of chip internal are configured, and has effectively alleviated the processing complexity of single configuration module.For main configuration module, its design complexities depends primarily on the number of modules in the chip; For from configuration module, its design complexities depends primarily on the register or the list item number of this module self, and irrelevant with other modules.Thereby, adopt hierarchical arrangement to help reducing the design complexities of single configuration module, reduce decoding and postpone, can alleviate multiplexer driving force deficiency and problems such as back end design and difficult wiring to a certain extent.
In actual applications, there is following problem in such scheme: when the chip module number more for a long time, can draw equally and conventional arrangement method similar problem.For example number of modules is 30, and the reading and writing data line of each module is respectively 32, and then each all needs 64 data lines to link to each other with main configuration module from configuration module, and main configuration module will be drawn 2000 data lines nearly, and design difficulty is still very big.
Cause the main cause of this situation to be, main configuration module still adopts multiplex mode to the selection from configuration module, and each has all required data line to link to each other between configuration module and main configuration module, finally causes the output data line of main configuration module too much.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of data collocation system, make it possible to thoroughly eliminate the too much problem of main configuration module output data line, and then can solve decoding module and postpone long, multiplexer and drive problems such as not enough, overstocked back end design that causes of register and difficult wiring.
For achieving the above object, the invention provides a kind of data collocation system, it comprises main configuration module and a plurality of from configuration module, each manages at least one register or list item respectively from configuration module, wherein main configuration module will be transmitted to from the configuration order that central processing unit receives from configuration module, dispose the register or the list item of its management from configuration module according to the configuration order that receives, described main configuration module is connected with cyclic structure from configuration module successively with a plurality of, described configuration order from central processing unit according to described cyclic structure through main configuration module serial by a plurality of from configuration module, describedly be transmitted to described central processing unit by a plurality of from configuration module and through main configuration module according to described cyclic structure serial from each response message from configuration module.
Described main configuration module and also comprise the fifo queue storer from configuration module is used for storing configuration order or the response message that cyclic structure upper level configuration module sends.
Described configuration order comprises configuration zone bit, module id, configuration address and the configuration data corresponding with module;
Described response message comprises answer logo position and expression configuration successful whether status information.
Described data collocation system from comprising also between configuration module and a plurality of register or the list item that a plurality of sons are from configuration module, described a plurality of son is divided into one or more groups from configuration module, a plurality of sons of each group describedly are connected with cyclic structure respectively from configuration module with one successively from configuration module, and manage at least one register or list item respectively;
Describedly also be used for receiving from the configuration order of cyclic structure upper level from configuration module or main configuration module from configuration module, whether the operand of judging this configuration order should be from the son in the group of configuration module place from configuration module, if then this configuration order is transmitted in the cyclic structure next stage from configuration module, and, will be transmitted to next stage from configuration module or main configuration module from the response message of configuration module from upper level in the cyclic structure;
Described son is used for receiving from the cyclic structure upper level from configuration module or sub configuration order and response message from configuration module from configuration module, for the described configuration order that sends to this module, response and finish internal data configuration after, next stage sends response message from configuration module or from configuration module in cyclic structure; For the described configuration order that sends to other modules with from the described response message of upper level in the cyclic structure from configuration module, then next stage is transmitted from configuration module or from configuration module in cyclic structure.
By relatively finding, technical scheme difference with the prior art of the present invention is, main configuration module is linked to each other from the configuration module annular with each, and main configuration module and each effectively reduce the complexity of chip system design from only linking to each other by the line that reads and writes data between the configuration module.
Difference on this technical scheme, brought comparatively significantly beneficial effect, promptly constitute single loop or a plurality of loop with each from configuration module by leading configuration, make the design of main configuration module be no longer dependent on number from configuration module, fundamentally having solved decoding postpones excessive, multiplexer drives not enough, and the problem of overstocked back end design of bringing of register and wiring.
Description of drawings
Fig. 1 is traditional data collocation system structural representation;
Fig. 2 is the structural representation that in the prior art chip internal is carried out hierarchical arrangement;
Fig. 3 is the structural representation of data collocation system according to an embodiment of the invention;
Fig. 4 is the workflow diagram of data collocation system according to an embodiment of the invention;
Fig. 5 is a configuration order data structure synoptic diagram of realizing loop configurations according to an embodiment of the invention;
Fig. 6 is a response message data structure synoptic diagram of realizing loop configurations according to an embodiment of the invention;
Fig. 7 is that the interface configuration message that realizes loop configurations is according to an embodiment of the invention transmitted synoptic diagram.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 3 is the structural representation of data collocation system according to an embodiment of the invention.As shown in the figure, this system is connected with central processing unit 30.Wherein data collocation system 31 comprises main configuration module 32 and from configuration module 33,34,35.Main configuration module 32 with link to each other by loop configuration from configuration module 33,34,35.
Wherein, main configuration module 32 is used for linking to each other with central processing unit 30, receives configuration order that central processing unit 30 sends over and to its echo reply message.Portion can in this case, also need to be provided with code translator by traditional local global register or list item of collocation method configuration within it.
On the other hand, main configuration module 32 with link to each other from configuration module 33,34,35 loop successively, wherein, each receives response message or configuration data from configuration module from a last module.If the response message of receiving then is transmitted to it next stage configuration module; If receive configuration order, judge then whether this configuration order is to be configured working as front module, if not, then this configuration order is forwarded to next module, if then carry out data configuration, and the response message that will dispose sends to next module.In the present embodiment, judge being configured from whether the sign of configuration module by more current configuration module be identical with the module id that comprises the configuration order when front module; If different, then expression is not.
Owing to adopt loop to link to each other, configuration order need be through loop one circle, and therefore the order of connection for each module has no requirement.Similar from the 26S Proteasome Structure and Function of configuration module from the 26S Proteasome Structure and Function of configuration module 33,34,35 and Fig. 2, be used for the register or the list item of each corresponding module are configured.
The function and the annexation of various piece in the data collocation system according to an embodiment of the invention have briefly been described above, owing to adopt annular to connect, only need the data line connection of some to get final product between the adjacent block, for example, if the reading and writing data line of each module is respectively 32, then only need 64 data lines that above-mentioned each module is connected into loop, thereby can effectively reduce the data line number of main configuration module output
To describe in detail below and adopt above-mentioned data collocation system to carry out the flow process of data configuration.As shown in Figure 4:
When the configuration order of central processing unit 30 arrives data collocation system 31, at first enter step 410, receive by main configuration module 32.Those of ordinary skill in the art are appreciated that, because configuration order will be passed through whole loop, each module by whole loop is selected, so this configuration order should comprise configuration zone bit, module id information, the configuration address information corresponding with module and the data that are used to be configured.
Fig. 5 is for realizing the configuration order data structure synoptic diagram of loop configurations according to an embodiment of the invention, as shown in the figure.This configuration order is 32 a configuration order.Wherein the first place of first long word (the 31st) is 0, represents this order to be configuration order; 24 to 30 of first long word is the command operation sign indicating number, is used to show that the operation of current execution is read operation or write operation, or other operations; Represent module id for 16 to 23 of first long word, be used to show that this configuration is that the module corresponding with this module id is configured, owing to only represent that this allocation plan can only be configured 256 modules at most with 8; Represent configuration messages length for 8 to 15 of first long word, owing to only use 8 bit representations, therefore the longest can be 256 long words; 0 to 7 of first long word for keeping the position.Second long word of this data structure is the address, is used for representing register to be configured or the list item position in module.Other long words all are configuration datas.
Enter step 420 then, judge whether it is configuration order, if then enter step 430; If not then entering step 470.Those of ordinary skill in the art can know, can realize that to the judgement of configuration order represent configuration order with 0 in for example above-mentioned configuration order structural representation, 1 expression is not a configuration order by the configuration zone bit in the configuration order.In this step, what main configuration module 32 received may be response message, and this will be described hereinafter.
Step 430 judges that whether this configuration order is that register or list item when front module are configured, if then enter step 440, is configured register or list item when front module; If not then entering step 460, directly configuration order is sent to next stage configuration module when front module.As mentioned above, deterministic process can be by more current configuration module sign whether with configuration order in identical realization of module id that comprise, if the sign of current configuration module is identical with module id information in the configuration order, then expression is to being configured when front module; If different, then expression is not.
In step 440, configuration address information that is comprised in according to configuration order when front module and configuration data are configured the register or the list item of its inside.In the concrete configuration process, can adopt traditional allocation plan.After finishing, configuration enters step 450.
In step 450, the response message after front module will dispose sends to the next stage module.Described response message should comprise respond flag and be used to represent configuration successful whether status information.After this enter step 480.
Fig. 6 is the response message data structure synoptic diagram of realizing loop configurations according to an embodiment of the invention.As shown in the figure, this response message also is 32 bit data forms, and wherein the first place of first long word (the 31st) is 1, and being used to represent this message is response message, and last 8 (0 to 7) of first long word are status information, and whether the expression configuration is successful.Those of ordinary skill in the art can know, if configuration makes mistakes, can determine the different types of makeing mistakes by different rreturn values.Other parts of this response message data structure are identical with configuration order data structure shown in Figure 5.
After step 460 directly sends to the next stage configuration module with configuration order, enter step 480.
After step 470 directly sends to the next stage configuration module with order, enter step 480.
In step 480, above-mentioned next stage configuration module is set to work as front module, and judges whether it is main configuration module, if then enter step 490; If not, then continue to return step 420, continue current configuration module is operated.This shows, when deserving after front module receives the response message of previous stage module, also forward this information to the next stage module, till this response message is passed to main configuration module 32, thereby this response message is returned to central processing unit 30 by main configuration module 32.On the other hand, the configuration order from central processing unit 30 also is passed in this way accordingly from configuration module.
Step 490 is used for response message is returned to central processing unit, and the expression configuration is finished.Need to prove that if configuration makes mistakes, central processing unit then can be operated accordingly according to different type of errors.
Also need to prove, when actual being configured, the sequential that a data buffer comes control interface need be set in each configuration module, guarantee that write operation can carry out smoothly.Those of ordinary skill in the art can know that data buffer can be to adopt random access memory (Random AccessMemory is called for short " RAM ") or pushup storage (First In First Out is called for short " FIFO ") to realize.RAM memory capacity is bigger in general, but need carry out address selection; The FIFO memory span is less, can operate fairly simple according to the order output data that writes data.In the configuration embodiment of this paper, owing to only need handle the information that the prime configuration module is sent here, the general message of storage that only needs is so can adopt the FIFO storer to be configured.
In addition, reality use constantly different, the FIFO storer can be respectively as command interface with reply interface.Fig. 7 is the interface configuration message that realizes loop configurations according to an embodiment of the invention and transmits synoptic diagram, as shown in the figure.Mainly form in this synoptic diagram by three FIFO storeies 50,51,52.The corresponding configuration module of each FIFO storer.
Wherein, the full signal 501 of command interface is sent by FIFO storer 51, is used to represent that whether FIFO storer 51 is just in deal with data.Those of ordinary skill in the art should be understood that this signal can adopt one digit number to represent according to the position, and 0 expression is empty, and 1 expression is full.
Command interface write signal 502 and command interface data-signal 503 are sent by the prime of FIFO storer 51, and FIFO storer 51 is configured.Wherein command interface write signal 502 can be with one digit number according to bit representation, and expression FIFO storer 51 can write data.Command interface data-signal 503 is data that prime sends.When above-mentioned two signals are effective simultaneously, can transmit data.
Reply the full signal 504 of interface and send, be used to represent that whether FIFO storer 52 is just in deal with data by next stage FIFO storer 52.
Reply interface write signal 505 and reply interface data signal 506 and send to FIFO storer 52 by FIFO storer 51.FIFO storer 52 is configured.Wherein replying interface write signal 505 can be with one digit number according to bit representation, and expression FIFO storer 52 can write data.Replying interface data signal 506 is that the data in the FIFO storer 51 are passed toward FIFO storer 52.
Because FIFO storer 51 need obtain data and handle from the upper level module, this moment, FIFO storer 51 was as command interface.In processing procedure, judge at first whether the full signal 501 of command interface is effective, if the full signal of command interface is effective, expression FIFO storer 51 can not write configuration order to it just in deal with data; If the full signal of command interface be empty, then put command interface write signal 502 and command interface data-signal 503 is effective, thus the data that reception FIFO storer 50 sends.
Data will transmit data to next stage after handling in through FIFO storer 51 pairing modules, this moment, FIFO storer 51 was as replying interface, its processing procedure and similar as the processing procedure of command interface.At first judge whether and to transmit data to the next stage module,, carry out and wait for operation if, then represent the next stage module just in deal with data for full by replying the full signal of interface; If be empty, then put and reply interface write signal 505 and reply the interface data signal effective, send data to the next stage configuration module, finish the transmittance process of data.
In the actual disposition process, configuration order need travel through configuration modules all in the whole loop, therefore processing delay can be bigger, in order to address this problem, can adopt The pipeline design to the intermodules at different levels of configuration bus, be that central processing unit adopts certain time interval to send data, need not to wait for that just carrying out the second time after the response message that receives previous configuration order disposes.Should the time interval by appropriate design, the time delay of strict each module of control, can reduce processing delay effectively.Those of ordinary skill in the art should be understood that the above-mentioned time interval is greater than configuration module at least and carries out the needed time of one's own configuration order.
In addition,, can divide into groups, in each group, dispose a son from configuration module and a plurality of next level from configuration module to each configuration module in order further to reduce time delay.Between configuration module, adopt loop configurations (be similar to Fig. 3 main configuration module and from the relation between the configuration module) from configuration module and a plurality of son in each group, form the experimental process loop, subsequently each subloop is also adopted loop configurations to form major loop, thereby form a kind of multiring structure.Have only when configuration order be just to travel through subloop when a certain module in the subring is configured, otherwise will can not travel through subloop.
In each group, be equivalent to the function of main configuration module Fig. 3 from the function of configuration module, son is equivalent to Fig. 3 function from configuration module from the function of configuration module.
This multiring structure combines the advantage of hierarchy and loop configuration, can further reduce time delay, can satisfy the requirement of any complication system.
Though by reference some preferred embodiment of the present invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that, can do various changes to it in the form and details, and the spirit and scope of the present invention that do not depart from appended claims and limited.
Claims (4)
1. data collocation system, it comprises main configuration module and a plurality of from configuration module, each manages at least one register or list item respectively from configuration module, wherein main configuration module will be transmitted to from the configuration order that central processing unit receives from configuration module, dispose the register or the list item of its management from configuration module according to the configuration order that receives, it is characterized in that, described main configuration module is connected with cyclic structure from configuration module successively with a plurality of, described configuration order from central processing unit according to described cyclic structure through main configuration module serial by a plurality of from configuration module, describedly be transmitted to described central processing unit by a plurality of from configuration module and through main configuration module according to described cyclic structure serial from each response message from configuration module.
2. data collocation system according to claim 1 is characterized in that, described main configuration module and also comprise the fifo queue storer from configuration module is used for storing configuration order or the response message that cyclic structure upper level configuration module sends.
3. data collocation system according to claim 1 is characterized in that, described configuration order comprises configuration zone bit, module id, configuration address and the configuration data corresponding with module;
Described response message comprises answer logo position and expression configuration successful whether status information.
4. data collocation system according to claim 1, it is characterized in that, described data collocation system from comprising also between configuration module and a plurality of register or the list item that a plurality of sons are from configuration module, described a plurality of son is divided into one or more groups from configuration module, a plurality of sons of each group describedly are connected with cyclic structure respectively from configuration module with one successively from configuration module, and manage at least one register or list item respectively;
Describedly also be used for receiving from the configuration order of cyclic structure upper level from configuration module or main configuration module from configuration module, whether the operand of judging this configuration order should be from the son in the group of configuration module place from configuration module, if then this configuration order is transmitted in the cyclic structure next stage from configuration module, and, will be transmitted to the cyclic structure next stage from configuration module or main configuration module from the response message of configuration module from upper level;
Described son is used for receiving from the cyclic structure upper level from configuration module or sub configuration order and response message from configuration module from configuration module, for the described configuration order that sends to this module, response and finish internal data configuration after, next stage sends response message from configuration module or from configuration module in cyclic structure; For the described configuration order that sends to other modules with from the described response message of upper level in the cyclic structure from configuration module, then next stage is transmitted from configuration module or from configuration module in cyclic structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100554564A CN100353356C (en) | 2004-08-06 | 2004-08-06 | Data configuration system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100554564A CN100353356C (en) | 2004-08-06 | 2004-08-06 | Data configuration system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1731384A CN1731384A (en) | 2006-02-08 |
| CN100353356C true CN100353356C (en) | 2007-12-05 |
Family
ID=35963739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100554564A Active CN100353356C (en) | 2004-08-06 | 2004-08-06 | Data configuration system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100353356C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101174985B (en) * | 2007-09-28 | 2010-11-10 | 华为技术有限公司 | Method and device for recovering configuration information |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6507943B1 (en) * | 2000-09-26 | 2003-01-14 | Xilinx, Inc. | Method of compressing a bitstream of an FPGA |
| CN1400772A (en) * | 2001-08-03 | 2003-03-05 | 华为技术有限公司 | Method for making data layout in communication equipment and its system |
| US20040103098A1 (en) * | 2002-11-21 | 2004-05-27 | Microsoft Corporation | Synchronizing centralized data store from distributed independent data stores using fixed application programming interfaces |
-
2004
- 2004-08-06 CN CNB2004100554564A patent/CN100353356C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6507943B1 (en) * | 2000-09-26 | 2003-01-14 | Xilinx, Inc. | Method of compressing a bitstream of an FPGA |
| CN1400772A (en) * | 2001-08-03 | 2003-03-05 | 华为技术有限公司 | Method for making data layout in communication equipment and its system |
| US20040103098A1 (en) * | 2002-11-21 | 2004-05-27 | Microsoft Corporation | Synchronizing centralized data store from distributed independent data stores using fixed application programming interfaces |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1731384A (en) | 2006-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1025382C (en) | Device driver system having generic operating system interface | |
| CN100504827C (en) | Establishing command order in an out of order dma command queue | |
| CN101996147B (en) | Method for realizing dual-port RAM (Random-Access memory) mutual exclusion access | |
| CN100499556C (en) | High-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor | |
| CN100440183C (en) | Inter-processor communication system | |
| JPS58500145A (en) | Interrupt concatenation and monitoring system | |
| TW521186B (en) | Sequencing method for accessing shared system resources and its bridging system | |
| CN102981984A (en) | Use of completer knowledge of memory region ordering requirements to modify transaction attributes | |
| US7181561B2 (en) | Ordering rule controlled command storage | |
| CN101436171B (en) | Modular communication control system | |
| CN101515261A (en) | Data transfer between devices within an integrated circuit | |
| JPH05205005A (en) | Host-interface for logic-simulation-machine | |
| CN102035658A (en) | High-speed 1553B fiber bus IP core | |
| CN101430739B (en) | System and method for parameter collocation of integrated chip | |
| CN101689159B (en) | Token protocol | |
| EP2899644A1 (en) | Device and method for inter-core communication in multi-core processor | |
| CN116661703B (en) | Memory access circuit, memory access method, integrated circuit, and electronic device | |
| CN100353356C (en) | Data configuration system | |
| US9367493B2 (en) | Method and system of communicating between peer processors in SoC environment | |
| WO1999022296A2 (en) | Method and system for synchronizing block-organized data transfer | |
| US20070280224A1 (en) | System and method for an output independent crossbar | |
| CN116521096A (en) | Memory access circuit, memory access method, integrated circuit, and electronic device | |
| CN101303687A (en) | Method for implementing chip-on communication of built-in isomerization multicore architecture | |
| US7035908B1 (en) | Method for multiprocessor communication within a shared memory architecture | |
| WO2000043896A1 (en) | Command reordering for out of order bus transfer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |